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-rw-r--r--src/arch/arm/isa.hh5
-rw-r--r--src/arch/arm/miscregs.cc5
2 files changed, 9 insertions, 1 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 89c673e4b..65d2251f8 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -229,6 +229,11 @@ namespace ArmISA
privNonSecure(v);
return *this;
}
+ chain privRead(bool v = true) const {
+ privSecureRead(v);
+ privNonSecureRead(v);
+ return *this;
+ }
chain hypRead(bool v = true) const {
info[MISCREG_HYP_RD] = v;
return *this;
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index ebe72dd52..1eee78116 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3165,7 +3165,10 @@ ISA::initializeMiscRegMetadata()
.bankedChild()
.secure().exceptUserMode();
InitReg(MISCREG_MVBAR)
- .mon().secure().exceptUserMode();
+ .mon().secure()
+ .hypRead(FullSystem && system->highestEL() == EL2)
+ .privRead(FullSystem && system->highestEL() == EL1)
+ .exceptUserMode();
InitReg(MISCREG_RMR)
.unimplemented()
.mon().secure().exceptUserMode();