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-rw-r--r--src/SConscript1
-rw-r--r--src/arch/alpha/isa/decoder.isa6
-rw-r--r--src/cpu/o3/cpu.cc8
-rwxr-xr-xsrc/cpu/o3/thread_context.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh6
-rw-r--r--src/cpu/simple/atomic.cc10
-rw-r--r--src/cpu/simple/timing.cc10
-rw-r--r--src/cpu/thread_context.hh4
-rw-r--r--src/cpu/thread_state.cc16
-rw-r--r--src/cpu/thread_state.hh6
-rw-r--r--src/mem/bus.cc2
-rw-r--r--src/mem/cache/cache_impl.hh19
-rw-r--r--src/mem/cache/coherence/simple_coherence.hh4
-rw-r--r--src/mem/cache/coherence/uni_coherence.cc33
-rw-r--r--src/mem/cache/coherence/uni_coherence.hh2
15 files changed, 99 insertions, 30 deletions
diff --git a/src/SConscript b/src/SConscript
index 9d54174ab..429e1bee1 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -333,6 +333,7 @@ makeEnv('fast', '.fo', strip = True,
# Profiled binary
makeEnv('prof', '.po',
CCFLAGS = Split('-O3 -g -pg'),
+ CPPDEFINES = ['NDEBUG', 'TRACING_ON=0'],
LINKFLAGS = '-pg')
Return('envList')
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 7014d4c22..6df47ef7a 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -795,6 +795,12 @@ decode OPCODE default Unknown::unknown() {
0x04: quiesceTime({{
R0 = AlphaPseudo::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
+ 0x10: ivlb({{
+ warn_once("Obsolete M5 instruction ivlb encountered.\n");
+ }});
+ 0x11: ivle({{
+ warn_once("Obsolete M5 instruction ivlb encountered.\n");
+ }});
0x20: m5exit_old({{
AlphaPseudo::m5exit_old(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 3dc353a9f..a5a00015f 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -497,8 +497,6 @@ FullO3CPU<Impl>::init()
}
#if FULL_SYSTEM
- src_tc->init();
-
TheISA::initCPU(src_tc, src_tc->readCpuId());
#endif
}
@@ -554,6 +552,12 @@ template <class Impl>
void
FullO3CPU<Impl>::activateContext(int tid, int delay)
{
+#if FULL_SYSTEM
+ // Connect the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ threadContexts[tid]->connectMemPorts();
+#endif
+
// Needs to set each stage to running as well.
if (delay){
DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 031f36480..390569c3d 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -92,7 +92,7 @@ class O3ThreadContext : public ThreadContext
void delVirtPort(VirtualPort *vp);
- virtual void init() { thread->init(); }
+ virtual void connectMemPorts() { thread->connectMemPorts(); }
#else
virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 0180756e3..afebf294f 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -101,8 +101,10 @@ template <class Impl>
void
O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
{
- delete vp->getPeer();
- delete vp;
+ if (vp != thread->getVirtPort()) {
+ delete vp->getPeer();
+ delete vp;
+ }
}
#endif
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b7699c405..67611e815 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -78,9 +78,6 @@ AtomicSimpleCPU::init()
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
- // initialize the mem pointers
- tc->init();
-
// initialize CPU, including PC
TheISA::initCPU(tc, tc->readCpuId());
}
@@ -241,6 +238,13 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
assert(!tickEvent.scheduled());
notIdleFraction++;
+
+#if FULL_SYSTEM
+ // Connect the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ tc->connectMemPorts();
+#endif
+
//Make sure ticks are still on multiples of cycles
tickEvent.schedule(nextCycle(curTick + cycles(delay)));
_status = Running;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index aa23a00e8..dfffb0b1f 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -59,9 +59,6 @@ TimingSimpleCPU::init()
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
- // initialize the mem pointers
- tc->init();
-
// initialize CPU, including PC
TheISA::initCPU(tc, tc->readCpuId());
}
@@ -241,6 +238,13 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
notIdleFraction++;
_status = Running;
+
+#if FULL_SYSTEM
+ // Connect the ThreadContext's memory ports (Functional/Virtual
+ // Ports)
+ tc->connectMemPorts();
+#endif
+
// kick things off by initiating the fetch of the next instruction
fetchEvent =
new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index baeb7a8be..bb9cc9e16 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -134,7 +134,7 @@ class ThreadContext
virtual void delVirtPort(VirtualPort *vp) = 0;
- virtual void init() = 0;
+ virtual void connectMemPorts() = 0;
#else
virtual TranslatingPort *getMemPort() = 0;
@@ -308,7 +308,7 @@ class ProxyThreadContext : public ThreadContext
void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
- void init() {actualTC->init(); }
+ void connectMemPorts() { actualTC->connectMemPorts(); }
#else
TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index 9cac4fd26..93dd1e2eb 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -113,23 +113,29 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
#if FULL_SYSTEM
void
-ThreadState::init()
+ThreadState::connectMemPorts()
{
- initPhysPort();
- initVirtPort();
+ connectPhysPort();
+ connectVirtPort();
}
void
-ThreadState::initPhysPort()
+ThreadState::connectPhysPort()
{
+ // @todo: For now this disregards any older port that may have
+ // already existed. Fix this memory leak once the bus port IDs
+ // for functional ports is resolved.
physPort = new FunctionalPort(csprintf("%s-%d-funcport",
baseCpu->name(), tid));
connectToMemFunc(physPort);
}
void
-ThreadState::initVirtPort()
+ThreadState::connectVirtPort()
{
+ // @todo: For now this disregards any older port that may have
+ // already existed. Fix this memory leak once the bus port IDs
+ // for functional ports is resolved.
virtPort = new VirtualPort(csprintf("%s-%d-vport",
baseCpu->name(), tid));
connectToMemFunc(virtPort);
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 1844be8b7..4f878db1f 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -91,11 +91,11 @@ struct ThreadState {
Tick readLastSuspend() { return lastSuspend; }
#if FULL_SYSTEM
- void init();
+ void connectMemPorts();
- void initPhysPort();
+ void connectPhysPort();
- void initVirtPort();
+ void connectVirtPort();
void dumpFuncProfile();
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 6b5b63f50..e9a870b80 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -296,7 +296,7 @@ Bus::findPort(Addr addr, int id)
// we shouldn't be sending this back to where it came from
- // only on a functional access and then we should terminate
+ // do the snoop access and then we should terminate
// the cyclical call.
if (dest_id == id)
return 0;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index df59b0a4f..3a681bc52 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -391,7 +391,13 @@ Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
}
//Send a timing (true) invalidate up if the protocol calls for it
- coherence->propogateInvalidate(pkt, true);
+ if (coherence->propogateInvalidate(pkt, true)) {
+ //Temp hack, we had a functional read hit in the L1, mark as success
+ pkt->flags |= SATISFIED;
+ pkt->result = Packet::Success;
+ respondToSnoop(pkt, curTick + hitLatency);
+ return;
+ }
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt);
@@ -562,6 +568,7 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
PacketList writebacks;
int lat;
+
BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(),
@@ -615,7 +622,8 @@ Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
// Can't handle it, return request unsatisfied.
panic("Atomic access ran into outstanding MSHR's or WB's!");
}
- if (!pkt->req->isUncacheable()) {
+ if (!pkt->req->isUncacheable() /*Uncacheables just go through*/
+ && (pkt->cmd != Packet::Writeback)/*Writebacks on miss fall through*/) {
// Fetch the cache block to fill
BlkType *blk = tags->findBlock(pkt);
Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
@@ -691,7 +699,12 @@ Tick
Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
{
//Send a atomic (false) invalidate up if the protocol calls for it
- coherence->propogateInvalidate(pkt, false);
+ if (coherence->propogateInvalidate(pkt, false)) {
+ //Temp hack, we had a functional read hit in the L1, mark as success
+ pkt->flags |= SATISFIED;
+ pkt->result = Packet::Success;
+ return hitLatency;
+ }
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt);
diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh
index 5316e64b9..a1fd33080 100644
--- a/src/mem/cache/coherence/simple_coherence.hh
+++ b/src/mem/cache/coherence/simple_coherence.hh
@@ -161,10 +161,10 @@ class SimpleCoherence
bool hasProtocol() { return true; }
- void propogateInvalidate(PacketPtr pkt, bool isTiming)
+ bool propogateInvalidate(PacketPtr pkt, bool isTiming)
{
//For now we do nothing, asssumes simple coherence is top level of cache
- return;
+ return false;
}
};
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index 19230e35b..ea615d70a 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -54,6 +54,7 @@ UniCoherence::sendResult(PacketPtr &pkt, MSHR* cshr, bool success)
{
bool unblock = cshrs.isFull();
// cshrs.markInService(cshr);
+ delete pkt->req;
cshrs.deallocate(cshr);
if (!cshrs.havePending()) {
cache->clearSlaveRequest(Request_Coherence);
@@ -81,17 +82,24 @@ UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr,
}
else if (blk) {
new_state = blk->status;
+ if (pkt->isRead()) {
+ DPRINTF(Cache, "Uni-coherence snoops a read that hit in itself"
+ ". Should satisfy the packet\n");
+ return true; //Satisfy Reads if we can
+ }
}
return false;
}
-void
+bool
UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming)
{
if (pkt->isInvalidate()) {
+/* Temp Fix for now, forward all invalidates up as functional accesses */
if (isTiming) {
// Forward to other caches
- PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+ Request* req = new Request(pkt->req->getPaddr(), pkt->getSize(), 0);
+ PacketPtr tmp = new Packet(req, Packet::InvalidateReq, -1);
cshrs.allocate(tmp);
cache->setSlaveRequest(Request_Coherence, curTick);
if (cshrs.isFull())
@@ -102,5 +110,26 @@ UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming)
cache->cpuSidePort->sendAtomic(tmp);
delete tmp;
}
+/**/
+/* PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+ cache->cpuSidePort->sendFunctional(tmp);
+ delete tmp;
+*/
+ }
+ if (pkt->isRead()) {
+ /*For now we will see if someone above us has the data by
+ doing a functional access on reads. Fix this later */
+ PacketPtr tmp = new Packet(pkt->req, Packet::ReadReq, -1);
+ tmp->allocate();
+ cache->cpuSidePort->sendFunctional(tmp);
+ bool hit = (tmp->result == Packet::Success);
+ if (hit) {
+ memcpy(pkt->getPtr<uint8_t>(), tmp->getPtr<uint8_t>(),
+ pkt->getSize());
+ DPRINTF(Cache, "Uni-coherence snoops a read that hit in L1\n");
+ }
+ delete tmp;
+ return hit;
}
+ return false;
}
diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh
index 44c752088..9a4aacdec 100644
--- a/src/mem/cache/coherence/uni_coherence.hh
+++ b/src/mem/cache/coherence/uni_coherence.hh
@@ -140,7 +140,7 @@ class UniCoherence
bool hasProtocol() { return false; }
- void propogateInvalidate(PacketPtr pkt, bool isTiming);
+ bool propogateInvalidate(PacketPtr pkt, bool isTiming);
};
#endif //__UNI_COHERENCE_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 16:48:10 +0000