diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mem/DRAMCtrl.py | 13 | ||||
| -rw-r--r-- | src/mem/dram_ctrl.cc | 17 | ||||
| -rw-r--r-- | src/mem/dram_ctrl.hh | 1 |
3 files changed, 23 insertions, 8 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index 62d237cfb..e729e9d78 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -135,6 +135,9 @@ class DRAMCtrl(AbstractMemory): # minimum time between a write data transfer and a precharge tWR = Param.Latency("Write recovery time") + # minimum time between a read and precharge command + tRTP = Param.Latency("Read to precharge") + # time to complete a burst transfer, typically the burst length # divided by two due to the DDR bus, but by making it a parameter # it is easier to also evaluate SDR memories like WideIO. @@ -198,6 +201,7 @@ class DDR3_1600_x64(DRAMCtrl): tRP = '13.75ns' tRAS = '35ns' tWR = '15ns' + tRTP = '7.5ns' # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. # Note this is a BL8 DDR device. @@ -257,6 +261,7 @@ class DDR3_1333_x64_DRAMSim2(DRAMCtrl): tRP = '15ns' tRAS = '36ns' tWR = '15ns' + tRTP = '7.5ns' # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. # Note this is a BL8 DDR device. @@ -314,6 +319,9 @@ class LPDDR2_S4_1066_x32(DRAMCtrl): tRAS = '42ns' tWR = '15ns' + # 6 CK read to precharge delay + tRTP = '11.256ns' + # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. # Note this is a BL8 DDR device. # Requests larger than 32 bytes are broken down into multiple requests @@ -365,6 +373,8 @@ class WideIO_200_x128(DRAMCtrl): tRP = '18ns' tRAS = '42ns' tWR = '15ns' + # Read to precharge is same as the burst + tRTP = '20ns' # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. # Note this is a BL4 SDR device. @@ -420,6 +430,9 @@ class LPDDR3_1600_x32(DRAMCtrl): tRAS = '42ns' tWR = '15ns' + # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns + tRTP = '7.5ns' + # Pre-charge one bank 15 ns (all banks 18 ns) tRP = '15ns' diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc index dd4b254ee..19a03b834 100644 --- a/src/mem/dram_ctrl.cc +++ b/src/mem/dram_ctrl.cc @@ -76,7 +76,7 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : writesThisTime(0), readsThisTime(0), tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR), - tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), + tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), tXAW(p->tXAW), activationLimit(p->activation_limit), memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), pageMgmt(p->page_policy), @@ -560,9 +560,10 @@ DRAMCtrl::printParams() const "tWTR %d ticks\n" \ "tRTW %d ticks\n" \ "tWR %d ticks\n" \ + "tRTP %d ticks\n" \ "tXAW (%d) %d ticks\n", name(), tRCD, tCL, tRP, tBURST, tRFC, tREFI, tWTR, - tRTW, tWR, activationLimit, tXAW); + tRTW, tWR, tRTP, activationLimit, tXAW); } void @@ -993,12 +994,12 @@ DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) // read/write (add a max with tCCD here) bank.colAllowedAt = cmd_at + tBURST; - // If this is a write, we also need to respect the write - // recovery time before a precharge - if (!dram_pkt->isRead) { - bank.preAllowedAt = std::max(bank.preAllowedAt, - dram_pkt->readyTime + tWR); - } + // If this is a write, we also need to respect the write recovery + // time before a precharge, in the case of a read, respect the + // read to precharge constraint + bank.preAllowedAt = std::max(bank.preAllowedAt, + dram_pkt->isRead ? cmd_at + tRTP : + dram_pkt->readyTime + tWR); // increment the bytes accessed and the accesses per row bank.bytesAccessed += burstSize; diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index c3ce9dc97..ae55a2d13 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -486,6 +486,7 @@ class DRAMCtrl : public AbstractMemory const Tick tRP; const Tick tRAS; const Tick tWR; + const Tick tRTP; const Tick tRFC; const Tick tREFI; const Tick tRRD; |