diff options
Diffstat (limited to 'src')
67 files changed, 159 insertions, 204 deletions
diff --git a/src/arch/alpha/linux/linux.cc b/src/arch/alpha/linux/linux.cc index bc0d48e0d..e6908a572 100644 --- a/src/arch/alpha/linux/linux.cc +++ b/src/arch/alpha/linux/linux.cc @@ -30,6 +30,8 @@ #include "arch/alpha/linux/linux.hh" +#include <fcntl.h> + // open(2) flags translation table OpenFlagTransTable AlphaLinux::openFlagTable[] = { #ifdef _MSC_VER diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa index 9db3108b4..8c89fbfa2 100644 --- a/src/arch/mips/isa/formats/branch.isa +++ b/src/arch/mips/isa/formats/branch.isa @@ -36,7 +36,6 @@ output header {{ #include <iostream> - using namespace std; /** * Base class for instructions whose disassembly is not purely a diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa index 56a4ec204..654dd8921 100644 --- a/src/arch/mips/isa/formats/int.isa +++ b/src/arch/mips/isa/formats/int.isa @@ -34,7 +34,6 @@ // output header {{ #include <iostream> - using namespace std; /** * Base class for integer operations. */ diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa index 9f25c7725..73164bc0d 100644 --- a/src/arch/mips/isa/formats/util.isa +++ b/src/arch/mips/isa/formats/util.isa @@ -133,7 +133,7 @@ output decoder {{ std::string inst2string(MachInst machInst) { - string str = ""; + std::string str = ""; uint32_t mask = 0x80000000; for(int i=0; i < 32; i++) { diff --git a/src/arch/mips/linux/linux.cc b/src/arch/mips/linux/linux.cc index 26e3dd479..90404af53 100644 --- a/src/arch/mips/linux/linux.cc +++ b/src/arch/mips/linux/linux.cc @@ -30,6 +30,8 @@ #include "arch/mips/linux/linux.hh" +#include <fcntl.h> + // open(2) flags translation table OpenFlagTransTable MipsLinux::openFlagTable[] = { #ifdef _MSC_VER diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh index e9447d39e..ce5f1fdde 100644 --- a/src/arch/mips/regfile/float_regfile.hh +++ b/src/arch/mips/regfile/float_regfile.hh @@ -139,7 +139,6 @@ namespace MipsISA Fault setReg(int floatReg, const FloatRegVal &val, int width) { - using namespace std; switch(width) { case SingleWidth: @@ -168,7 +167,6 @@ namespace MipsISA Fault setRegBits(int floatReg, const FloatRegBits &val, int width) { - using namespace std; switch(width) { diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index c2e1c3176..a4527a203 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -31,7 +31,6 @@ #ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ #define __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__ -#include "arch/mips/isa_traits.hh" #include "arch/mips/types.hh" #include "sim/faults.hh" diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index dce015a36..3a18c681b 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -32,7 +32,6 @@ #define __ARCH_MIPS_REGFILE_REGFILE_HH__ #include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" #include "arch/mips/regfile/int_regfile.hh" #include "arch/mips/regfile/float_regfile.hh" #include "arch/mips/regfile/misc_regfile.hh" diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index e7455fdbf..9ac4bb6d8 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -28,15 +28,12 @@ * Authors: Korey Sewell */ -#include "arch/mips/isa_traits.hh" +#include "arch/mips/regfile.hh" #include "arch/mips/utility.hh" -#include "config/full_system.hh" -#include "cpu/static_inst.hh" -#include "sim/serialize.hh" +#include "base/misc.hh" #include "base/bitfield.hh" using namespace MipsISA; -using namespace std; uint64_t MipsISA::fpConvert(ConvertType cvt_type, double fp_val) diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 9558aa235..ae2fe1aea 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -33,12 +33,14 @@ #define __ARCH_MIPS_UTILITY_HH__ #include "arch/mips/types.hh" -#include "arch/mips/isa_traits.hh" #include "base/misc.hh" +#include "config/full_system.hh" //XXX This is needed for size_t. We should use something other than size_t -#include "kern/linux/linux.hh" +//#include "kern/linux/linux.hh" #include "sim/host.hh" +class ThreadContext; + namespace MipsISA { //Floating Point Utility Functions diff --git a/src/arch/sparc/linux/linux.cc b/src/arch/sparc/linux/linux.cc index ae6ffbc2a..1211d5f65 100644 --- a/src/arch/sparc/linux/linux.cc +++ b/src/arch/sparc/linux/linux.cc @@ -29,6 +29,7 @@ */ #include "arch/sparc/linux/linux.hh" +#include <fcntl.h> // open(2) flags translation table OpenFlagTransTable SparcLinux::openFlagTable[] = { diff --git a/src/arch/sparc/linux/process.hh b/src/arch/sparc/linux/process.hh index f4819ba84..4af8f0f75 100644 --- a/src/arch/sparc/linux/process.hh +++ b/src/arch/sparc/linux/process.hh @@ -32,6 +32,7 @@ #define __SPARC_LINUX_PROCESS_HH__ #include "arch/sparc/linux/linux.hh" +#include "arch/sparc/syscallreturn.hh" #include "arch/sparc/process.hh" #include "sim/process.hh" diff --git a/src/arch/sparc/solaris/solaris.cc b/src/arch/sparc/solaris/solaris.cc index c588925b0..c53caa72a 100644 --- a/src/arch/sparc/solaris/solaris.cc +++ b/src/arch/sparc/solaris/solaris.cc @@ -30,6 +30,8 @@ #include "arch/sparc/solaris/solaris.hh" +#include <fcntl.h> + // open(2) flags translation table OpenFlagTransTable SparcSolaris::openFlagTable[] = { #ifdef _MSC_VER diff --git a/src/arch/sparc/syscallreturn.hh b/src/arch/sparc/syscallreturn.hh index fd63a8868..d850f4b65 100644 --- a/src/arch/sparc/syscallreturn.hh +++ b/src/arch/sparc/syscallreturn.hh @@ -33,6 +33,8 @@ #include <inttypes.h> +#include "arch/sparc/regfile.hh" + class SyscallReturn { public: diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index a344990b4..f2109e88d 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -36,15 +36,12 @@ #include "base/cprintf.hh" #include "base/trace.hh" -#include "arch/faults.hh" +#include "sim/faults.hh" #include "cpu/exetrace.hh" #include "mem/request.hh" #include "cpu/base_dyn_inst.hh" -using namespace std; -using namespace TheISA; - #define NOHASH #ifndef NOHASH @@ -65,7 +62,7 @@ my_hash_t thishash; #endif template <class Impl> -BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC, +BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC, Addr pred_PC, InstSeqNum seq_num, ImplCPU *cpu) : staticInst(machInst), traceData(NULL), cpu(cpu) @@ -73,8 +70,8 @@ BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC, seqNum = seq_num; PC = inst_PC; - nextPC = PC + sizeof(MachInst); - nextNPC = nextPC + sizeof(MachInst); + nextPC = PC + sizeof(TheISA::MachInst); + nextNPC = nextPC + sizeof(TheISA::MachInst); predPC = pred_PC; initVars(); @@ -250,7 +247,7 @@ void BaseDynInst<Impl>::dump() { cprintf("T%d : %#08d `", threadNumber, PC); - cout << staticInst->disassemble(PC); + std::cout << staticInst->disassemble(PC); cprintf("'\n"); } diff --git a/src/cpu/o3/2bit_local_pred.hh b/src/cpu/o3/2bit_local_pred.hh index 0a2a71d3e..954b86b4c 100644 --- a/src/cpu/o3/2bit_local_pred.hh +++ b/src/cpu/o3/2bit_local_pred.hh @@ -31,9 +31,8 @@ #ifndef __CPU_O3_2BIT_LOCAL_PRED_HH__ #define __CPU_O3_2BIT_LOCAL_PRED_HH__ -// For Addr type. -#include "arch/isa_traits.hh" #include "cpu/o3/sat_counter.hh" +#include "sim/host.hh" #include <vector> diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index b961341d5..9d97f9701 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -31,7 +31,8 @@ #ifndef __CPU_O3_ALPHA_CPU_HH__ #define __CPU_O3_ALPHA_CPU_HH__ -#include "arch/isa_traits.hh" +#include "arch/regfile.hh" +#include "arch/types.hh" #include "cpu/thread_context.hh" #include "cpu/o3/cpu.hh" #include "sim/byteswap.hh" diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 0473e60c2..c07595024 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -53,8 +53,6 @@ #include "sim/system.hh" #endif -using namespace TheISA; - template <class Impl> AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) #if FULL_SYSTEM diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh index 2c0a39565..3c4c8e478 100644 --- a/src/cpu/o3/bpred_unit.hh +++ b/src/cpu/o3/bpred_unit.hh @@ -31,8 +31,6 @@ #ifndef __CPU_O3_BPRED_UNIT_HH__ #define __CPU_O3_BPRED_UNIT_HH__ -// For Addr type. -#include "arch/isa_traits.hh" #include "base/statistics.hh" #include "cpu/inst_seq.hh" @@ -41,6 +39,8 @@ #include "cpu/o3/ras.hh" #include "cpu/o3/tournament_pred.hh" +#include "sim/host.hh" + #include <list> /** diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh index 8dad42011..e4e656632 100644 --- a/src/cpu/o3/bpred_unit_impl.hh +++ b/src/cpu/o3/bpred_unit_impl.hh @@ -28,15 +28,11 @@ * Authors: Kevin Lim */ -#include <list> -#include <vector> - +#include "arch/types.hh" #include "base/trace.hh" #include "base/traceflags.hh" #include "cpu/o3/bpred_unit.hh" -using namespace std; - template<class Impl> BPredUnit<Impl>::BPredUnit(Params *params) : BTB(params->BTBEntries, diff --git a/src/cpu/o3/btb.cc b/src/cpu/o3/btb.cc index 01640f4d1..93d6ee768 100644 --- a/src/cpu/o3/btb.cc +++ b/src/cpu/o3/btb.cc @@ -32,8 +32,6 @@ #include "base/trace.hh" #include "cpu/o3/btb.hh" -using namespace TheISA; - DefaultBTB::DefaultBTB(unsigned _numEntries, unsigned _tagBits, unsigned _instShiftAmt) diff --git a/src/cpu/o3/btb.hh b/src/cpu/o3/btb.hh index dfa3b7b06..3c4899e89 100644 --- a/src/cpu/o3/btb.hh +++ b/src/cpu/o3/btb.hh @@ -31,9 +31,8 @@ #ifndef __CPU_O3_BTB_HH__ #define __CPU_O3_BTB_HH__ -// For Addr type. -#include "arch/isa_traits.hh" #include "base/misc.hh" +#include "sim/host.hh" class DefaultBTB { diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh index e311910cf..aa58fc20e 100644 --- a/src/cpu/o3/comm.hh +++ b/src/cpu/o3/comm.hh @@ -33,8 +33,7 @@ #include <vector> -#include "arch/faults.hh" -#include "arch/isa_traits.hh" +#include "sim/faults.hh" #include "cpu/inst_seq.hh" #include "sim/host.hh" diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 5caa317b3..7575783f7 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -32,7 +32,6 @@ #ifndef __CPU_O3_COMMIT_HH__ #define __CPU_O3_COMMIT_HH__ -#include "arch/faults.hh" #include "base/statistics.hh" #include "base/timebuf.hh" #include "cpu/exetrace.hh" diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index e51d03994..f200f5f18 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -45,8 +45,6 @@ #include "cpu/checker/cpu.hh" #endif -using namespace std; - template <class Impl> DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid) @@ -87,7 +85,7 @@ DefaultCommit<Impl>::DefaultCommit(Params *params) { _status = Active; _nextStatus = Inactive; - string policy = params->smtCommitPolicy; + std::string policy = params->smtCommitPolicy; //Convert string to lowercase std::transform(policy.begin(), policy.end(), policy.begin(), @@ -236,7 +234,7 @@ DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr) template <class Impl> void -DefaultCommit<Impl>::setThreads(vector<Thread *> &threads) +DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads) { thread = threads; } @@ -297,7 +295,7 @@ DefaultCommit<Impl>::setIEWStage(IEW *iew_stage) template<class Impl> void -DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr) +DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) { DPRINTF(Commit, "Commit: Setting active threads list pointer.\n"); activeThreads = at_ptr; @@ -391,7 +389,7 @@ void DefaultCommit<Impl>::updateStatus() { // reset ROB changed variable - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; changedROBNumEntries[tid] = false; @@ -420,7 +418,7 @@ DefaultCommit<Impl>::setNextStatus() { int squashes = 0; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; @@ -443,7 +441,7 @@ template <class Impl> bool DefaultCommit<Impl>::changedROBEntries() { - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; @@ -570,7 +568,7 @@ DefaultCommit<Impl>::tick() if ((*activeThreads).size() <= 0) return; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); // Check if any of the threads are done squashing. Change the // status if they are done. @@ -688,7 +686,7 @@ DefaultCommit<Impl>::commit() // Check for any possible squashes, handle them first //////////////////////////////////// - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; @@ -1119,10 +1117,10 @@ DefaultCommit<Impl>::getInsts() #if THE_ISA == ALPHA_ISA // Read any renamed instructions and place them into the ROB. - int insts_to_process = min((int)renameWidth, fromRename->size); + int insts_to_process = std::min((int)renameWidth, fromRename->size); #else // Read any renamed instructions and place them into the ROB. - int insts_to_process = min((int)renameWidth, + int insts_to_process = std::min((int)renameWidth, (int)(fromRename->size + skidBuffer.size())); int rename_idx = 0; @@ -1244,7 +1242,7 @@ template <class Impl> bool DefaultCommit<Impl>::robDoneSquashing() { - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; @@ -1341,8 +1339,8 @@ template<class Impl> int DefaultCommit<Impl>::roundRobin() { - list<unsigned>::iterator pri_iter = priority_list.begin(); - list<unsigned>::iterator end = priority_list.end(); + std::list<unsigned>::iterator pri_iter = priority_list.begin(); + std::list<unsigned>::iterator end = priority_list.end(); while (pri_iter != end) { unsigned tid = *pri_iter; @@ -1372,7 +1370,7 @@ DefaultCommit<Impl>::oldestReady() unsigned oldest = 0; bool first = true; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 8c4f663ef..7e18571f1 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -38,7 +38,7 @@ #include <set> #include <vector> -#include "arch/isa_traits.hh" +#include "arch/types.hh" #include "base/statistics.hh" #include "base/timebuf.hh" #include "config/full_system.hh" diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index 0bc6a109f..160845378 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -30,8 +30,6 @@ #include "cpu/o3/decode.hh" -using namespace std; - template<class Impl> DefaultDecode<Impl>::DefaultDecode(Params *params) : renameToDecodeDelay(params->renameToDecodeDelay), @@ -160,7 +158,7 @@ DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr) template<class Impl> void -DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr) +DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) { DPRINTF(Decode, "Setting active threads list pointer.\n"); activeThreads = at_ptr; @@ -426,7 +424,7 @@ template<class Impl> bool DefaultDecode<Impl>::skidsEmpty() { - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { if (!skidBuffer[*threads++].empty()) @@ -442,7 +440,7 @@ DefaultDecode<Impl>::updateStatus() { bool any_unblocking = false; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); threads = (*activeThreads).begin(); @@ -599,7 +597,7 @@ DefaultDecode<Impl>::tick() toRenameIndex = 0; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); sortInsts(); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 274c7c46e..20b89e2a4 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -51,9 +51,6 @@ #include <algorithm> -using namespace std; -using namespace TheISA; - template<class Impl> Tick DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt) @@ -118,7 +115,7 @@ DefaultFetch<Impl>::DefaultFetch(Params *params) // Set fetch stage's status to inactive. _status = Inactive; - string policy = params->smtFetchPolicy; + std::string policy = params->smtFetchPolicy; // Convert string to lowercase std::transform(policy.begin(), policy.end(), policy.begin(), @@ -177,7 +174,7 @@ DefaultFetch<Impl>::DefaultFetch(Params *params) } // Get the size of an instruction. - instSize = sizeof(MachInst); + instSize = sizeof(TheISA::MachInst); } template <class Impl> @@ -317,7 +314,7 @@ DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer) template<class Impl> void -DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr) +DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) { DPRINTF(Fetch, "Setting active threads list pointer.\n"); activeThreads = at_ptr; @@ -739,7 +736,7 @@ typename DefaultFetch<Impl>::FetchStatus DefaultFetch<Impl>::updateFetchStatus() { //Check Running - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { @@ -802,7 +799,7 @@ template <class Impl> void DefaultFetch<Impl>::tick() { - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); bool status_change = false; wroteToTimeBuffer = false; @@ -1350,8 +1347,8 @@ template<class Impl> int DefaultFetch<Impl>::roundRobin() { - list<unsigned>::iterator pri_iter = priorityList.begin(); - list<unsigned>::iterator end = priorityList.end(); + std::list<unsigned>::iterator pri_iter = priorityList.begin(); + std::list<unsigned>::iterator end = priorityList.end(); int high_pri; @@ -1380,9 +1377,9 @@ template<class Impl> int DefaultFetch<Impl>::iqCount() { - priority_queue<unsigned> PQ; + std::priority_queue<unsigned> PQ; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; @@ -1410,10 +1407,10 @@ template<class Impl> int DefaultFetch<Impl>::lsqCount() { - priority_queue<unsigned> PQ; + std::priority_queue<unsigned> PQ; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; @@ -1441,7 +1438,7 @@ template<class Impl> int DefaultFetch<Impl>::branchCount() { - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); panic("Branch Count Fetch policy unimplemented\n"); return *threads; } diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index c4ec93b3e..cdc36c6c3 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -38,8 +38,6 @@ #include "cpu/o3/fu_pool.hh" #include "cpu/o3/iew.hh" -using namespace std; - template<class Impl> DefaultIEW<Impl>::DefaultIEW(Params *params) : issueToExecQueue(params->backComSize, params->forwardComSize), @@ -336,7 +334,7 @@ DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) template<class Impl> void -DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) +DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) { DPRINTF(IEW, "Setting active threads list pointer.\n"); activeThreads = at_ptr; @@ -663,7 +661,7 @@ DefaultIEW<Impl>::skidCount() { int max=0; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned thread_count = skidBuffer[*threads++].size(); @@ -678,7 +676,7 @@ template<class Impl> bool DefaultIEW<Impl>::skidsEmpty() { - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { if (!skidBuffer[*threads++].empty()) @@ -694,7 +692,7 @@ DefaultIEW<Impl>::updateStatus() { bool any_unblocking = false; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); threads = (*activeThreads).begin(); @@ -1195,13 +1193,13 @@ DefaultIEW<Impl>::printAvailableInsts() { int inst = 0; - cout << "Available Instructions: "; + std::cout << "Available Instructions: "; while (fromIssue->insts[inst]) { - if (inst%3==0) cout << "\n\t"; + if (inst%3==0) std::cout << "\n\t"; - cout << "PC: " << fromIssue->insts[inst]->readPC() + std::cout << "PC: " << fromIssue->insts[inst]->readPC() << " TN: " << fromIssue->insts[inst]->threadNumber << " SN: " << fromIssue->insts[inst]->seqNum << " | "; @@ -1209,7 +1207,7 @@ DefaultIEW<Impl>::printAvailableInsts() } - cout << "\n"; + std::cout << "\n"; } template <class Impl> @@ -1219,7 +1217,7 @@ DefaultIEW<Impl>::executeInsts() wbNumInst = 0; wbCycle = 0; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; @@ -1443,7 +1441,7 @@ DefaultIEW<Impl>::tick() // Free function units marked as being freed this cycle. fuPool->processFreeUnits(); - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); // Check stall and squash signals, dispatch any instructions. while (threads != (*activeThreads).end()) { diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 8faae3ebf..e7991662b 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -37,8 +37,6 @@ #include "cpu/o3/fu_pool.hh" #include "cpu/o3/inst_queue.hh" -using namespace std; - template <class Impl> InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, int fu_idx, @@ -100,7 +98,7 @@ InstructionQueue<Impl>::InstructionQueue(Params *params) resetState(); - string policy = params->smtIQPolicy; + std::string policy = params->smtIQPolicy; //Convert string to lowercase std::transform(policy.begin(), policy.end(), policy.begin(), @@ -279,7 +277,7 @@ InstructionQueue<Impl>::regStats() ; for (int i=0; i<Num_OpClasses; ++i) { - stringstream subname; + std::stringstream subname; subname << opClassStrings[i] << "_delay"; issueDelayDist.subname(i, subname.str()); } @@ -359,7 +357,7 @@ InstructionQueue<Impl>::resetState() template <class Impl> void -InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr) +InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) { DPRINTF(IQ, "Setting active threads list pointer.\n"); activeThreads = at_ptr; @@ -421,8 +419,8 @@ InstructionQueue<Impl>::resetEntries() if (iqPolicy != Dynamic || numThreads > 1) { int active_threads = (*activeThreads).size(); - list<unsigned>::iterator threads = (*activeThreads).begin(); - list<unsigned>::iterator list_end = (*activeThreads).end(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator list_end = (*activeThreads).end(); while (threads != list_end) { if (iqPolicy == Partitioned) { diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index 4e3957029..db2c253e1 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -29,12 +29,11 @@ */ #include <algorithm> +#include <list> #include <string> #include "cpu/o3/lsq.hh" -using namespace std; - template <class Impl> Tick LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt) @@ -89,7 +88,7 @@ LSQ<Impl>::LSQ(Params *params) //**********************************************/ //************ Handle SMT Parameters ***********/ //**********************************************/ - string policy = params->smtLSQPolicy; + std::string policy = params->smtLSQPolicy; //Convert string to lowercase std::transform(policy.begin(), policy.end(), policy.begin(), @@ -163,7 +162,7 @@ LSQ<Impl>::regStats() template<class Impl> void -LSQ<Impl>::setActiveThreads(list<unsigned> *at_ptr) +LSQ<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) { activeThreads = at_ptr; assert(activeThreads != 0); @@ -229,8 +228,8 @@ LSQ<Impl>::resetEntries() if (lsqPolicy != Dynamic || numThreads > 1) { int active_threads = (*activeThreads).size(); - list<unsigned>::iterator threads = (*activeThreads).begin(); - list<unsigned>::iterator list_end = (*activeThreads).end(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator list_end = (*activeThreads).end(); int maxEntries; @@ -268,7 +267,7 @@ template<class Impl> void LSQ<Impl>::tick() { - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -317,7 +316,7 @@ template<class Impl> void LSQ<Impl>::writebackStores() { - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -336,7 +335,7 @@ bool LSQ<Impl>::violation() { /* Answers: Does Anybody Have a Violation?*/ - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -353,7 +352,7 @@ LSQ<Impl>::getCount() { unsigned total = 0; - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -369,7 +368,7 @@ LSQ<Impl>::numLoads() { unsigned total = 0; - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -385,7 +384,7 @@ LSQ<Impl>::numStores() { unsigned total = 0; - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -401,7 +400,7 @@ LSQ<Impl>::numLoadsReady() { unsigned total = 0; - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -417,7 +416,7 @@ LSQ<Impl>::numFreeEntries() { unsigned total = 0; - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -441,7 +440,7 @@ template<class Impl> bool LSQ<Impl>::isFull() { - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -468,7 +467,7 @@ template<class Impl> bool LSQ<Impl>::lqFull() { - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -495,7 +494,7 @@ template<class Impl> bool LSQ<Impl>::sqFull() { - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -522,7 +521,7 @@ template<class Impl> bool LSQ<Impl>::isStalled() { - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -547,7 +546,7 @@ template<class Impl> bool LSQ<Impl>::hasStoresToWB() { - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); if ((*activeThreads).empty()) return false; @@ -565,7 +564,7 @@ template<class Impl> bool LSQ<Impl>::willWB() { - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; @@ -580,7 +579,7 @@ template<class Impl> void LSQ<Impl>::dumpInsts() { - list<unsigned>::iterator active_threads = (*activeThreads).begin(); + std::list<unsigned>::iterator active_threads = (*activeThreads).begin(); while (active_threads != (*activeThreads).end()) { unsigned tid = *active_threads++; diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh index 1813e8656..bf04b9f69 100755 --- a/src/cpu/o3/mips/cpu.hh +++ b/src/cpu/o3/mips/cpu.hh @@ -32,10 +32,12 @@ #ifndef __CPU_O3_MIPS_CPU_HH__ #define __CPU_O3_MIPS_CPU_HH__ -#include "arch/isa_traits.hh" +#include "arch/mips/regfile.hh" +#include "arch/mips/syscallreturn.hh" #include "cpu/thread_context.hh" #include "cpu/o3/cpu.hh" #include "sim/byteswap.hh" +#include "sim/faults.hh" class EndQuiesceEvent; namespace Kernel { @@ -55,14 +57,6 @@ class TranslatingPort; template <class Impl> class MipsO3CPU : public FullO3CPU<Impl> { - protected: - typedef TheISA::IntReg IntReg; - typedef TheISA::FloatReg FloatReg; - typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::MiscReg MiscReg; - typedef TheISA::RegFile RegFile; - typedef TheISA::MiscRegFile MiscRegFile; - public: typedef O3ThreadState<Impl> ImplState; typedef O3ThreadState<Impl> Thread; @@ -93,20 +87,22 @@ class MipsO3CPU : public FullO3CPU<Impl> } /** Reads a miscellaneous register. */ - MiscReg readMiscReg(int misc_reg, unsigned tid); + TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid); + TheISA::MiscReg readMiscRegWithEffect(int misc_reg, + Fault &fault, unsigned tid); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); + Fault setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); + Fault setMiscRegWithEffect(int misc_reg, + const TheISA::MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given * thread. The source of the squash is an external update of @@ -122,10 +118,10 @@ class MipsO3CPU : public FullO3CPU<Impl> */ void syscall(int64_t callnum, int tid); /** Gets a syscall argument. */ - IntReg getSyscallArg(int i, int tid); + TheISA::IntReg getSyscallArg(int i, int tid); /** Used to shift args for indirect syscall. */ - void setSyscallArg(int i, IntReg val, int tid); + void setSyscallArg(int i, TheISA::IntReg val, int tid); /** Sets the return value of a syscall. */ void setSyscallReturn(SyscallReturn return_value, int tid); diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index 72b64943b..e08741626 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -45,8 +45,6 @@ #include "cpu/o3/comm.hh" #include "cpu/o3/thread_state.hh" -using namespace TheISA; - template <class Impl> MipsO3CPU<Impl>::MipsO3CPU(Params *params) : FullO3CPU<Impl>(params) @@ -240,12 +238,13 @@ MipsO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) // check for error condition. if (return_value.successful()) { // no error - this->setArchIntReg(SyscallSuccessReg, 0, tid); - this->setArchIntReg(ReturnValueReg, return_value.value(), tid); + this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid); + this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid); } else { // got an error, return details - this->setArchIntReg(SyscallSuccessReg, (IntReg) -1, tid); - this->setArchIntReg(ReturnValueReg, -return_value.value(), tid); + this->setArchIntReg(TheISA::SyscallSuccessReg, + (TheISA::IntReg) -1, tid); + this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid); } } #endif diff --git a/src/cpu/o3/ras.hh b/src/cpu/o3/ras.hh index 5c8a93285..97846ed16 100644 --- a/src/cpu/o3/ras.hh +++ b/src/cpu/o3/ras.hh @@ -31,8 +31,7 @@ #ifndef __CPU_O3_RAS_HH__ #define __CPU_O3_RAS_HH__ -// For Addr type. -#include "arch/isa_traits.hh" +#include "sim/host.hh" #include <vector> /** Return address stack class, implements a simple RAS. */ diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index b6677b4b1..512cf0721 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -33,11 +33,11 @@ #define __CPU_O3_REGFILE_HH__ #include "arch/isa_traits.hh" -#include "arch/faults.hh" #include "arch/types.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" +#include "sim/faults.hh" #if FULL_SYSTEM #include "kern/kernel_stats.hh" diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index ee251de00..892eb12cf 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -34,8 +34,6 @@ #include "config/full_system.hh" #include "cpu/o3/rename.hh" -using namespace std; - template <class Impl> DefaultRename<Impl>::DefaultRename(Params *params) : iewToRenameDelay(params->iewToRenameDelay), @@ -223,7 +221,7 @@ DefaultRename<Impl>::initStage() template<class Impl> void -DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) +DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) { DPRINTF(Rename, "Setting active threads list pointer.\n"); activeThreads = at_ptr; @@ -272,7 +270,8 @@ DefaultRename<Impl>::switchOut() { // Clear any state, fix up the rename map. for (int i = 0; i < numThreads; i++) { - typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin(); + typename std::list<RenameHistory>::iterator hb_it = + historyBuffer[i].begin(); while (!historyBuffer[i].empty()) { assert(hb_it != historyBuffer[i].end()); @@ -407,7 +406,7 @@ DefaultRename<Impl>::tick() sortInsts(); - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); // Check stall and squash signals. while (threads != (*activeThreads).end()) { @@ -759,7 +758,7 @@ template<class Impl> bool DefaultRename<Impl>::skidsEmpty() { - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { if (!skidBuffer[*threads++].empty()) @@ -775,7 +774,7 @@ DefaultRename<Impl>::updateStatus() { bool any_unblocking = false; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); threads = (*activeThreads).begin(); @@ -865,7 +864,8 @@ template <class Impl> void DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) { - typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); + typename std::list<RenameHistory>::iterator hb_it = + historyBuffer[tid].begin(); // After a syscall squashes everything, the history buffer may be empty // but the ROB may still be squashing instructions. @@ -903,7 +903,8 @@ DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) "history buffer %u (size=%i), until [sn:%lli].\n", tid, tid, historyBuffer[tid].size(), inst_seq_num); - typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); + typename std::list<RenameHistory>::iterator hb_it = + historyBuffer[tid].end(); --hb_it; @@ -1302,7 +1303,7 @@ template <class Impl> void DefaultRename<Impl>::dumpHistory() { - typename list<RenameHistory>::iterator buf_it; + typename std::list<RenameHistory>::iterator buf_it; for (int i = 0; i < numThreads; i++) { diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh index c4c90c99a..896c66f3e 100644 --- a/src/cpu/o3/rename_map.hh +++ b/src/cpu/o3/rename_map.hh @@ -40,8 +40,7 @@ #include <vector> #include "cpu/o3/free_list.hh" -//For RegIndex -#include "arch/isa_traits.hh" +#include "arch/types.hh" class SimpleRenameMap { diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh index 1b9f666b8..fab114a74 100644 --- a/src/cpu/o3/rob_impl.hh +++ b/src/cpu/o3/rob_impl.hh @@ -32,11 +32,11 @@ #include "config/full_system.hh" #include "cpu/o3/rob.hh" -using namespace std; +#include <list> template <class Impl> ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth, - string _smtROBPolicy, unsigned _smtROBThreshold, + std::string _smtROBPolicy, unsigned _smtROBThreshold, unsigned _numThreads) : numEntries(_numEntries), squashWidth(_squashWidth), @@ -49,7 +49,7 @@ ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth, threadEntries[tid] = 0; } - string policy = _smtROBPolicy; + std::string policy = _smtROBPolicy; //Convert string to lowercase std::transform(policy.begin(), policy.end(), policy.begin(), @@ -118,7 +118,7 @@ ROB<Impl>::setCPU(O3CPU *cpu_ptr) template <class Impl> void -ROB<Impl>::setActiveThreads(list<unsigned> *at_ptr) +ROB<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) { DPRINTF(ROB, "Setting active threads list pointer.\n"); activeThreads = at_ptr; @@ -157,8 +157,8 @@ ROB<Impl>::resetEntries() if (robPolicy != Dynamic || numThreads > 1) { int active_threads = (*activeThreads).size(); - list<unsigned>::iterator threads = (*activeThreads).begin(); - list<unsigned>::iterator list_end = (*activeThreads).end(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator list_end = (*activeThreads).end(); while (threads != list_end) { if (robPolicy == Partitioned) { @@ -318,7 +318,7 @@ bool ROB<Impl>::canCommit() { //@todo: set ActiveThreads through ROB or CPU - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; @@ -432,7 +432,7 @@ ROB<Impl>::updateHead() bool first_valid = true; // @todo: set ActiveThreads through ROB or CPU - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned thread_num = *threads++; @@ -472,7 +472,7 @@ ROB<Impl>::updateTail() tail = instList[0].end(); bool first_valid = true; - list<unsigned>::iterator threads = (*activeThreads).begin(); + std::list<unsigned>::iterator threads = (*activeThreads).begin(); while (threads != (*activeThreads).end()) { unsigned tid = *threads++; diff --git a/src/cpu/o3/scoreboard.hh b/src/cpu/o3/scoreboard.hh index 544084c40..eefff1d8b 100644 --- a/src/cpu/o3/scoreboard.hh +++ b/src/cpu/o3/scoreboard.hh @@ -35,7 +35,6 @@ #include <iostream> #include <utility> #include <vector> -#include "arch/isa_traits.hh" #include "base/trace.hh" #include "base/traceflags.hh" #include "cpu/o3/comm.hh" diff --git a/src/cpu/o3/store_set.hh b/src/cpu/o3/store_set.hh index f5a44a1ac..f9f7637d0 100644 --- a/src/cpu/o3/store_set.hh +++ b/src/cpu/o3/store_set.hh @@ -36,8 +36,8 @@ #include <utility> #include <vector> -#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" +#include "sim/host.hh" struct ltseqnum { bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index bf8cbf850..ae085d200 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -32,8 +32,6 @@ #include "cpu/o3/thread_context.hh" #include "cpu/quiesce_event.hh" -using namespace TheISA; - #if FULL_SYSTEM template <class Impl> VirtualPort * diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 1c8105204..b6f2e14c0 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -31,8 +31,6 @@ #ifndef __CPU_O3_THREAD_STATE_HH__ #define __CPU_O3_THREAD_STATE_HH__ -#include "arch/faults.hh" -#include "arch/isa_traits.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" diff --git a/src/cpu/o3/tournament_pred.hh b/src/cpu/o3/tournament_pred.hh index 92402adc6..66b4aaae2 100644 --- a/src/cpu/o3/tournament_pred.hh +++ b/src/cpu/o3/tournament_pred.hh @@ -31,9 +31,8 @@ #ifndef __CPU_O3_TOURNAMENT_PRED_HH__ #define __CPU_O3_TOURNAMENT_PRED_HH__ -// For Addr type. -#include "arch/isa_traits.hh" #include "cpu/o3/sat_counter.hh" +#include "sim/host.hh" #include <vector> /** diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index f58b81990..80f18434c 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -47,6 +47,7 @@ #include "arch/faults.hh" #include "arch/alpha/osfpal.hh" #include "arch/alpha/tlb.hh" +#include "arch/alpha/types.hh" #include "arch/vtophys.hh" #include "base/callback.hh" //#include "base/remote_gdb.hh" diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index 67691d416..75ac464ec 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -32,6 +32,7 @@ #define __CPU_OZONE_DYN_INST_HH__ #include "arch/isa_traits.hh" +#include "arch/types.hh" #include "config/full_system.hh" #include "cpu/base_dyn_inst.hh" #include "cpu/inst_seq.hh" diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index bad902c2a..ba0d70417 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -29,13 +29,10 @@ */ #include "arch/faults.hh" -#include "arch/isa_traits.hh" #include "config/full_system.hh" #include "cpu/ozone/dyn_inst.hh" #include "kern/kernel_stats.hh" -using namespace TheISA; - template <class Impl> OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu) : BaseDynInst<Impl>(0, 0, 0, 0, cpu) diff --git a/src/cpu/ozone/ea_list.hh b/src/cpu/ozone/ea_list.hh index 64882632c..d9e9d701f 100644 --- a/src/cpu/ozone/ea_list.hh +++ b/src/cpu/ozone/ea_list.hh @@ -35,8 +35,8 @@ #include <list> #include <utility> -#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" +#include "sim/host.hh" /** * Simple class to hold onto a list of pairs, each pair having a memory diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 9da937320..c9c5a869b 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -32,6 +32,7 @@ #include "arch/faults.hh" #include "arch/isa_traits.hh" +#include "arch/utility.hh" #include "base/statistics.hh" #include "cpu/thread_context.hh" #include "cpu/exetrace.hh" diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh index cbb73364e..701fc0ee9 100644 --- a/src/cpu/ozone/inorder_back_end_impl.hh +++ b/src/cpu/ozone/inorder_back_end_impl.hh @@ -29,12 +29,10 @@ */ #include "arch/faults.hh" -#include "arch/isa_traits.hh" +#include "arch/types.hh" #include "cpu/ozone/inorder_back_end.hh" #include "cpu/ozone/thread_state.hh" -using namespace TheISA; - template <class Impl> InorderBackEnd<Impl>::InorderBackEnd(Params *params) : squashPending(false), diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh index 1b5340e55..38c1c09a2 100644 --- a/src/cpu/ozone/lsq_unit.hh +++ b/src/cpu/ozone/lsq_unit.hh @@ -36,7 +36,7 @@ #include <algorithm> #include "arch/faults.hh" -#include "arch/isa_traits.hh" +#include "arch/types.hh" #include "config/full_system.hh" #include "base/hashmap.hh" #include "cpu/inst_seq.hh" diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh index f8cb18634..ee0804036 100644 --- a/src/cpu/ozone/lsq_unit_impl.hh +++ b/src/cpu/ozone/lsq_unit_impl.hh @@ -28,7 +28,7 @@ * Authors: Kevin Lim */ -#include "arch/isa_traits.hh" +#include "arch/faults.hh" #include "base/str.hh" #include "cpu/ozone/lsq_unit.hh" diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index 2eb09d01a..9a21a9d01 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -37,7 +37,7 @@ #include <algorithm> #include "arch/faults.hh" -#include "arch/isa_traits.hh" +#include "arch/types.hh" #include "config/full_system.hh" #include "base/hashmap.hh" #include "cpu/inst_seq.hh" diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index 88e9c218f..7eef4b11f 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -30,7 +30,7 @@ #include "config/use_checker.hh" -#include "arch/isa_traits.hh" +#include "arch/faults.hh" #include "base/str.hh" #include "cpu/ozone/lw_lsq.hh" #include "cpu/checker/cpu.hh" diff --git a/src/cpu/ozone/null_predictor.hh b/src/cpu/ozone/null_predictor.hh index a98c89d69..0751338b7 100644 --- a/src/cpu/ozone/null_predictor.hh +++ b/src/cpu/ozone/null_predictor.hh @@ -31,8 +31,8 @@ #ifndef __CPU_OZONE_NULL_PREDICTOR_HH__ #define __CPU_OZONE_NULL_PREDICTOR_HH__ -#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" +#include "sim/host.hh" template <class Impl> class NullPredictor diff --git a/src/cpu/ozone/ozone_impl.hh b/src/cpu/ozone/ozone_impl.hh index 503675738..2271cd68a 100644 --- a/src/cpu/ozone/ozone_impl.hh +++ b/src/cpu/ozone/ozone_impl.hh @@ -31,7 +31,6 @@ #ifndef __CPU_OZONE_OZONE_IMPL_HH__ #define __CPU_OZONE_OZONE_IMPL_HH__ -#include "arch/alpha/isa_traits.hh" #include "cpu/o3/bpred_unit.hh" #include "cpu/ozone/front_end.hh" #include "cpu/ozone/inst_queue.hh" diff --git a/src/cpu/ozone/simple_impl.hh b/src/cpu/ozone/simple_impl.hh index 3199d8d8a..42002180b 100644 --- a/src/cpu/ozone/simple_impl.hh +++ b/src/cpu/ozone/simple_impl.hh @@ -31,7 +31,6 @@ #ifndef __CPU_OZONE_SIMPLE_IMPL_HH__ #define __CPU_OZONE_SIMPLE_IMPL_HH__ -#include "arch/isa_traits.hh" #include "cpu/o3/bpred_unit.hh" #include "cpu/ozone/cpu.hh" #include "cpu/ozone/front_end.hh" diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index ef4b1429d..8234cf938 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -32,7 +32,8 @@ #define __CPU_OZONE_THREAD_STATE_HH__ #include "arch/faults.hh" -#include "arch/isa_traits.hh" +#include "arch/types.hh" +#include "arch/regfile.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" #include "sim/process.hh" diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 4322e8092..9d76c1225 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -35,13 +35,13 @@ #include <string> #include "arch/isa_traits.hh" -#include "arch/faults.hh" #include "base/bitfield.hh" #include "base/hashmap.hh" #include "base/misc.hh" #include "base/refcnt.hh" #include "cpu/op_class.hh" #include "cpu/o3/dyn_inst.hh" +#include "sim/faults.hh" #include "sim/host.hh" // forward declarations diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index b03a2e2bb..6e985054f 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -31,7 +31,7 @@ #ifndef __CPU_THREAD_STATE_HH__ #define __CPU_THREAD_STATE_HH__ -#include "arch/isa_traits.hh" +#include "arch/types.hh" #include "cpu/thread_context.hh" #if !FULL_SYSTEM diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index a447ae3d5..56e7a4d58 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -53,8 +53,6 @@ #include "sim/sim_events.hh" // for SimExitEvent -using namespace std; - template<class TagStore, class Buffering, class Coherence> bool Cache<TagStore,Buffering,Coherence>:: @@ -501,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update) MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid()); // There can be many matching outstanding writes. - vector<MSHR*> writes; + std::vector<MSHR*> writes; missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes); if (!update) { diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc index 10d53b109..2f61e8a54 100644 --- a/src/mem/cache/miss/blocking_buffer.cc +++ b/src/mem/cache/miss/blocking_buffer.cc @@ -40,8 +40,6 @@ #include "sim/eventq.hh" // for Event declaration. #include "mem/request.hh" -using namespace TheISA; - /** * @todo Move writebacks into shared BaseBuffer class. */ diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh index db5c94820..e554b3cec 100644 --- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh +++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh @@ -33,6 +33,7 @@ * Describes a tagged prefetcher based on template policies. */ +#include "arch/isa_traits.hh" #include "mem/cache/prefetch/tagged_prefetcher.hh" template <class TagStore, class Buffering> diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 534db0077..83b4006e2 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -39,7 +39,7 @@ #define __MEM_PACKET_HH__ #include "mem/request.hh" -#include "arch/isa_traits.hh" +#include "sim/host.hh" #include "sim/root.hh" #include <list> diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index 86247f276..52c81671b 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -38,7 +38,7 @@ #include <string> -#include "arch/faults.hh" +#include "sim/faults.hh" #include "arch/isa_traits.hh" #include "base/hashmap.hh" #include "base/trace.hh" diff --git a/src/mem/port_impl.hh b/src/mem/port_impl.hh index e9a159293..b7980bdd2 100644 --- a/src/mem/port_impl.hh +++ b/src/mem/port_impl.hh @@ -28,8 +28,6 @@ * Authors: Ali Saidi */ -#include "arch/isa_specific.hh" -#include "arch/isa_traits.hh" #include "mem/port.hh" #include "sim/byteswap.hh" @@ -37,7 +35,7 @@ template <typename T> void FunctionalPort::writeHtoG(Addr addr, T d) { - d = TheISA::htog(d); + d = htog(d); writeBlob(addr, (uint8_t*)&d, sizeof(T)); } @@ -48,6 +46,6 @@ FunctionalPort::readGtoH(Addr addr) { T d; readBlob(addr, (uint8_t*)&d, sizeof(T)); - return TheISA::gtoh(d); + return gtoh(d); } diff --git a/src/mem/request.hh b/src/mem/request.hh index a62fe2a20..f3647e55f 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -38,7 +38,7 @@ #ifndef __MEM_REQUEST_HH__ #define __MEM_REQUEST_HH__ -#include "arch/isa_traits.hh" +#include "sim/host.hh" #include "sim/root.hh" class Request; diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index 5e5b7d95f..4a83b93e0 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -30,10 +30,8 @@ class ThreadContext; -//We need the "Tick" data type from here +//We need the "Tick" and "Addr" data types from here #include "sim/host.hh" -//We need the "Addr" data type from here -#include "arch/isa_traits.hh" namespace AlphaPseudo { |