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-rw-r--r--src/arch/alpha/isa/decoder.isa36
-rw-r--r--src/arch/sparc/isa/bitfields.isa1
-rw-r--r--src/arch/sparc/isa/decoder.isa14
-rw-r--r--src/arch/sparc/isa/includes.isa4
-rw-r--r--src/arch/sparc/isa/operands.isa6
-rw-r--r--src/arch/sparc/tlb.cc47
-rw-r--r--src/sim/pseudo_inst.cc2
-rw-r--r--src/sim/pseudo_inst.hh2
8 files changed, 74 insertions, 38 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 1da6a60f1..49c25c3c2 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -790,19 +790,19 @@ decode OPCODE default Unknown::unknown() {
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
0x00: arm({{
- AlphaPseudo::arm(xc->tcBase());
+ PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
- AlphaPseudo::quiesce(xc->tcBase());
+ PseudoInst::quiesce(xc->tcBase());
}}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
- AlphaPseudo::quiesceNs(xc->tcBase(), R16);
+ PseudoInst::quiesceNs(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce);
0x03: quiesceCycles({{
- AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
+ PseudoInst::quiesceCycles(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
0x04: quiesceTime({{
- R0 = AlphaPseudo::quiesceTime(xc->tcBase());
+ R0 = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
0x10: ivlb({{
warn_once("Obsolete M5 instruction ivlb encountered.\n");
@@ -811,47 +811,47 @@ decode OPCODE default Unknown::unknown() {
warn_once("Obsolete M5 instruction ivlb encountered.\n");
}});
0x20: m5exit_old({{
- AlphaPseudo::m5exit_old(xc->tcBase());
+ PseudoInst::m5exit_old(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
- AlphaPseudo::m5exit(xc->tcBase(), R16);
+ PseudoInst::m5exit(xc->tcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
0x31: loadsymbol({{
- AlphaPseudo::loadsymbol(xc->tcBase());
+ PseudoInst::loadsymbol(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
0x40: resetstats({{
- AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
+ PseudoInst::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
- AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
+ PseudoInst::dumpstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
- AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
+ PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
- AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
+ PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
- R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
+ R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
- AlphaPseudo::debugbreak(xc->tcBase());
+ PseudoInst::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
- AlphaPseudo::switchcpu(xc->tcBase());
+ PseudoInst::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
- AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
+ PseudoInst::addsymbol(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, IsNonSpeculative);
0x55: m5anBegin({{
- AlphaPseudo::anBegin(xc->tcBase(), R16);
+ PseudoInst::anBegin(xc->tcBase(), R16);
}}, IsNonSpeculative);
0x56: m5anWait({{
- AlphaPseudo::anWait(xc->tcBase(), R16, R17);
+ PseudoInst::anWait(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
}
}
diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa
index e75680d2b..afa8f88a2 100644
--- a/src/arch/sparc/isa/bitfields.isa
+++ b/src/arch/sparc/isa/bitfields.isa
@@ -54,6 +54,7 @@ def bitfield FCN <29:25>;
def bitfield I <13>;
def bitfield IMM_ASI <12:5>;
def bitfield IMM22 <21:0>;
+def bitfield M5FUNC <15:7>;
def bitfield MMASK <3:0>;
def bitfield OP <31:30>;
def bitfield OP2 <24:22>;
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 0be7defba..e2d1707dd 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1009,7 +1009,16 @@ decode OP default Unknown::unknown()
0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
0x81: FailUnimpl::siam();
}
- 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
+ // M5 special opcodes use the reserved IMPDEP2A opcode space
+ 0x37: decode M5FUNC {
+ // we have 7 bits of space here to play with...
+ 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
+ }}, No_OpClass, IsNonSpeculative);
+ 0x54: m5panic({{
+ panic("M5 panic instruction called at pc=%#x.", xc->readPC());
+ }}, No_OpClass, IsNonSpeculative);
+
+ }
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;
if(target & 0x3)
@@ -1077,7 +1086,8 @@ decode OP default Unknown::unknown()
}
}}, IsSerializeAfter, IsNonSpeculative);
}
- 0x3B: Nop::flush({{/*Instruction memory flush*/}});
+ 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
+ MemWriteOp);
0x3C: save({{
if(Cansave == 0)
{
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index b46ef011e..05e9e8731 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -70,6 +70,10 @@ output exec {{
#include <ieeefp.h>
#endif
+#if FULL_SYSTEM
+#include "sim/pseudo_inst.hh"
+#endif
+
#include <limits>
#include <cmath>
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index f624c3e2b..82e9407de 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -100,6 +100,12 @@ def operands {{
'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
'R16': ('IntReg', 'udw', '16', None, 9),
+ 'O0': ('IntReg', 'udw', '24', 'IsInteger', 10),
+ 'O1': ('IntReg', 'udw', '25', 'IsInteger', 11),
+ 'O2': ('IntReg', 'udw', '26', 'IsInteger', 12),
+ 'O3': ('IntReg', 'udw', '27', 'IsInteger', 13),
+ 'O4': ('IntReg', 'udw', '28', 'IsInteger', 14),
+ 'O5': ('IntReg', 'udw', '29', 'IsInteger', 15),
# Control registers
# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 82b1ed175..3ed2a9cc6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -596,21 +596,36 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
// Be fast if we can!
if (cacheValid && cacheState == tlbdata) {
- if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
- cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
- (!write || cacheEntry[0]->pte.writable())) {
- req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
- vaddr & cacheEntry[0]->pte.size()-1 );
- return NoFault;
- }
- if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
- cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
- (!write || cacheEntry[1]->pte.writable())) {
- req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
- vaddr & cacheEntry[1]->pte.size()-1 );
- return NoFault;
- }
- }
+
+
+
+ if (cacheEntry[0]) {
+ TlbEntry *ce = cacheEntry[0];
+ Addr ce_va = ce->range.va;
+ if (cacheAsi[0] == asi &&
+ ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+ (!write || ce->pte.writable())) {
+ req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+ if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+ req->setFlags(req->getFlags() | UNCACHEABLE);
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+ return NoFault;
+ } // if matched
+ } // if cache entry valid
+ if (cacheEntry[1]) {
+ TlbEntry *ce = cacheEntry[1];
+ Addr ce_va = ce->range.va;
+ if (cacheAsi[1] == asi &&
+ ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+ (!write || ce->pte.writable())) {
+ req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+ if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+ req->setFlags(req->getFlags() | UNCACHEABLE);
+ DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+ return NoFault;
+ } // if matched
+ } // if cache entry valid
+ }
bool red = bits(tlbdata,1,1);
bool priv = bits(tlbdata,2,2);
@@ -756,7 +771,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
}
- if (e->pte.sideffect())
+ if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
req->setFlags(req->getFlags() | UNCACHEABLE);
// cache translation date for next translation
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 66ebc10e1..56a779674 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -55,7 +55,7 @@ using namespace std;
using namespace Stats;
using namespace TheISA;
-namespace AlphaPseudo
+namespace PseudoInst
{
void
arm(ThreadContext *tc)
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index bc71a7e64..93021abad 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -33,7 +33,7 @@ class ThreadContext;
//We need the "Tick" and "Addr" data types from here
#include "sim/host.hh"
-namespace AlphaPseudo
+namespace PseudoInst
{
/**
* @todo these externs are only here for a hack in fullCPU::takeOver...
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 09:35:19 +0000