diff options
Diffstat (limited to 'src')
33 files changed, 448 insertions, 245 deletions
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index a0a6112de..c2ef97bfa 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -60,6 +60,7 @@ full_system_sources = Split(''' stacktrace.cc system.cc tlb.cc + ua2005.cc vtophys.cc ''') diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index a355816ac..781958c77 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -377,7 +377,9 @@ decode OP default Unknown::unknown() //1 should cause an illegal instruction exception 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 0x03: NoPriv::rdasi({{Rd = Asi;}}); - 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); + 0x04: PrivCheck::rdtick( + {{ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);}}, + {{Tick<63:>}}); 0x05: NoPriv::rdpc({{ if(Pstate<3:>) Rd = (xc->readPC())<31:0>; @@ -403,9 +405,15 @@ decode OP default Unknown::unknown() }}); //0x14-0x15 should cause an illegal instruction exception 0x16: Priv::rdsoftint({{Rd = Softint;}}); - 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); - 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); - 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); + 0x17: Priv::rdtick_cmpr({{ + Rd = xc->readMiscRegWithEffect(MISCREG_TICK_CMPR); + }}); + 0x18: PrivCheck::rdstick({{ + Rd = xc->readMiscRegWithEffect(MISCREG_STICK); + }}, {{Stick<63:>}}); + 0x19: Priv::rdstick_cmpr({{ + Rd = xc->readMiscRegWithEffect(MISCREG_STICK_CMPR); + }}); 0x1A: Priv::rdstrand_sts_reg({{ if(Pstate<2:> && !Hpstate<2:>) Rd = StrandStsReg<0:>; @@ -429,7 +437,9 @@ decode OP default Unknown::unknown() 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 0x06: HPriv::rdhprhver({{Rd = Hver;}}); //0x07-0x1E should cause an illegal instruction exception - 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); + 0x1F: HPriv::rdhprhstick_cmpr({{ + Rd = xc->readMiscRegWithEffect(MISCREG_HSTICK_CMPR); + }}); } 0x2A: decode RS1 { 0x00: Priv::rdprtpc({{ @@ -452,7 +462,9 @@ decode OP default Unknown::unknown() return new IllegalInstruction; Rd = Tt; }}); - 0x04: Priv::rdprtick({{Rd = Tick;}}); + 0x04: Priv::rdprtick({{ + Rd = xc->readMiscRegWithEffect(MISCREG_TICK); + }}); 0x05: Priv::rdprtba({{Rd = Tba;}}); 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 0x07: Priv::rdprtl({{Rd = Tl;}}); @@ -542,13 +554,17 @@ decode OP default Unknown::unknown() 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); - 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); + 0x17: Priv::wrtick_cmpr({{ + xc->setMiscRegWithEffect(MISCREG_TICK_CMPR, Rs1 ^ Rs2_or_imm13); + }}); 0x18: NoPriv::wrstick({{ if(!Hpstate<2:>) return new IllegalInstruction; - Stick = Rs1 ^ Rs2_or_imm13; + xc->setMiscRegWithEffect(MISCREG_STICK, Rs1 ^ Rs2_or_imm13); + }}); + 0x19: Priv::wrstick_cmpr({{ + xc->setMiscRegWithEffect(MISCREG_STICK_CMPR, Rs1 ^ Rs2_or_imm13); }}); - 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 0x1A: Priv::wrstrand_sts_reg({{ if(Pstate<2:> && !Hpstate<2:>) StrandStsReg = StrandStsReg<63:1> | @@ -605,7 +621,9 @@ decode OP default Unknown::unknown() else Tt = Rs1 ^ Rs2_or_imm13; }}); - 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); + 0x04: HPriv::wrprtick({{ + xc->setMiscRegWithEffect(MISCREG_TICK, Rs1 ^ Rs2_or_imm13); + }}); 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 0x07: Priv::wrprtl({{ @@ -642,7 +660,9 @@ decode OP default Unknown::unknown() //0x04 should cause an illegal instruction exception 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); //0x06-0x01D should cause an illegal instruction exception - 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); + 0x1F: HPriv::wrhprhstick_cmpr({{ + xc->setMiscRegWithEffect(MISCREG_HSTICK_CMPR, Rs1 ^ Rs2_or_imm13); + }}); } 0x34: decode OPF{ format BasicOperate{ diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index d2164155f..046d811e0 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -72,7 +72,7 @@ void MiscRegFile::clear() y = 0; ccr = 0; asi = 0; - tick = 0; + tick = ULL(1) << 63; fprs = 0; gsr = 0; softint = 0; @@ -282,10 +282,19 @@ MiscReg MiscRegFile::readReg(int miscReg) MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) { switch (miscReg) { + // tick and stick are aliased to each other in niagra + case MISCREG_STICK: case MISCREG_TICK: case MISCREG_PRIVTICK: - return tc->getCpuPtr()->curCycle() - (tick & mask(63)) | - (tick & ~(mask(63))) << 63; + // I'm not sure why legion ignores the lowest two bits, but we'll go + // with it + // change from curCycle() to instCount() until we're done with legion + DPRINTFN("Instruction Count when STICK read: %#X\n", + tc->getCpuPtr()->instCount()); + uint64_t t1 = mbits(tc->getCpuPtr()->instCount() - (tick & + mask(63)),62,2); + uint64_t t2 = mbits(tick,63,63) ; + return t1 | t2; case MISCREG_FPRS: panic("FPU not implemented\n"); case MISCREG_PCR: @@ -296,13 +305,13 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) panic("Floating Point not implemented\n"); //We'll include this only in FS so we don't need the SparcSystem type around //in SE. -#if FULL_SYSTEM +/*#if FULL_SYSTEM case MISCREG_STICK: SparcSystem *sys; sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); -#endif +#endif*/ case MISCREG_HVER: return NWindows | MaxTL << 8 | MaxGL << 16; } @@ -518,8 +527,10 @@ void MiscRegFile::setRegWithEffect(int miscReg, SparcSystem *sys; #endif switch (miscReg) { + case MISCREG_STICK: case MISCREG_TICK: - tick = tc->getCpuPtr()->curCycle() - val & ~Bit64; + // change from curCycle() to instCount() until we're done with legion + tick = tc->getCpuPtr()->instCount() - val & ~Bit64; tick |= val & Bit64; break; case MISCREG_FPRS: @@ -575,12 +586,14 @@ void MiscRegFile::setRegWithEffect(int miscReg, //We'll include this only in FS so we don't need the SparcSystem type around //in SE. #if FULL_SYSTEM - case MISCREG_STICK: + // @todo figure out how we're actualy going to do this. In niagra the + // registers are aliased to the same thing (see tick above) + /*case MISCREG_STICK: sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; stick |= val & Bit64; - break; + break;*/ case MISCREG_STICK_CMPR: if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index e7779d333..916c23028 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -213,6 +213,10 @@ namespace SparcISA // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu #if FULL_SYSTEM + void setFSRegWithEffect(int miscReg, const MiscReg &val, + ThreadContext *tc); + MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc); + /** Process a tick compare event and generate an interrupt on the cpu if * appropriate. */ void processTickCompare(ThreadContext *tc); diff --git a/src/arch/sparc/mmaped_ipr.hh b/src/arch/sparc/mmaped_ipr.hh index d87d127b0..b11c16754 100644 --- a/src/arch/sparc/mmaped_ipr.hh +++ b/src/arch/sparc/mmaped_ipr.hh @@ -37,6 +37,7 @@ * ISA-specific helper functions for memory mapped IPR accesses. */ +#include "config/full_system.hh" #include "cpu/thread_context.hh" #include "mem/packet.hh" #include "arch/sparc/tlb.hh" @@ -47,14 +48,22 @@ namespace SparcISA inline Tick handleIprRead(ThreadContext *xc, Packet *pkt) { +#if FULL_SYSTEM return xc->getDTBPtr()->doMmuRegRead(xc, pkt); +#else + panic("Shouldn't have a memory mapped register in SE\n"); +#endif } inline Tick handleIprWrite(ThreadContext *xc, Packet *pkt) { +#if FULL_SYSTEM return xc->getDTBPtr()->doMmuRegWrite(xc, pkt); +#else + panic("Shouldn't have a memory mapped register in SE\n"); +#endif } diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index 72c87f0ad..da83d86fc 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -155,6 +155,11 @@ SparcSystem::SparcSystem(Params *p) if (!hypervisor->loadLocalSymbols(debugSymbolTable)) panic("could not load hypervisor symbols\n"); + // Strip off the rom address so when the hypervisor is copied into memory we + // have symbols still + if (!hypervisor->loadLocalSymbols(debugSymbolTable, 0xFFFFFF)) + panic("could not load hypervisor symbols\n"); + if (!nvram->loadGlobalSymbols(debugSymbolTable)) panic("could not load reset symbols\n"); diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 5fde4d36d..51f867612 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -29,10 +29,11 @@ */ #include "arch/sparc/asi.hh" -#include "arch/sparc/tlb.hh" -#include "sim/builder.hh" #include "arch/sparc/miscregfile.hh" +#include "arch/sparc/tlb.hh" +#include "base/trace.hh" #include "cpu/thread_context.hh" +#include "sim/builder.hh" /* @todo remove some of the magic constants. -- ali * */ @@ -72,6 +73,10 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real, MapIter i; TlbEntry *new_entry; + + DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x, pid=%d cid=%d r=%d\n", + va, partition_id, context_id, (int)real); + int x = -1; for (x = 0; x < size; x++) { if (!tlb[x].valid || !tlb[x].used) { @@ -104,6 +109,7 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real, i->second->used = false; usedEntries--; } + DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n"); lookupTable.erase(i); } @@ -127,6 +133,8 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id) TlbRange tr; TlbEntry *t; + DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", + va, partition_id, context_id, real); // Assemble full address structure tr.va = va; tr.size = va + MachineBytes; @@ -137,8 +145,10 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id) // Try to find the entry i = lookupTable.find(tr); if (i == lookupTable.end()) { + DPRINTF(TLB, "TLB: No valid entry found\n"); return NULL; } + DPRINTF(TLB, "TLB: Valid entry found\n"); // Mark the entries used bit and clear other used bits in needed t = i->second; @@ -279,6 +289,8 @@ void ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, bool se, FaultTypes ft, int asi) { + DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", + (int)write, ct, ft, asi); TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); } @@ -286,6 +298,8 @@ void DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, bool se, FaultTypes ft, int asi) { + DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", + a, (int)write, ct, ft, asi); TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); } @@ -308,6 +322,9 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) bool real = false; TlbEntry *e; + DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", + vaddr, req->getSize()); + assert(req->getAsi() == ASI_IMPLICIT); if (tl > 0) { @@ -385,14 +402,17 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) bool implicit = false; bool real = false; Addr vaddr = req->getVaddr(); + Addr size = req->getSize(); ContextType ct; int context; ASI asi; TlbEntry *e; - asi = (ASI)req->getAsi(); + DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", + vaddr, size, asi); + if (asi == ASI_IMPLICIT) implicit = true; @@ -432,7 +452,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) } // If the asi is unaligned trap - if (AsiIsBlock(asi) && vaddr & 0x3f || vaddr & 0x7) { + if (vaddr & size-1) { writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); return new MemAddressNotAligned; } @@ -478,6 +498,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) if (e == NULL || !e->valid) { tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, vaddr & ~BytesInPageMask | context); + DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); if (real) return new DataRealTranslationMiss; else @@ -516,6 +537,7 @@ handleScratchRegAccess: return new DataAccessException; } handleMmuRegAccess: + DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); req->setMmapedIpr(true); req->setPaddr(req->getVaddr()); return NoFault; diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 6493ddfd5..32bc2a44b 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -28,27 +28,32 @@ * Authors: Ali Saidi */ -#include "arch/sparc/regfile.hh" +#include "arch/sparc/miscregfile.hh" +#include "base/bitfield.hh" +#include "base/trace.hh" +#include "cpu/base.hh" +#include "cpu/thread_context.hh" -Fault -SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, +using namespace SparcISA; + +void +MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, ThreadContext *tc) { int64_t time; - SparcSystem *sys; + int oldLevel, newLevel; switch (miscReg) { /* Full system only ASRs */ case MISCREG_SOFTINT: - if (isNonPriv()) - return new PrivilegedOpcode; // Check if we are going to interrupt because of something - int oldLevel = InterruptLevel(softint); - int newLevel = InterruptLevel(val); + oldLevel = InterruptLevel(softint); + newLevel = InterruptLevel(val); setReg(miscReg, val); if (newLevel > oldLevel) ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX //tc->getCpuPtr()->checkInterrupts = true; - return NoFault; + panic("SOFTINT not implemented\n"); + break; case MISCREG_SOFTINT_CLR: return setRegWithEffect(miscReg, ~val & softint, tc); @@ -56,152 +61,100 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, return setRegWithEffect(miscReg, val | softint, tc); case MISCREG_TICK_CMPR: - if (isNonPriv()) - return new PrivilegedOpcode; if (tickCompare == NULL) tickCompare = new TickCompareEvent(this, tc); setReg(miscReg, val); - if (tick_cmprFields.int_dis && tickCompare.scheduled()) - tickCompare.deschedule(); - time = tick_cmprFields.tick_cmpr - tickFields.counter; - if (!tick_cmprFields.int_dis && time > 0) - tickCompare.schedule(time * tc->getCpuPtr()->cycles(1)); - return NoFault; - - case MISCREG_STICK: - if (isNonPriv()) - return new PrivilegedOpcode; - if (isPriv()) - return new PrivilegedAction; - sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); - assert(sys != NULL); - sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; - stickFields.npt = val & Bit64 ? 1 : 0; - return NoFault; + if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) + tickCompare->deschedule(); + time = (tick_cmpr & mask(63)) - (tick & mask(63)); + if (!(tick_cmpr & ~mask(63)) && time > 0) + tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + break; case MISCREG_STICK_CMPR: - if (isNonPriv()) - return new PrivilegedOpcode; if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); - sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); - assert(sys != NULL); setReg(miscReg, val); - if (stick_cmprFields.int_dis && sTickCompare.scheduled()) - sTickCompare.deschedule(); - time = stick_cmprFields.tick_cmpr - sys->sysTick; - if (!stick_cmprFields.int_dis && time > 0) - sTickCompare.schedule(time * Clock::Int::ns); - return NoFault; - - /* Fullsystem only Priv registers. */ + if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) + sTickCompare->deschedule(); + time = (stick_cmpr & mask(63)) - (stick & mask(63)); + if (!(stick_cmpr & ~mask(63)) && time > 0) + sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + break; + case MISCREG_PIL: - if (FULL_SYSTEM) { - setReg(miscReg, val); - //tc->getCpuPtr()->checkInterrupts; - // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX - return NoFault; - } else - panic("PIL not implemented for syscall emulation\n"); - - /* Hyper privileged registers */ - case MISCREG_HPSTATE: - case MISCREG_HINTP: setReg(miscReg, val); - return NoFault; - case MISCREG_HTSTATE: - if (tl == 0) - return new IllegalInstruction; - setReg(miscReg, val); - return NoFault; + //tc->getCpuPtr()->checkInterrupts; + // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX + panic("PIL not implemented\n"); + break; + + case MISCREG_HVER: + panic("Shouldn't be writing HVER\n"); case MISCREG_HTBA: // clear lower 7 bits on writes. setReg(miscReg, val & ULL(~0x7FFF)); - return NoFault; + break; - case MISCREG_STRAND_STS_REG: - setReg(miscReg, strandStatusReg); - return NoFault; case MISCREG_HSTICK_CMPR: - if (isNonPriv()) - return new PrivilegedOpcode; if (hSTickCompare == NULL) hSTickCompare = new HSTickCompareEvent(this, tc); - sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); - assert(sys != NULL); setReg(miscReg, val); - if (hstick_cmprFields.int_dis && hSTickCompare.scheduled()) - hSTickCompare.deschedule(); - int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick; - if (!hstick_cmprFields.int_dis && time > 0) - hSTickCompare.schedule(time * Clock::Int::ns); - return NoFault; + if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) + hSTickCompare->deschedule(); + time = (hstick_cmpr & mask(63)) - (stick & mask(63)); + if (!(hstick_cmpr & ~mask(63)) && time > 0) + hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + break; + + case MISCREG_HPSTATE: + case MISCREG_HTSTATE: + case MISCREG_STRAND_STS_REG: + setReg(miscReg, val); + break; + default: - return new IllegalInstruction; + panic("Invalid write to FS misc register\n"); } } MiscReg -MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) +MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) { switch (miscReg) { /* Privileged registers. */ case MISCREG_SOFTINT: - if (isNonPriv()) { - fault = new PrivilegedOpcode; - return 0; - } - return readReg(miscReg); case MISCREG_TICK_CMPR: - if (isNonPriv()) { - fault = new PrivilegedOpcode; - return 0; - } - return readReg(miscReg); - case MISCREG_STICK: - SparcSystem *sys; - if (stickFields.npt && !isNonPriv()) { - fault = new PrivilegedAction; - return 0; - } - sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); - assert(sys != NULL); - return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; case MISCREG_STICK_CMPR: - if (isNonPriv()) { - fault = new PrivilegedOpcode; - return 0; - } - return readReg(miscReg); - - - /* Hyper privileged registers */ + case MISCREG_PIL: case MISCREG_HPSTATE: case MISCREG_HINTP: - return readReg(miscReg); case MISCREG_HTSTATE: - if (tl == 0) { - fault = new IllegalInstruction; - return 0; - } - return readReg(miscReg); + case MISCREG_STRAND_STS_REG: + case MISCREG_HSTICK_CMPR: + return readReg(miscReg) ; case MISCREG_HTBA: return readReg(miscReg) & ULL(~0x7FFF); case MISCREG_HVER: return NWindows | MaxTL << 8 | MaxGL << 16; - case MISCREG_STRAND_STS_REG: - return strandStatusReg; - case MISCREG_HSTICK_CMPR: - return hstick_cmpr; default: - fault = new IllegalInstruction; - return 0; + panic("Invalid read to FS misc register\n"); } } +/* + In Niagra STICK==TICK so this isn't needed + case MISCREG_STICK: + SparcSystem *sys; + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); + assert(sys != NULL); + return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); +*/ + + void MiscRegFile::processTickCompare(ThreadContext *tc) @@ -221,4 +174,3 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) panic("tick compare not implemented\n"); } -}; // namespace SparcISA diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh index 177279678..1fc0bad5d 100644 --- a/src/base/bitfield.hh +++ b/src/base/bitfield.hh @@ -58,6 +58,18 @@ bits(T val, int first, int last) } /** + * Mask off the given bits in place like bits() but without shifting. + * msb = 63, lsb = 0 + */ +template <class T> +inline +T +mbits(T val, int first, int last) +{ + return val & (mask(first+1) & ~mask(last)); +} + +/** * Sign-extend an N-bit value to 64 bits. */ template <int N> diff --git a/src/base/loader/aout_object.cc b/src/base/loader/aout_object.cc index 6691bd4ae..8fbad8030 100644 --- a/src/base/loader/aout_object.cc +++ b/src/base/loader/aout_object.cc @@ -82,14 +82,14 @@ AoutObject::AoutObject(const string &_filename, int _fd, bool -AoutObject::loadGlobalSymbols(SymbolTable *symtab) +AoutObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask) { // a.out symbols not supported yet return false; } bool -AoutObject::loadLocalSymbols(SymbolTable *symtab) +AoutObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask) { // a.out symbols not supported yet return false; diff --git a/src/base/loader/aout_object.hh b/src/base/loader/aout_object.hh index d180d69f3..7bac5be65 100644 --- a/src/base/loader/aout_object.hh +++ b/src/base/loader/aout_object.hh @@ -48,8 +48,10 @@ class AoutObject : public ObjectFile public: virtual ~AoutObject() {} - virtual bool loadGlobalSymbols(SymbolTable *symtab); - virtual bool loadLocalSymbols(SymbolTable *symtab); + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); static ObjectFile *tryFile(const std::string &fname, int fd, size_t len, uint8_t *data); diff --git a/src/base/loader/ecoff_object.cc b/src/base/loader/ecoff_object.cc index 134f2d98d..a5a0ad9a4 100644 --- a/src/base/loader/ecoff_object.cc +++ b/src/base/loader/ecoff_object.cc @@ -86,7 +86,7 @@ EcoffObject::EcoffObject(const string &_filename, int _fd, bool -EcoffObject::loadGlobalSymbols(SymbolTable *symtab) +EcoffObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask) { if (!symtab) return false; @@ -115,7 +115,7 @@ EcoffObject::loadGlobalSymbols(SymbolTable *symtab) } bool -EcoffObject::loadLocalSymbols(SymbolTable *symtab) +EcoffObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask) { if (!symtab) return false; diff --git a/src/base/loader/ecoff_object.hh b/src/base/loader/ecoff_object.hh index 05c604b2b..ca6fa2dd0 100644 --- a/src/base/loader/ecoff_object.hh +++ b/src/base/loader/ecoff_object.hh @@ -52,8 +52,10 @@ class EcoffObject : public ObjectFile public: virtual ~EcoffObject() {} - virtual bool loadGlobalSymbols(SymbolTable *symtab); - virtual bool loadLocalSymbols(SymbolTable *symtab); + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); static ObjectFile *tryFile(const std::string &fname, int fd, size_t len, uint8_t *data); diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index 2ca0d4f4a..7339507f6 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -330,13 +330,13 @@ ElfObject::loadSomeSymbols(SymbolTable *symtab, int binding) } bool -ElfObject::loadGlobalSymbols(SymbolTable *symtab) +ElfObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask) { return loadSomeSymbols(symtab, STB_GLOBAL); } bool -ElfObject::loadLocalSymbols(SymbolTable *symtab) +ElfObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask) { return loadSomeSymbols(symtab, STB_LOCAL); } diff --git a/src/base/loader/elf_object.hh b/src/base/loader/elf_object.hh index 9755426b4..fb728b3c5 100644 --- a/src/base/loader/elf_object.hh +++ b/src/base/loader/elf_object.hh @@ -53,8 +53,10 @@ class ElfObject : public ObjectFile public: virtual ~ElfObject() {} - virtual bool loadGlobalSymbols(SymbolTable *symtab); - virtual bool loadLocalSymbols(SymbolTable *symtab); + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); static ObjectFile *tryFile(const std::string &fname, int fd, size_t len, uint8_t *data); diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh index 64085185d..6e98332c5 100644 --- a/src/base/loader/object_file.hh +++ b/src/base/loader/object_file.hh @@ -78,8 +78,10 @@ class ObjectFile virtual bool loadSections(Port *memPort, Addr addrMask = std::numeric_limits<Addr>::max()); - virtual bool loadGlobalSymbols(SymbolTable *symtab) = 0; - virtual bool loadLocalSymbols(SymbolTable *symtab) = 0; + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()) = 0; + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()) = 0; Arch getArch() const { return arch; } OpSys getOpSys() const { return opSys; } diff --git a/src/base/loader/raw_object.cc b/src/base/loader/raw_object.cc index 1faf33426..2a52b0d6e 100644 --- a/src/base/loader/raw_object.cc +++ b/src/base/loader/raw_object.cc @@ -61,21 +61,21 @@ RawObject::RawObject(const std::string &_filename, int _fd, size_t _len, } bool -RawObject::loadGlobalSymbols(SymbolTable *symtab) +RawObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask) { int fnameStart = filename.rfind('/',filename.size()) + 1; int extStart = filename.rfind('.',filename.size()); - symtab->insert(text.baseAddr, filename.substr(fnameStart, + symtab->insert(text.baseAddr & addrMask, filename.substr(fnameStart, extStart-fnameStart) + "_start"); return true; } bool -RawObject::loadLocalSymbols(SymbolTable *symtab) +RawObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask) { int fnameStart = filename.rfind('/',filename.size()) + 1; int extStart = filename.rfind('.',filename.size()); - symtab->insert(text.baseAddr, filename.substr(fnameStart, + symtab->insert(text.baseAddr & addrMask, filename.substr(fnameStart, extStart-fnameStart) + "_start"); return true; } diff --git a/src/base/loader/raw_object.hh b/src/base/loader/raw_object.hh index c7fff4e66..9014a2d30 100644 --- a/src/base/loader/raw_object.hh +++ b/src/base/loader/raw_object.hh @@ -41,8 +41,10 @@ class RawObject: public ObjectFile public: virtual ~RawObject() {} - virtual bool loadGlobalSymbols(SymbolTable *symtab); - virtual bool loadLocalSymbols(SymbolTable *symtab); + virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); + virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = + std::numeric_limits<Addr>::max()); static ObjectFile *tryFile(const std::string &fname, int fd, size_t len, uint8_t *data); diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 7cbbb0b96..31604ad58 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -96,7 +96,7 @@ CPUProgressEvent::description() #if FULL_SYSTEM BaseCPU::BaseCPU(Params *p) - : MemObject(p->name), clock(p->clock), checkInterrupts(true), + : MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true), params(p), number_of_threads(p->numberOfThreads), system(p->system), phase(p->phase) #else diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 1d9b6a93b..8c6b079da 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -70,12 +70,16 @@ class BaseCPU : public MemObject protected: // CPU's clock period in terms of the number of ticks of curTime. Tick clock; + // @todo remove me after debugging with legion done + Tick instCnt; public: // Tick currentTick; inline Tick frequency() const { return Clock::Frequency / clock; } inline Tick cycles(int numCycles) const { return clock * numCycles; } inline Tick curCycle() const { return curTick / clock; } + // @todo remove me after debugging with legion done + Tick instCount() { return instCnt; } /** The next cycle the CPU should be scheduled, given a cache * access or quiesce event returning on this cycle. This function diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index f3b9b51b2..71e974a36 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -279,12 +279,13 @@ Trace::InstRecord::dump(ostream &outs) // outs << endl; } -#if THE_ISA == SPARC_ISA +#if THE_ISA == SPARC_ISA && FULL_SYSTEM // Compare if (flags[LEGION_LOCKSTEP]) { bool compared = false; bool diffPC = false; + bool diffCC = false; bool diffInst = false; bool diffRegs = false; bool diffTpc = false; @@ -317,6 +318,11 @@ Trace::InstRecord::dump(ostream &outs) lgnPc = shared_data->pc & TheISA::PAddrImplMask; if (lgnPc != m5Pc) diffPC = true; + + if (shared_data->cycle_count != + thread->getCpuPtr()->instCount()) + diffCC = true; + if (shared_data->instruction != (SparcISA::MachInst)staticInst->machInst) { diffInst = true; @@ -332,19 +338,19 @@ Trace::InstRecord::dump(ostream &outs) for (int i = 1; i <= MaxTL; i++) { thread->setMiscReg(MISCREG_TL, i); if (thread->readMiscReg(MISCREG_TPC) != - shared_data->tpc[i]) + shared_data->tpc[i-1]) diffTpc = true; if (thread->readMiscReg(MISCREG_TNPC) != - shared_data->tnpc[i]) + shared_data->tnpc[i-1]) diffTnpc = true; if (thread->readMiscReg(MISCREG_TSTATE) != - shared_data->tstate[i]) + shared_data->tstate[i-1]) diffTstate = true; if (thread->readMiscReg(MISCREG_TT) != - shared_data->tt[i]) + shared_data->tt[i-1]) diffTt = true; if (thread->readMiscReg(MISCREG_HTSTATE) != - shared_data->htstate[i]) + shared_data->htstate[i-1]) diffHtstate = true; } thread->setMiscReg(MISCREG_TL, oldTl); @@ -385,8 +391,8 @@ Trace::InstRecord::dump(ostream &outs) if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) diffCleanwin = true; - if (diffPC || diffInst || diffRegs || diffTpc || diffTnpc || - diffTstate || diffTt || diffHpstate || + if (diffPC || diffCC || diffInst || diffRegs || diffTpc || + diffTnpc || diffTstate || diffTt || diffHpstate || diffHtstate || diffHtba || diffPstate || diffY || diffCcr || diffTl || diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || @@ -394,6 +400,8 @@ Trace::InstRecord::dump(ostream &outs) outs << "Differences found between M5 and Legion:"; if (diffPC) outs << " [PC]"; + if (diffCC) + outs << " [CC]"; if (diffInst) outs << " [Instruction]"; if (diffRegs) @@ -445,6 +453,13 @@ Trace::InstRecord::dump(ostream &outs) << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex << lgnPc << endl << endl; + outs << right << setfill(' ') << setw(15) + << "M5 CC: " << "0x"<< setw(16) << setfill('0') + << hex << thread->getCpuPtr()->instCount() << endl; + outs << setfill(' ') << setw(15) + << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex + << shared_data->cycle_count << endl << endl; + outs << setfill(' ') << setw(15) << "M5 Inst: " << "0x"<< setw(8) << setfill('0') << hex << staticInst->machInst @@ -512,19 +527,19 @@ Trace::InstRecord::dump(ostream &outs) thread->setMiscReg(MISCREG_TL, i); printRegPair(outs, "Tpc", thread->readMiscReg(MISCREG_TPC), - shared_data->tpc[i]); + shared_data->tpc[i-1]); printRegPair(outs, "Tnpc", thread->readMiscReg(MISCREG_TNPC), - shared_data->tnpc[i]); + shared_data->tnpc[i-1]); printRegPair(outs, "Tstate", thread->readMiscReg(MISCREG_TSTATE), - shared_data->tstate[i]); + shared_data->tstate[i-1]); printRegPair(outs, "Tt", thread->readMiscReg(MISCREG_TT), - shared_data->tt[i]); + shared_data->tt[i-1]); printRegPair(outs, "Htstate", thread->readMiscReg(MISCREG_HTSTATE), - shared_data->htstate[i]); + shared_data->htstate[i-1]); } thread->setMiscReg(MISCREG_TL, oldTl); outs << endl; diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h index 373fbeb11..bfb88485a 100644 --- a/src/cpu/m5legion_interface.h +++ b/src/cpu/m5legion_interface.h @@ -30,7 +30,7 @@ #include <unistd.h> -#define VERSION 0xA1000005 +#define VERSION 0xA1000006 #define OWN_M5 0x000000AA #define OWN_LEGION 0x00000055 @@ -42,6 +42,8 @@ typedef struct { uint64_t pc; uint64_t new_pc; + uint64_t cycle_count; + uint64_t new_cycle_count; uint32_t instruction; uint32_t new_instruction; uint64_t intregs[32]; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 67611e815..8db864153 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -295,8 +295,11 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) else dcache_latency = dcachePort.sendAtomic(pkt); dcache_access = true; - - assert(pkt->result == Packet::Success); +#if !defined(NDEBUG) + if (pkt->result != Packet::Success) + panic("Unable to find responder for address pa = %#X va = %#X\n", + pkt->req->getPaddr(), pkt->req->getVaddr()); +#endif data = pkt->get<T>(); if (req->isLocked()) { @@ -391,7 +394,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } dcache_access = true; - assert(pkt->result == Packet::Success); +#if !defined(NDEBUG) + if (pkt->result != Packet::Success) + panic("Unable to find responder for address pa = %#X va = %#X\n", + pkt->req->getPaddr(), pkt->req->getVaddr()); +#endif } if (req->isLocked()) { @@ -484,9 +491,15 @@ AtomicSimpleCPU::tick() dcache_access = false; // assume no dcache access preExecute(); + fault = curStaticInst->execute(this, traceData); postExecute(); + // @todo remove me after debugging with legion done + if (curStaticInst && (!curStaticInst->isMicroOp() || + curStaticInst->isLastMicroOp())) + instCnt++; + if (simulate_stalls) { Tick icache_stall = icache_latency - cycles(1); Tick dcache_stall = diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc index 40909c6a1..c36ddeb83 100644 --- a/src/dev/isa_fake.cc +++ b/src/dev/isa_fake.cc @@ -47,7 +47,10 @@ IsaFake::IsaFake(Params *p) if (!params()->retBadAddr) pioSize = p->pio_size; - memset(&retData, p->retData, sizeof(retData)); + retData8 = params()->retData8; + retData16 = params()->retData16; + retData32 = params()->retData32; + retData64 = params()->retData64; } Tick @@ -55,6 +58,9 @@ IsaFake::read(PacketPtr pkt) { assert(pkt->result == Packet::Unknown); + if (params()->warnAccess != "") + warn("Device %s accessed by read to address %#x size=%d\n", + name(), pkt->getAddr(), pkt->getSize()); if (params()->retBadAddr) { DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); @@ -65,16 +71,16 @@ IsaFake::read(PacketPtr pkt) pkt->getAddr(), pkt->getSize()); switch (pkt->getSize()) { case sizeof(uint64_t): - pkt->set(retData); + pkt->set(retData64); break; case sizeof(uint32_t): - pkt->set((uint32_t)retData); + pkt->set(retData32); break; case sizeof(uint16_t): - pkt->set((uint16_t)retData); + pkt->set(retData16); break; case sizeof(uint8_t): - pkt->set((uint8_t)retData); + pkt->set(retData8); break; default: panic("invalid access size!\n"); @@ -87,6 +93,27 @@ IsaFake::read(PacketPtr pkt) Tick IsaFake::write(PacketPtr pkt) { + if (params()->warnAccess != "") { + uint64_t data; + switch (pkt->getSize()) { + case sizeof(uint64_t): + data = pkt->get<uint64_t>(); + break; + case sizeof(uint32_t): + data = pkt->get<uint32_t>(); + break; + case sizeof(uint16_t): + data = pkt->get<uint16_t>(); + break; + case sizeof(uint8_t): + data = pkt->get<uint8_t>(); + break; + default: + panic("invalid access size!\n"); + } + warn("Device %s accessed by write to address %#x size=%d data=%#x\n", + name(), pkt->getAddr(), pkt->getSize(), data); + } if (params()->retBadAddr) { DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); @@ -94,6 +121,25 @@ IsaFake::write(PacketPtr pkt) } else { DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); + + if (params()->updateData) { + switch (pkt->getSize()) { + case sizeof(uint64_t): + retData64 = pkt->get<uint64_t>(); + break; + case sizeof(uint32_t): + retData32 = pkt->get<uint32_t>(); + break; + case sizeof(uint16_t): + retData16 = pkt->get<uint16_t>(); + break; + case sizeof(uint8_t): + retData8 = pkt->get<uint8_t>(); + break; + default: + panic("invalid access size!\n"); + } + } pkt->result = Packet::Success; } return pioDelay; @@ -105,7 +151,12 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake) Param<Tick> pio_latency; Param<Addr> pio_size; Param<bool> ret_bad_addr; - Param<uint8_t> ret_data; + Param<bool> update_data; + Param<std::string> warn_access; + Param<uint8_t> ret_data8; + Param<uint16_t> ret_data16; + Param<uint32_t> ret_data32; + Param<uint64_t> ret_data64; SimObjectParam<Platform *> platform; SimObjectParam<System *> system; @@ -117,7 +168,12 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake) INIT_PARAM(pio_latency, "Programmed IO latency"), INIT_PARAM(pio_size, "Size of address range"), INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"), - INIT_PARAM(ret_data, "Data to return if not bad addr"), + INIT_PARAM(update_data, "Update returned data"), + INIT_PARAM(warn_access, "Warn if this device is touched"), + INIT_PARAM(ret_data8, "Data to return if not bad addr"), + INIT_PARAM(ret_data16, "Data to return if not bad addr"), + INIT_PARAM(ret_data32, "Data to return if not bad addr"), + INIT_PARAM(ret_data64, "Data to return if not bad addr"), INIT_PARAM(platform, "platform"), INIT_PARAM(system, "system object") @@ -131,7 +187,12 @@ CREATE_SIM_OBJECT(IsaFake) p->pio_delay = pio_latency; p->pio_size = pio_size; p->retBadAddr = ret_bad_addr; - p->retData = ret_data; + p->updateData = update_data; + p->warnAccess = warn_access; + p->retData8= ret_data8; + p->retData16 = ret_data16; + p->retData32 = ret_data32; + p->retData64 = ret_data64; p->platform = platform; p->system = system; return new IsaFake(p); diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh index fee41e325..dc2ad48e8 100644 --- a/src/dev/isa_fake.hh +++ b/src/dev/isa_fake.hh @@ -40,6 +40,8 @@ #include "dev/alpha/tsunami.hh" #include "mem/packet.hh" +#include <string> + /** * IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and * rites. It is meant to be placed at an address range @@ -54,11 +56,20 @@ class IsaFake : public BasicPioDevice { Addr pio_size; bool retBadAddr; - uint8_t retData; + bool updateData; + uint8_t retData8; + uint16_t retData16; + uint32_t retData32; + uint64_t retData64; + std::string warnAccess; }; protected: const Params *params() const { return (const Params*)_params; } - uint64_t retData; + uint8_t retData8; + uint16_t retData16; + uint32_t retData32; + uint64_t retData64; + public: /** diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc index 1df6bf15f..5fc787084 100644 --- a/src/dev/sparc/t1000.cc +++ b/src/dev/sparc/t1000.cc @@ -56,50 +56,56 @@ T1000::T1000(const string &name, System *s, IntrControl *ic) Tick T1000::intrFrequency() { - return (Tick)0; + panic("Need implementation\n"); } void T1000::postConsoleInt() { + panic("Need implementation\n"); } void T1000::clearConsoleInt() { + panic("Need implementation\n"); } void T1000::postPciInt(int line) { + panic("Need implementation\n"); } void T1000::clearPciInt(int line) { + panic("Need implementation\n"); } Addr T1000::pciToDma(Addr pciAddr) const { - return (Addr)0; + panic("Need implementation\n"); } Addr T1000::calcConfigAddr(int bus, int dev, int func) { - return (Addr)0; + panic("Need implementation\n"); } void T1000::serialize(std::ostream &os) { + panic("Need implementation\n"); } void T1000::unserialize(Checkpoint *cp, const std::string §ion) { + panic("Need implementation\n"); } BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000) diff --git a/src/dev/sparc/t1000.hh b/src/dev/sparc/t1000.hh index fb82dff11..2955763a9 100644 --- a/src/dev/sparc/t1000.hh +++ b/src/dev/sparc/t1000.hh @@ -30,7 +30,7 @@ /** * @file - * Declaration of top level class for the Tsunami chipset. This class just + * Declaration of top level class for the T1000 platform chips. This class just * retains pointers to all its children so the children can communicate. */ @@ -69,7 +69,7 @@ class T1000 : public Platform virtual void postConsoleInt(); /** - * Clear a posted CPU interrupt (id=55) + * Clear a posted CPU interrupt */ virtual void clearConsoleInt(); diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index e7019f3ac..8226fe8d2 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -2,7 +2,7 @@ from m5 import build_env from m5.params import * from m5.proxy import * from MemObject import MemObject -from Tsunami import BadAddr +from Device import BadAddr class Bus(MemObject): type = 'Bus' @@ -12,7 +12,7 @@ class Bus(MemObject): width = Param.Int(64, "bus width (bytes)") responder_set = Param.Bool(False, "Did the user specify a default responder.") if build_env['FULL_SYSTEM']: - default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") responder = BadAddr(pio_addr=0x0, pio_latency="1ps") + default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") else: default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index 4672d1065..f4b873a60 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,3 +19,19 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + +class IsaFake(BasicPioDevice): + type = 'IsaFake' + pio_size = Param.Addr(0x8, "Size of address range") + ret_data8 = Param.UInt8(0xFF, "Default data to return") + ret_data16 = Param.UInt16(0xFFFF, "Default data to return") + ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") + ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") + ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") + update_data = Param.Bool(False, "Update the data that is returned on writes") + warn_access = Param.String("", "String to print when device is accessed") + +class BadAddr(IsaFake): + ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") + + diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py index 7ac4dd701..810a320be 100644 --- a/src/python/m5/objects/System.py +++ b/src/python/m5/objects/System.py @@ -15,7 +15,7 @@ class System(SimObject): "boot processor frequency") init_param = Param.UInt64(0, "numerical value to pass into simulator") boot_osflags = Param.String("a", "boot flags to pass to the kernel") - kernel = Param.String("file that contains the kernel code") + kernel = Param.String("", "file that contains the kernel code") readfile = Param.String("", "file to read startup script from") symbolfile = Param.String("", "file to get the symbols from") diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py index bb0d37bf8..f4ec5bec4 100644 --- a/src/python/m5/objects/T1000.py +++ b/src/python/m5/objects/T1000.py @@ -1,31 +1,62 @@ from m5.params import * from m5.proxy import * -from Device import BasicPioDevice +from Device import BasicPioDevice, IsaFake, BadAddr from Uart import Uart8250 from Platform import Platform from SimConsole import SimConsole, ConsoleListener -class IsaFake(BasicPioDevice): - type = 'IsaFake' - pio_size = Param.Addr(0x8, "Size of address range") - ret_data = Param.UInt8(0xFF, "Default data to return") - ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") - -class BadAddr(IsaFake): - ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") - class T1000(Platform): type = 'T1000' system = Param.System(Parent.any, "system") - fake_iob = IsaFake(pio_addr=0x8000000000, pio_size=0x7F00000000) + fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000, + warn_access="Accessing Clock Unit -- Unimplemented!") + + fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, + ret_data64=0x0000000000000000, update_data=False, + warn_access="Accessing Memory Banks -- Unimplemented!") + + fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000, + warn_access="Accessing IOB -- Unimplemented!") + + fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000, + warn_access="Accessing JBI -- Unimplemented!") + + fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000, + warn_access="Accessing SSI -- Unimplemented!") - uart = Uart8250(pio_addr=0xfff0c2c000) + hvuart = Uart8250(pio_addr=0xfff0c2c000) + puart0 = Uart8250(pio_addr=0x1f10000000) console = SimConsole(listener = ConsoleListener()) # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): + self.fake_clk.pio = bus.port + self.fake_membnks.pio = bus.port self.fake_iob.pio = bus.port - self.uart.pio = bus.port + self.fake_jbi.pio = bus.port + self.fake_l2_1.pio = bus.port + self.fake_l2_2.pio = bus.port + self.fake_l2_3.pio = bus.port + self.fake_l2_4.pio = bus.port + self.fake_ssi.pio = bus.port + self.puart0.pio = bus.port + self.hvuart.pio = bus.port diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index ffe93727b..c18210bba 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -1,6 +1,6 @@ from m5.params import * from m5.proxy import * -from Device import BasicPioDevice +from Device import BasicPioDevice, IsaFake, BadAddr from Platform import Platform from AlphaConsole import AlphaConsole from Uart import Uart8250 @@ -11,15 +11,6 @@ class TsunamiCChip(BasicPioDevice): type = 'TsunamiCChip' tsunami = Param.Tsunami(Parent.any, "Tsunami") -class IsaFake(BasicPioDevice): - type = 'IsaFake' - pio_size = Param.Addr(0x8, "Size of address range") - ret_data = Param.UInt8(0xFF, "Default data to return") - ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") - -class BadAddr(IsaFake): - ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") - class TsunamiIO(BasicPioDevice): type = 'TsunamiIO' time = Param.UInt64(1136073600, diff --git a/src/sim/system.cc b/src/sim/system.cc index 4b42d41fc..b3ba1b8f1 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -89,36 +89,41 @@ System::System(Params *p) /** * Load the kernel code into memory */ - // Load kernel code - kernel = createObjectFile(params()->kernel_path); - if (kernel == NULL) - fatal("Could not load kernel file %s", params()->kernel_path); - - // Load program sections into memory - kernel->loadSections(&functionalPort, LoadAddrMask); - - // setup entry points - kernelStart = kernel->textBase(); - kernelEnd = kernel->bssBase() + kernel->bssSize(); - kernelEntry = kernel->entryPoint(); - - // load symbols - if (!kernel->loadGlobalSymbols(kernelSymtab)) - panic("could not load kernel symbols\n"); - - if (!kernel->loadLocalSymbols(kernelSymtab)) - panic("could not load kernel local symbols\n"); - - if (!kernel->loadGlobalSymbols(debugSymbolTable)) - panic("could not load kernel symbols\n"); - - if (!kernel->loadLocalSymbols(debugSymbolTable)) - panic("could not load kernel local symbols\n"); - - DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); - DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); - DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); - DPRINTF(Loader, "Kernel loaded...\n"); + if (params()->kernel_path == "") { + warn("No kernel set for full system simulation. Assuming you know what" + " you're doing...\n"); + } else { + // Load kernel code + kernel = createObjectFile(params()->kernel_path); + if (kernel == NULL) + fatal("Could not load kernel file %s", params()->kernel_path); + + // Load program sections into memory + kernel->loadSections(&functionalPort, LoadAddrMask); + + // setup entry points + kernelStart = kernel->textBase(); + kernelEnd = kernel->bssBase() + kernel->bssSize(); + kernelEntry = kernel->entryPoint(); + + // load symbols + if (!kernel->loadGlobalSymbols(kernelSymtab)) + panic("could not load kernel symbols\n"); + + if (!kernel->loadLocalSymbols(kernelSymtab)) + panic("could not load kernel local symbols\n"); + + if (!kernel->loadGlobalSymbols(debugSymbolTable)) + panic("could not load kernel symbols\n"); + + if (!kernel->loadLocalSymbols(debugSymbolTable)) + panic("could not load kernel local symbols\n"); + + DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); + DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); + DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); + DPRINTF(Loader, "Kernel loaded...\n"); + } #endif // FULL_SYSTEM // increment the number of running systms |