diff options
Diffstat (limited to 'src')
72 files changed, 4232 insertions, 2623 deletions
diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py new file mode 100644 index 000000000..0a76913e3 --- /dev/null +++ b/src/arch/arm/ArmNativeTrace.py @@ -0,0 +1,37 @@ +# Copyright (c) 2009 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.SimObject import SimObject +from m5.params import * +from NativeTrace import NativeTrace + +class ArmNativeTrace(NativeTrace): + type = 'ArmNativeTrace' + cxx_class = 'Trace::ArmNativeTrace' + stop_on_pc_error = Param.Bool(True, + "Stop M5 if it and statetrace's pcs are different") diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 519435489..55ecabdc3 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -39,11 +39,14 @@ if env['TARGET_ISA'] == 'arm': Source('insts/mem.cc') Source('insts/pred_inst.cc') Source('insts/static_inst.cc') + Source('nativetrace.cc') Source('pagetable.cc') Source('tlb.cc') Source('vtophys.cc') + SimObject('ArmNativeTrace.py') SimObject('ArmTLB.py') + TraceFlag('Arm') if env['FULL_SYSTEM']: diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 39acc9c08..2315afa9e 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -48,7 +48,11 @@ namespace ArmISA public: void clear() { - // Unknown startup state currently + memset(miscRegs, 0, sizeof(miscRegs)); + CPSR cpsr = 0; + cpsr.mode = MODE_USER; + miscRegs[MISCREG_CPSR] = cpsr; + //XXX We need to initialize the rest of the state. } MiscReg diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index 76d584858..a999b52e9 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -113,8 +113,7 @@ format DataOp { 0x1: decode OPCODE { 0x9: BranchExchange::bx({{ }}); 0xb: PredOp::clz({{ - unsigned lsb = findLsbSet(Rm); - Rd = (lsb > 31) ? 32 : lsb; + Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); }}); } 0x2: decode OPCODE { @@ -319,6 +318,10 @@ format DataOp { 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); } + 0xb: decode LOADOP { + 0x0: WarnUnimpl::fstmx(); + 0x1: WarnUnimpl::fldmx(); + } } 0x7: decode OPCODE_24 { 0: decode CPNUM { @@ -417,12 +420,29 @@ format DataOp { } } } + 0xa: decode MISC_OPCODE { + 0x1: decode MEDIA_OPCODE { + 0xf: decode RN { + 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); + 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); + 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); + } + 0xe: decode RN { + 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); + 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); + 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); + } + } + } } format PredOp { // ARM System Call (SoftWare Interrupt) 1: swi({{ if (testPredicate(Cpsr, condCode)) { - xc->syscall(IMMED_23_0); + if (IMMED_23_0) + xc->syscall(IMMED_23_0); + else + xc->syscall(R7); } }}); } diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index 50e162f3d..e90788c91 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -105,7 +105,8 @@ let {{ def getCcCode(flagtype): icReg = icImm = iv = '' if flagtype == "none": - icReg = icImm = iv = '1' + icReg = icImm = 'Cpsr<29:>' + iv = 'Cpsr<28:>' elif flagtype == "add": icReg = icImm = 'findCarry(32, resTemp, Rn, op2)' iv = 'findOverflow(32, resTemp, Rn, op2)' @@ -125,7 +126,8 @@ let {{ def getImmCcCode(flagtype): ivValue = icValue = '' if flagtype == "none": - icValue = ivValue = '1' + icValue = 'Cpsr<29:>' + ivValue = 'Cpsr<28:>' elif flagtype == "add": icValue = 'findCarry(32, resTemp, Rn, rotated_imm)' ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)' diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index fa41918c1..ac7427dad 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -57,6 +57,7 @@ def operands {{ 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), + 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), #Destination register for load/store double instructions 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), @@ -81,7 +82,10 @@ def operands {{ 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40), 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41), - 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42), - 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43), + 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42), + 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43), + 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44), + 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45), + 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46) }}; diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh index 16bcee47a..d99fa8e49 100644 --- a/src/arch/arm/linux/linux.hh +++ b/src/arch/arm/linux/linux.hh @@ -66,18 +66,7 @@ class ArmLinux : public Linux //@} /// For mmap(). - static const unsigned TGT_MAP_ANONYMOUS = 0x800; - - //@{ - /// For getsysinfo(). - static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string - static const unsigned GSI_CPU_INFO = 59; //!< CPU information - static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type - static const unsigned GSI_MAX_CPU = 30; //!< max # cpu's on this machine - static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system - static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB - static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz - //@} + static const unsigned TGT_MAP_ANONYMOUS = 0x20; //@{ /// For getrusage(). @@ -87,13 +76,8 @@ class ArmLinux : public Linux //@} //@{ - /// For setsysinfo(). - static const unsigned SSI_IEEE_FP_CONTROL = 14; //!< ieee_set_fp_control() - //@} - - //@{ /// ioctl() command codes. - static const unsigned TIOCGETP_ = 0x40067408; + static const unsigned TIOCGETP_ = 0x5401; static const unsigned TIOCSETP_ = 0x80067409; static const unsigned TIOCSETN_ = 0x8006740a; static const unsigned TIOCSETC_ = 0x80067411; @@ -114,15 +98,56 @@ class ArmLinux : public Linux TGT_RLIMIT_DATA = 2, TGT_RLIMIT_STACK = 3, TGT_RLIMIT_CORE = 4, - TGT_RLIMIT_NOFILE = 5, - TGT_RLIMIT_AS = 6, - TGT_RLIMIT_RSS = 7, - TGT_RLIMIT_VMEM = 7, - TGT_RLIMIT_NPROC = 8, - TGT_RLIMIT_MEMLOCK = 9, + TGT_RLIMIT_RSS = 5, + TGT_RLIMIT_NPROC = 6, + TGT_RLIMIT_NOFILE = 7, + TGT_RLIMIT_MEMLOCK = 8, + TGT_RLIMIT_AS = 9, TGT_RLIMIT_LOCKS = 10 }; + typedef struct { + uint32_t st_dev; + uint32_t st_ino; + uint16_t st_mode; + uint16_t st_nlink; + uint16_t st_uid; + uint16_t st_gid; + uint32_t st_rdev; + uint32_t st_size; + uint32_t st_blksize; + uint32_t st_blocks; + uint32_t st_atimeX; + uint32_t st_atime_nsec; + uint32_t st_mtimeX; + uint32_t st_mtime_nsec; + uint32_t st_ctimeX; + uint32_t st_ctime_nsec; + } tgt_stat; + + typedef struct { + uint64_t st_dev; + uint8_t __pad0[4]; + uint32_t __st_ino; + uint32_t st_mode; + uint32_t st_nlink; + uint32_t st_uid; + uint32_t st_gid; + uint64_t st_rdev; + uint8_t __pad3[4]; + int64_t __attribute__ ((aligned (8))) st_size; + uint32_t st_blksize; + uint64_t __attribute__ ((aligned (8))) st_blocks; + uint32_t st_atimeX; + uint32_t st_atime_nsec; + uint32_t st_mtimeX; + uint32_t st_mtime_nsec; + uint32_t st_ctimeX; + uint32_t st_ctime_nsec; + uint64_t st_ino; + } tgt_stat64; + + }; #endif diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc index 7158acfff..56e3588a7 100644 --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -106,7 +106,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = { /* 40 */ SyscallDesc("rmdir", unimplementedFunc), /* 41 */ SyscallDesc("dup", unimplementedFunc), /* 42 */ SyscallDesc("pipe", unimplementedFunc), - /* 43 */ SyscallDesc("times", unimplementedFunc), + /* 43 */ SyscallDesc("times", ignoreFunc), /* 44 */ SyscallDesc("prof", unimplementedFunc), /* 45 */ SyscallDesc("brk", brkFunc), /* 46 */ SyscallDesc("setgid", unimplementedFunc), @@ -260,7 +260,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = { /* 194 */ SyscallDesc("ftruncate64", unimplementedFunc), /* 195 */ SyscallDesc("stat64", unimplementedFunc), /* 196 */ SyscallDesc("lstat64", lstat64Func<ArmLinux>), - /* 197 */ SyscallDesc("fstat64", fstatFunc<ArmLinux>), + /* 197 */ SyscallDesc("fstat64", fstat64Func<ArmLinux>), /* 198 */ SyscallDesc("lchown", unimplementedFunc), /* 199 */ SyscallDesc("getuid", getuidFunc), /* 200 */ SyscallDesc("getgid", getgidFunc), @@ -418,7 +418,6 @@ setTLSFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ThreadContext *tc) { uint32_t tlsPtr = process->getSyscallArg(tc, 0); - TypedBufferArg<Linux::utsname> name(process->getSyscallArg(tc, 0)); tc->getMemPort()->writeBlob(ArmLinuxProcess::commPage + 0x0ff0, (uint8_t *)&tlsPtr, sizeof(tlsPtr)); @@ -448,7 +447,8 @@ ArmLinuxProcess::getDesc(int callnum) // Angel SWI syscalls are unsupported in this release if (callnum == 0x123456) { panic("Attempt to execute an ANGEL_SWI system call (newlib-related)"); - } else if ((callnum & 0x00f00000) == 0x00900000) { + } else if ((callnum & 0x00f00000) == 0x00900000 || + (callnum & 0xf0000) == 0xf0000) { callnum &= 0x000fffff; if ((callnum & 0x0f0000) == 0xf0000) { callnum -= 0x0f0001; @@ -496,7 +496,7 @@ ArmLinuxProcess::startup() { 0x00, 0x30, 0x92, 0xe5, //ldr r3, [r2] 0x00, 0x30, 0x53, 0xe0, //subs r3, r3, r0 - 0x00, 0x10, 0x92, 0x05, //streq r1, [r2] + 0x00, 0x10, 0x82, 0x05, //streq r1, [r2] 0x03, 0x00, 0xa0, 0xe1, //mov r0, r3 0x0e, 0xf0, 0xa0, 0xe1 //usr_ret lr }; diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 42065b0fd..3180669de 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -62,6 +62,9 @@ namespace ArmISA MISCREG_SPSR_UND, MISCREG_SPSR_ABT, MISCREG_FPSR, + MISCREG_FPSID, + MISCREG_FPSCR, + MISCREG_FPEXC, NUM_MISCREGS }; diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc new file mode 100644 index 000000000..1ad9e1a19 --- /dev/null +++ b/src/arch/arm/nativetrace.cc @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/arm/isa_traits.hh" +#include "arch/arm/miscregs.hh" +#include "arch/arm/nativetrace.hh" +#include "cpu/thread_context.hh" +#include "params/ArmNativeTrace.hh" + +namespace Trace { + +#if TRACING_ON +static const char *regNames[] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", + "cpsr" +}; +#endif + +void +Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent) +{ + oldState = state[current]; + current = (current + 1) % 2; + newState = state[current]; + + memcpy(newState, oldState, sizeof(state[0])); + + uint32_t diffVector; + parent->read(&diffVector, sizeof(diffVector)); + diffVector = ArmISA::gtoh(diffVector); + + int changes = 0; + for (int i = 0; i < STATE_NUMVALS; i++) { + if (diffVector & 0x1) { + changed[i] = true; + changes++; + } else { + changed[i] = false; + } + diffVector >>= 1; + } + + uint32_t values[changes]; + parent->read(values, sizeof(values)); + int pos = 0; + for (int i = 0; i < STATE_NUMVALS; i++) { + if (changed[i]) { + newState[i] = ArmISA::gtoh(values[pos++]); + changed[i] = (newState[i] != oldState[i]); + } + } +} + +void +Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) +{ + oldState = state[current]; + current = (current + 1) % 2; + newState = state[current]; + + // Regular int regs + for (int i = 0; i < 15; i++) { + newState[i] = tc->readIntReg(i); + changed[i] = (oldState[i] != newState[i]); + } + + //R15, aliased with the PC + newState[STATE_PC] = tc->readNextPC(); + changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]); + + //CPSR + newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR); + changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); +} + +void +Trace::ArmNativeTrace::check(NativeTraceRecord *record) +{ + ThreadContext *tc = record->getThread(); + // This area is read only on the target. It can't stop there to tell us + // what's going on, so we should skip over anything there also. + if (tc->readNextPC() > 0xffff0000) + return; + nState.update(this); + mState.update(tc); + + bool errorFound = false; + // Regular int regs + for (int i = 0; i < STATE_NUMVALS; i++) { + if (nState.changed[i] || mState.changed[i]) { + const char *vergence = " "; + bool oldMatch = (mState.oldState[i] == nState.oldState[i]); + bool newMatch = (mState.newState[i] == nState.newState[i]); + if (oldMatch && newMatch) { + // The more things change, the more they stay the same. + continue; + } else if (oldMatch && !newMatch) { + vergence = "<>"; + } else if (!oldMatch && newMatch) { + vergence = "><"; + } + errorFound = true; + if (!nState.changed[i]) { + DPRINTF(ExecRegDelta, "%s [%5s] "\ + "Native: %#010x "\ + "M5: %#010x => %#010x\n", + vergence, regNames[i], + nState.newState[i], + mState.oldState[i], mState.newState[i]); + } else if (!mState.changed[i]) { + DPRINTF(ExecRegDelta, "%s [%5s] "\ + "Native: %#010x => %#010x "\ + "M5: %#010x \n", + vergence, regNames[i], + nState.oldState[i], nState.newState[i], + mState.newState[i]); + } else { + DPRINTF(ExecRegDelta, "%s [%5s] "\ + "Native: %#010x => %#010x "\ + "M5: %#010x => %#010x\n", + vergence, regNames[i], + nState.oldState[i], nState.newState[i], + mState.oldState[i], mState.newState[i]); + } + } + } + if (errorFound) { + StaticInstPtr inst = record->getStaticInst(); + assert(inst); + bool ran = true; + if (inst->isMicroop()) { + ran = false; + inst = record->getMacroStaticInst(); + } + assert(inst); + record->traceInst(inst, ran); + + bool pcError = (mState.newState[STATE_PC] != + nState.newState[STATE_PC]); + if (stopOnPCError && pcError) + panic("Native trace detected an error in control flow!"); + } +} + +} /* namespace Trace */ + +//////////////////////////////////////////////////////////////////////// +// +// ExeTracer Simulation Object +// +Trace::ArmNativeTrace * +ArmNativeTraceParams::create() +{ + return new Trace::ArmNativeTrace(this); +}; diff --git a/src/arch/arm/nativetrace.hh b/src/arch/arm/nativetrace.hh new file mode 100644 index 000000000..7467e3378 --- /dev/null +++ b/src/arch/arm/nativetrace.hh @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_ARM_NATIVETRACE_HH__ +#define __ARCH_ARM_NATIVETRACE_HH__ + +#include "base/types.hh" +#include "cpu/nativetrace.hh" +#include "params/ArmNativeTrace.hh" + +namespace Trace { + +class ArmNativeTrace : public NativeTrace +{ + public: + enum StateID { + STATE_R0, + STATE_R1, + STATE_R2, + STATE_R3, + STATE_R4, + STATE_R5, + STATE_R6, + STATE_R7, + STATE_R8, + STATE_R9, + STATE_R10, + STATE_R11, + STATE_FP = STATE_R11, + STATE_R12, + STATE_R13, + STATE_SP = STATE_R13, + STATE_R14, + STATE_LR = STATE_R14, + STATE_R15, + STATE_PC = STATE_R15, + STATE_CPSR, + STATE_NUMVALS + }; + + protected: + struct ThreadState { + bool changed[STATE_NUMVALS]; + uint32_t state[2][STATE_NUMVALS]; + uint32_t *newState; + uint32_t *oldState; + int current; + void update(NativeTrace *parent); + void update(ThreadContext *tc); + + ThreadState() + { + for (int i = 0; i < STATE_NUMVALS; i++) { + changed[i] = false; + state[0][i] = state[1][i] = 0; + current = 0; + newState = state[0]; + oldState = state[1]; + } + } + }; + + ThreadState nState, mState; + + bool stopOnPCError; + + public: + typedef ArmNativeTraceParams Params; + + const Params * + params() const + { + return dynamic_cast<const Params *>(_params); + } + + ArmNativeTrace(const Params *p) : + NativeTrace(p), stopOnPCError(p->stop_on_pc_error) + {} + + void check(NativeTraceRecord *record); +}; + +} /* namespace Trace */ + +#endif // __ARCH_ARM_NATIVETRACE_HH__ diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 365d5b22c..cd7cc9736 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -46,7 +46,7 @@ using namespace ArmISA; ArmLiveProcess::ArmLiveProcess(LiveProcessParams *params, ObjectFile *objFile) : LiveProcess(params, objFile) { - stack_base = 0xc0000000L; + stack_base = 0xbf000000L; // Set pointer for next thread stack. Reserve 8M for main stack. next_thread_stack_base = stack_base - (8 * 1024 * 1024); @@ -88,73 +88,239 @@ ArmLiveProcess::copyStringArray32(std::vector<std::string> &strings, void ArmLiveProcess::argsInit(int intSize, int pageSize) { + typedef AuxVector<uint32_t> auxv_t; + std::vector<auxv_t> auxv; + + string filename; + if (argv.size() < 1) + filename = ""; + else + filename = argv[0]; + + //We want 16 byte alignment + uint64_t align = 16; + // Overloaded argsInit so that we can fine-tune for ARM architecture Process::startup(); // load object file into target memory objFile->loadSections(initVirtMem); - // Calculate how much space we need for arg & env arrays. - int argv_array_size = intSize * (argv.size() + 1); - int envp_array_size = intSize * (envp.size() + 1); - int arg_data_size = 0; - for (int i = 0; i < argv.size(); ++i) { - arg_data_size += argv[i].size() + 1; + enum ArmCpuFeature { + Arm_Swp = 1 << 0, + Arm_Half = 1 << 1, + Arm_Thumb = 1 << 2, + Arm_26Bit = 1 << 3, + Arm_FastMult = 1 << 4, + Arm_Fpa = 1 << 5, + Arm_Vfp = 1 << 6, + Arm_Edsp = 1 << 7, + Arm_Java = 1 << 8, + Arm_Iwmmxt = 1 << 9, + Arm_Crunch = 1 << 10 + }; + + //Setup the auxilliary vectors. These will already have endian conversion. + //Auxilliary vectors are loaded only for elf formatted executables. + ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); + if (elfObject) { + uint32_t features = + Arm_Swp | + Arm_Half | + Arm_Thumb | +// Arm_26Bit | + Arm_FastMult | +// Arm_Fpa | + Arm_Vfp | + Arm_Edsp | + Arm_Java | +// Arm_Iwmmxt | +// Arm_Crunch | + 0; + + //Bits which describe the system hardware capabilities + //XXX Figure out what these should be + auxv.push_back(auxv_t(M5_AT_HWCAP, features)); + //The system page size + auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::VMPageSize)); + //Frequency at which times() increments + auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64)); + // For statically linked executables, this is the virtual address of the + // program header tables if they appear in the executable image + auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); + // This is the size of a program header entry from the elf file. + auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); + // This is the number of program headers from the original elf file. + auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); + //This is the address of the elf "interpreter", It should be set + //to 0 for regular executables. It should be something else + //(not sure what) for dynamic libraries. + auxv.push_back(auxv_t(M5_AT_BASE, 0)); + + //XXX Figure out what this should be. + auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); + //The entry point to the program + auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); + //Different user and group IDs + auxv.push_back(auxv_t(M5_AT_UID, uid())); + auxv.push_back(auxv_t(M5_AT_EUID, euid())); + auxv.push_back(auxv_t(M5_AT_GID, gid())); + auxv.push_back(auxv_t(M5_AT_EGID, egid())); + //Whether to enable "secure mode" in the executable + auxv.push_back(auxv_t(M5_AT_SECURE, 0)); + //The filename of the program + auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); + //The string "v51" with unknown meaning + auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); } + + //Figure out how big the initial stack nedes to be + + // A sentry NULL void pointer at the top of the stack. + int sentry_size = intSize; + + string platform = "v51"; + int platform_size = platform.size() + 1; + + // The aux vectors are put on the stack in two groups. The first group are + // the vectors that are generated as the elf is loaded. The second group + // are the ones that were computed ahead of time and include the platform + // string. + int aux_data_size = filename.size() + 1; + int env_data_size = 0; for (int i = 0; i < envp.size(); ++i) { env_data_size += envp[i].size() + 1; } + int arg_data_size = 0; + for (int i = 0; i < argv.size(); ++i) { + arg_data_size += argv[i].size() + 1; + } - int space_needed = - argv_array_size + envp_array_size + arg_data_size + env_data_size; - if (space_needed < 16*1024) - space_needed = 16*1024; + int info_block_size = + sentry_size + env_data_size + arg_data_size + + aux_data_size + platform_size; + + //Each auxilliary vector is two 4 byte words + int aux_array_size = intSize * 2 * (auxv.size() + 1); + + int envp_array_size = intSize * (envp.size() + 1); + int argv_array_size = intSize * (argv.size() + 1); + + int argc_size = intSize; + + //Figure out the size of the contents of the actual initial frame + int frame_size = + info_block_size + + aux_array_size + + envp_array_size + + argv_array_size + + argc_size; + + //There needs to be padding after the auxiliary vector data so that the + //very bottom of the stack is aligned properly. + int partial_size = frame_size; + int aligned_partial_size = roundUp(partial_size, align); + int aux_padding = aligned_partial_size - partial_size; + + int space_needed = frame_size + aux_padding; - // set bottom of stack stack_min = stack_base - space_needed; - // align it - stack_min = roundDown(stack_min, pageSize); + stack_min = roundDown(stack_min, align); stack_size = stack_base - stack_min; + // map memory - pTable->allocate(stack_min, roundUp(stack_size, pageSize)); + pTable->allocate(roundDown(stack_min, pageSize), + roundUp(stack_size, pageSize)); // map out initial stack contents - Addr argv_array_base = stack_min + intSize; // room for argc - Addr envp_array_base = argv_array_base + argv_array_size; - Addr arg_data_base = envp_array_base + envp_array_size; - Addr env_data_base = arg_data_base + arg_data_size; + uint32_t sentry_base = stack_base - sentry_size; + uint32_t aux_data_base = sentry_base - aux_data_size; + uint32_t env_data_base = aux_data_base - env_data_size; + uint32_t arg_data_base = env_data_base - arg_data_size; + uint32_t platform_base = arg_data_base - platform_size; + uint32_t auxv_array_base = platform_base - aux_array_size - aux_padding; + uint32_t envp_array_base = auxv_array_base - envp_array_size; + uint32_t argv_array_base = envp_array_base - argv_array_size; + uint32_t argc_base = argv_array_base - argc_size; + + DPRINTF(Stack, "The addresses of items on the initial stack:\n"); + DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); + DPRINTF(Stack, "0x%x - env data\n", env_data_base); + DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); + DPRINTF(Stack, "0x%x - platform base\n", platform_base); + DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); + DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); + DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); + DPRINTF(Stack, "0x%x - argc \n", argc_base); + DPRINTF(Stack, "0x%x - stack min\n", stack_min); // write contents to stack - uint64_t argc = argv.size(); - if (intSize == 8) - argc = htog((uint64_t)argc); - else if (intSize == 4) - argc = htog((uint32_t)argc); - else - panic("Unknown int size"); - initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize); + // figure out argc + uint32_t argc = argv.size(); + uint32_t guestArgc = ArmISA::htog(argc); - copyStringArray32(argv, argv_array_base, arg_data_base, initVirtMem); - copyStringArray32(envp, envp_array_base, env_data_base, initVirtMem); + //Write out the sentry void * + uint32_t sentry_NULL = 0; + initVirtMem->writeBlob(sentry_base, + (uint8_t*)&sentry_NULL, sentry_size); - /* - //uint8_t insns[] = {0xe5, 0x9f, 0x00, 0x08, 0xe1, 0xa0, 0xf0, 0x0e}; - uint8_t insns[] = {0x08, 0x00, 0x9f, 0xe5, 0x0e, 0xf0, 0xa0, 0xe1}; + //Fix up the aux vectors which point to other data + for (int i = auxv.size() - 1; i >= 0; i--) { + if (auxv[i].a_type == M5_AT_PLATFORM) { + auxv[i].a_val = platform_base; + initVirtMem->writeString(platform_base, platform.c_str()); + } else if (auxv[i].a_type == M5_AT_EXECFN) { + auxv[i].a_val = aux_data_base; + initVirtMem->writeString(aux_data_base, filename.c_str()); + } + } - initVirtMem->writeBlob(0xffff0fe0, insns, 8); - */ + //Copy the aux stuff + for(int x = 0; x < auxv.size(); x++) + { + initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, + (uint8_t*)&(auxv[x].a_type), intSize); + initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, + (uint8_t*)&(auxv[x].a_val), intSize); + } + //Write out the terminating zeroed auxilliary vector + const uint64_t zero = 0; + initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(), + (uint8_t*)&zero, 2 * intSize); - ThreadContext *tc = system->getThreadContext(contextIds[0]); + copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); + copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); + + initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); - tc->setIntReg(ArgumentReg1, argc); - tc->setIntReg(ArgumentReg2, argv_array_base); + ThreadContext *tc = system->getThreadContext(contextIds[0]); + //Set the stack pointer register tc->setIntReg(StackPointerReg, stack_min); + //A pointer to a function to run when the program exits. We'll set this + //to zero explicitly to make sure this isn't used. + tc->setIntReg(ArgumentReg0, 0); + //Set argument regs 1 and 2 to argv[0] and envp[0] respectively + if (argv.size() > 0) { + tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size - + argv[argv.size() - 1].size() - 1); + } else { + tc->setIntReg(ArgumentReg1, 0); + } + if (envp.size() > 0) { + tc->setIntReg(ArgumentReg2, env_data_base + env_data_size - + envp[envp.size() - 1].size() - 1); + } else { + tc->setIntReg(ArgumentReg2, 0); + } Addr prog_entry = objFile->entryPoint(); tc->setPC(prog_entry); tc->setNextPC(prog_entry + sizeof(MachInst)); + + //Align the "stack_min" to a page boundary. + stack_min = roundDown(stack_min, pageSize); } ArmISA::IntReg diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 8cce5c152..febc6d081 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -147,7 +147,7 @@ TLB::checkCacheability(RequestPtr &req) // or by the TLB entry if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { // mark request as uncacheable - req->setFlags(req->getFlags() | Request::UNCACHEABLE); + req->setFlags(Request::UNCACHEABLE); } return NoFault; } diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 6faab054f..815784388 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -178,18 +178,18 @@ void MipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode) { // modify SRS Ctl - Save CSS, put ESS into CSS - StatusReg status = tc->readMiscReg(Status); + StatusReg status = tc->readMiscReg(MISCREG_STATUS); if (status.exl != 1 && status.bev != 1) { // SRS Ctl is modified only if Status_EXL and Status_BEV are not set - SRSCtlReg srsCtl = tc->readMiscReg(SRSCtl); + SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); srsCtl.pss = srsCtl.css; srsCtl.css = srsCtl.ess; - tc->setMiscRegNoEffect(SRSCtl, srsCtl); + tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl); } // set EXL bit (don't care if it is already set!) status.exl = 1; - tc->setMiscRegNoEffect(Status, status); + tc->setMiscRegNoEffect(MISCREG_STATUS, status); // write EPC // CHECK ME or FIXME or FIX ME or POSSIBLE HACK @@ -198,21 +198,21 @@ MipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode) tc->readPC(), tc->readNextPC(), tc->readNextNPC()); int bd = 0; if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) { - tc->setMiscRegNoEffect(EPC, tc->readPC() - sizeof(MachInst)); + tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC() - sizeof(MachInst)); // In the branch delay slot? set CAUSE_31 bd = 1; } else { - tc->setMiscRegNoEffect(EPC, tc->readPC()); + tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC()); // In the branch delay slot? reset CAUSE_31 bd = 0; } // Set Cause_EXCCODE field - CauseReg cause = tc->readMiscReg(Cause); + CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); cause.excCode = excCode; cause.bd = bd; cause.ce = 0; - tc->setMiscRegNoEffect(Cause, cause); + tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); } void @@ -223,12 +223,12 @@ ArithmeticFault::invoke(ThreadContext *tc) // Set new PC Addr HandlerBase; - StatusReg status = tc->readMiscReg(Status); + StatusReg status = tc->readMiscReg(MISCREG_STATUS); // Here, the handler is dependent on BEV, which is not modified by // setExceptionState() if (!status.bev) { // See MIPS ARM Vol 3, Revision 2, Page 38 - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); } else { HandlerBase = 0xBFC00200; } @@ -240,12 +240,12 @@ StoreAddressErrorFault::invoke(ThreadContext *tc) { DPRINTF(MipsPRA, "%s encountered.\n", name()); setExceptionState(tc, 0x5); - tc->setMiscRegNoEffect(BadVAddr, badVAddr); + tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); // Set new PC Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); setHandlerPC(HandlerBase, tc); } @@ -258,7 +258,7 @@ TrapFault::invoke(ThreadContext *tc) // Set new PC Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); setHandlerPC(HandlerBase, tc); } @@ -270,7 +270,7 @@ BreakpointFault::invoke(ThreadContext *tc) // Set new PC Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); setHandlerPC(HandlerBase, tc); } @@ -279,23 +279,23 @@ DtbInvalidFault::invoke(ThreadContext *tc) { DPRINTF(MipsPRA, "%s encountered.\n", name()); - tc->setMiscRegNoEffect(BadVAddr, badVAddr); - EntryHiReg entryHi = tc->readMiscReg(EntryHi); + tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); + EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); entryHi.asid = entryHiAsid; entryHi.vpn2 = entryHiVPN2; entryHi.vpn2x = entryHiVPN2X; - tc->setMiscRegNoEffect(EntryHi, entryHi); + tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); - ContextReg context = tc->readMiscReg(Context); + ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); context.badVPN2 = contextBadVPN2; - tc->setMiscRegNoEffect(Context, context); + tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); setExceptionState(tc, 0x3); // Set new PC Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); setHandlerPC(HandlerBase, tc); } @@ -304,12 +304,12 @@ AddressErrorFault::invoke(ThreadContext *tc) { DPRINTF(MipsPRA, "%s encountered.\n", name()); setExceptionState(tc, 0x4); - tc->setMiscRegNoEffect(BadVAddr, badVAddr); + tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); // Set new PC Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); setHandlerPC(HandlerBase, tc); } @@ -318,51 +318,51 @@ ItbInvalidFault::invoke(ThreadContext *tc) { DPRINTF(MipsPRA, "%s encountered.\n", name()); setExceptionState(tc, 0x2); - tc->setMiscRegNoEffect(BadVAddr, badVAddr); - EntryHiReg entryHi = tc->readMiscReg(EntryHi); + tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); + EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); entryHi.asid = entryHiAsid; entryHi.vpn2 = entryHiVPN2; entryHi.vpn2x = entryHiVPN2X; - tc->setMiscRegNoEffect(EntryHi, entryHi); + tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); - ContextReg context = tc->readMiscReg(Context); + ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); context.badVPN2 = contextBadVPN2; - tc->setMiscRegNoEffect(Context, context); + tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); // Set new PC Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); setHandlerPC(HandlerBase,tc); DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n", - HandlerBase, tc->readMiscReg(EPC)); + HandlerBase, tc->readMiscReg(MISCREG_EPC)); } void ItbRefillFault::invoke(ThreadContext *tc) { - DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), badVAddr); + DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR); Addr HandlerBase; - tc->setMiscRegNoEffect(BadVAddr, badVAddr); - EntryHiReg entryHi = tc->readMiscReg(EntryHi); + tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); + EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); entryHi.asid = entryHiAsid; entryHi.vpn2 = entryHiVPN2; entryHi.vpn2x = entryHiVPN2X; - tc->setMiscRegNoEffect(EntryHi, entryHi); - ContextReg context = tc->readMiscReg(Context); + tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); + ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); context.badVPN2 = contextBadVPN2; - tc->setMiscRegNoEffect(Context, context); + tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); - StatusReg status = tc->readMiscReg(Status); + StatusReg status = tc->readMiscReg(MISCREG_STATUS); // Since handler depends on EXL bit, must check EXL bit before setting it!! // See MIPS ARM Vol 3, Revision 2, Page 38 if (status.exl == 1) { // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); } else { // Offset 0x000 - HandlerBase = tc->readMiscReg(EBase); + HandlerBase = tc->readMiscReg(MISCREG_EBASE); } setExceptionState(tc, 0x2); @@ -375,26 +375,26 @@ DtbRefillFault::invoke(ThreadContext *tc) // Set new PC DPRINTF(MipsPRA, "%s encountered.\n", name()); Addr HandlerBase; - tc->setMiscRegNoEffect(BadVAddr, badVAddr); - EntryHiReg entryHi = tc->readMiscReg(EntryHi); + tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); + EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); entryHi.asid = entryHiAsid; entryHi.vpn2 = entryHiVPN2; entryHi.vpn2x = entryHiVPN2X; - tc->setMiscRegNoEffect(EntryHi, entryHi); + tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); - ContextReg context = tc->readMiscReg(Context); + ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); context.badVPN2 = contextBadVPN2; - tc->setMiscRegNoEffect(Context, context); + tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); - StatusReg status = tc->readMiscReg(Status); + StatusReg status = tc->readMiscReg(MISCREG_STATUS); // Since handler depends on EXL bit, must check EXL bit before setting it!! // See MIPS ARM Vol 3, Revision 2, Page 38 if (status.exl) { // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); } else { // Offset 0x000 - HandlerBase = tc->readMiscReg(EBase); + HandlerBase = tc->readMiscReg(MISCREG_EBASE); } setExceptionState(tc, 0x3); @@ -406,21 +406,21 @@ void TLBModifiedFault::invoke(ThreadContext *tc) { DPRINTF(MipsPRA, "%s encountered.\n", name()); - tc->setMiscRegNoEffect(BadVAddr, badVAddr); - EntryHiReg entryHi = tc->readMiscReg(EntryHi); + tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr); + EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); entryHi.asid = entryHiAsid; entryHi.vpn2 = entryHiVPN2; entryHi.vpn2x = entryHiVPN2X; - tc->setMiscRegNoEffect(EntryHi, entryHi); + tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi); - ContextReg context = tc->readMiscReg(Context); + ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); context.badVPN2 = contextBadVPN2; - tc->setMiscRegNoEffect(Context, context); + tc->setMiscRegNoEffect(MISCREG_CONTEXT, context); // Set new PC Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); setExceptionState(tc, 0x1); setHandlerPC(HandlerBase, tc); @@ -435,7 +435,7 @@ SystemCallFault::invoke(ThreadContext *tc) // Set new PC Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); setHandlerPC(HandlerBase, tc); } @@ -447,13 +447,13 @@ InterruptFault::invoke(ThreadContext *tc) setExceptionState(tc, 0x0A); Addr HandlerBase; - CauseReg cause = tc->readMiscRegNoEffect(Cause); + CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); if (cause.iv) { // Offset 200 for release 2 - HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(EBase); + HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); } else { //Ofset at 180 for release 1 - HandlerBase = vect() + tc->readMiscRegNoEffect(EBase); + HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); } setHandlerPC(HandlerBase, tc); @@ -475,9 +475,9 @@ ResetFault::invoke(ThreadContext *tc) #endif // Set Coprocessor 1 (Floating Point) To Usable - StatusReg status = tc->readMiscRegNoEffect(Status); + StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); status.cu.cu1 = 1; - tc->setMiscReg(Status, status); + tc->setMiscReg(MISCREG_STATUS, status); } void @@ -488,7 +488,7 @@ ReservedInstructionFault::invoke(ThreadContext *tc) setExceptionState(tc, 0x0A); Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscRegNoEffect(EBase); + HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE); setHandlerPC(HandlerBase, tc); #else panic("%s encountered.\n", name()); @@ -517,13 +517,13 @@ CoprocessorUnusableFault::invoke(ThreadContext *tc) setExceptionState(tc, 0xb); // The ID of the coprocessor causing the exception is stored in // CoprocessorUnusableFault::coProcID - CauseReg cause = tc->readMiscReg(Cause); + CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); cause.ce = coProcID; - tc->setMiscRegNoEffect(Cause, cause); + tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); Addr HandlerBase; // Offset 0x180 - General Exception Vector - HandlerBase = vect() + tc->readMiscReg(EBase); + HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE); setHandlerPC(HandlerBase, tc); #else diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc index 4b1f37856..096aa628f 100755 --- a/src/arch/mips/interrupts.cc +++ b/src/arch/mips/interrupts.cc @@ -42,15 +42,15 @@ namespace MipsISA static inline uint8_t getCauseIP(ThreadContext *tc) { - CauseReg cause = tc->readMiscRegNoEffect(Cause); + CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); return cause.ip; } static inline void setCauseIP(ThreadContext *tc, uint8_t val) { - CauseReg cause = tc->readMiscRegNoEffect(Cause); + CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); cause.ip = val; - tc->setMiscRegNoEffect(Cause, cause); + tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); } void @@ -111,14 +111,14 @@ Interrupts::getInterrupt(ThreadContext * tc) DPRINTF(Interrupt, "Interrupts getInterrupt\n"); //Check if there are any outstanding interrupts - StatusReg status = tc->readMiscRegNoEffect(Status); + StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); // Interrupts must be enabled, error level must be 0 or interrupts // inhibited, and exception level must be 0 or interrupts inhibited if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) { // Software interrupts & hardware interrupts are handled in software. // So if any interrupt that isn't masked is detected, jump to interrupt // handler - CauseReg cause = tc->readMiscRegNoEffect(Cause); + CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); if (status.im && cause.ip) { DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n", (unsigned)status.im, (unsigned)cause.ip); @@ -132,8 +132,8 @@ Interrupts::getInterrupt(ThreadContext * tc) bool Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const { - MiscReg compare = tc->readMiscRegNoEffect(Compare); - MiscReg count = tc->readMiscRegNoEffect(Count); + MiscReg compare = tc->readMiscRegNoEffect(MISCREG_COMPARE); + MiscReg count = tc->readMiscRegNoEffect(MISCREG_COUNT); if (compare == count && count != 0) return true; return false; @@ -153,7 +153,7 @@ Interrupts::interruptsPending(ThreadContext *tc) const if (onCpuTimerInterrupt(tc)) { DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n"); //determine timer interrupt IP # - IntCtlReg intCtl = tc->readMiscRegNoEffect(IntCtl); + IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL); uint8_t intStatus = getCauseIP(tc); intStatus |= 1 << intCtl.ipti; setCauseIP(tc, intStatus); diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 6ef6f9f41..3c8c9a986 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -129,10 +129,14 @@ void ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) { // Initialize all Per-VPE regs - uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask, - VPESchedule, VPEScheFBack, VPEOpt, SRSConf0, - SRSConf1, SRSConf2, SRSConf3, SRSConf4, - EBase + uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL, + MISCREG_VPE_CONF0, MISCREG_VPE_CONF1, + MISCREG_YQMASK, + MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK, + MISCREG_VPE_OPT, MISCREG_SRS_CONF0, + MISCREG_SRS_CONF1, MISCREG_SRS_CONF2, + MISCREG_SRS_CONF3, MISCREG_SRS_CONF4, + MISCREG_EBASE }; uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4; for (int i = 0; i < num_vpe_regs; i++) { @@ -143,9 +147,12 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) } // Initialize all Per-TC regs - uint32_t per_tc_regs[] = { Status, TCStatus, TCBind, TCRestart, TCHalt, - TCContext, TCSchedule, TCScheFBack, Debug, - LLAddr + uint32_t per_tc_regs[] = { MISCREG_STATUS, + MISCREG_TC_STATUS, MISCREG_TC_BIND, + MISCREG_TC_RESTART, MISCREG_TC_HALT, + MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE, + MISCREG_TC_SCHEFBACK, + MISCREG_DEBUG, MISCREG_LLADDR }; uint32_t num_tc_regs = sizeof(per_tc_regs) / 4; @@ -181,34 +188,34 @@ ISA::reset(std::string core_name, ThreadID num_threads, // =================================================== DPRINTF(MipsPRA, "Initializing CP0 State.... "); - PRIdReg procId = readMiscRegNoEffect(PRId); + PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID); procId.coOp = cp.CP0_PRId_CompanyOptions; procId.coId = cp.CP0_PRId_CompanyID; procId.procId = cp.CP0_PRId_ProcessorID; procId.rev = cp.CP0_PRId_Revision; - setMiscRegNoEffect(PRId, procId); + setMiscRegNoEffect(MISCREG_PRID, procId); // Now, create Write Mask for ProcID register - MiscReg ProcID_Mask = 0; // Read-Only register - replaceBits(ProcID_Mask, 0, 32, 0); - setRegMask(PRId, ProcID_Mask); + MiscReg procIDMask = 0; // Read-Only register + replaceBits(procIDMask, 0, 32, 0); + setRegMask(MISCREG_PRID, procIDMask); // Config - ConfigReg cfg = readMiscRegNoEffect(Config); + ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG); cfg.be = cp.CP0_Config_BE; cfg.at = cp.CP0_Config_AT; cfg.ar = cp.CP0_Config_AR; cfg.mt = cp.CP0_Config_MT; cfg.vi = cp.CP0_Config_VI; cfg.m = 1; - setMiscRegNoEffect(Config, cfg); + setMiscRegNoEffect(MISCREG_CONFIG, cfg); // Now, create Write Mask for Config register MiscReg cfg_Mask = 0x7FFF0007; replaceBits(cfg_Mask, 0, 32, 0); - setRegMask(Config, cfg_Mask); + setRegMask(MISCREG_CONFIG, cfg_Mask); // Config1 - Config1Reg cfg1 = readMiscRegNoEffect(Config1); + Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1); cfg1.mmuSize = cp.CP0_Config1_MMU; cfg1.is = cp.CP0_Config1_IS; cfg1.il = cp.CP0_Config1_IL; @@ -223,14 +230,14 @@ ISA::reset(std::string core_name, ThreadID num_threads, cfg1.c2 = cp.CP0_Config1_C2; cfg1.pc = cp.CP0_Config1_PC; cfg1.m = cp.CP0_Config1_M; - setMiscRegNoEffect(Config1, cfg1); + setMiscRegNoEffect(MISCREG_CONFIG1, cfg1); // Now, create Write Mask for Config register MiscReg cfg1_Mask = 0; // Read Only Register replaceBits(cfg1_Mask, 0, 32, 0); - setRegMask(Config1, cfg1_Mask); + setRegMask(MISCREG_CONFIG1, cfg1_Mask); // Config2 - Config2Reg cfg2 = readMiscRegNoEffect(Config2); + Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2); cfg2.tu = cp.CP0_Config2_TU; cfg2.ts = cp.CP0_Config2_TS; cfg2.tl = cp.CP0_Config2_TL; @@ -240,14 +247,14 @@ ISA::reset(std::string core_name, ThreadID num_threads, cfg2.sl = cp.CP0_Config2_SL; cfg2.sa = cp.CP0_Config2_SA; cfg2.m = cp.CP0_Config2_M; - setMiscRegNoEffect(Config2, cfg2); + setMiscRegNoEffect(MISCREG_CONFIG2, cfg2); // Now, create Write Mask for Config register MiscReg cfg2_Mask = 0x7000F000; // Read Only Register replaceBits(cfg2_Mask, 0, 32, 0); - setRegMask(Config2, cfg2_Mask); + setRegMask(MISCREG_CONFIG2, cfg2_Mask); // Config3 - Config3Reg cfg3 = readMiscRegNoEffect(Config3); + Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3); cfg3.dspp = cp.CP0_Config3_DSPP; cfg3.lpa = cp.CP0_Config3_LPA; cfg3.veic = cp.CP0_Config3_VEIC; @@ -256,79 +263,79 @@ ISA::reset(std::string core_name, ThreadID num_threads, cfg3.mt = cp.CP0_Config3_MT; cfg3.sm = cp.CP0_Config3_SM; cfg3.tl = cp.CP0_Config3_TL; - setMiscRegNoEffect(Config3, cfg3); + setMiscRegNoEffect(MISCREG_CONFIG3, cfg3); // Now, create Write Mask for Config register MiscReg cfg3_Mask = 0; // Read Only Register replaceBits(cfg3_Mask, 0, 32, 0); - setRegMask(Config3, cfg3_Mask); + setRegMask(MISCREG_CONFIG3, cfg3_Mask); // EBase - CPUNum - EBaseReg eBase = readMiscRegNoEffect(EBase); + EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE); eBase.cpuNum = cp.CP0_EBase_CPUNum; replaceBits(eBase, 31, 31, 1); - setMiscRegNoEffect(EBase, eBase); + setMiscRegNoEffect(MISCREG_EBASE, eBase); // Now, create Write Mask for Config register MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the // entire register is read only replaceBits(EB_Mask, 0, 32, 0); - setRegMask(EBase, EB_Mask); + setRegMask(MISCREG_EBASE, EB_Mask); // SRS Control - HSS (Highest Shadow Set) - SRSCtlReg scsCtl = readMiscRegNoEffect(SRSCtl); + SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL); scsCtl.hss = cp.CP0_SrsCtl_HSS; - setMiscRegNoEffect(SRSCtl, scsCtl); + setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl); // Now, create Write Mask for the SRS Ctl register MiscReg SC_Mask = 0x0000F3C0; replaceBits(SC_Mask, 0, 32, 0); - setRegMask(SRSCtl, SC_Mask); + setRegMask(MISCREG_SRSCTL, SC_Mask); // IntCtl - IPTI, IPPCI - IntCtlReg intCtl = readMiscRegNoEffect(IntCtl); + IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL); intCtl.ipti = cp.CP0_IntCtl_IPTI; intCtl.ippci = cp.CP0_IntCtl_IPPCI; - setMiscRegNoEffect(IntCtl, intCtl); + setMiscRegNoEffect(MISCREG_INTCTL, intCtl); // Now, create Write Mask for the IntCtl register MiscReg IC_Mask = 0x000003E0; replaceBits(IC_Mask, 0, 32, 0); - setRegMask(IntCtl, IC_Mask); + setRegMask(MISCREG_INTCTL, IC_Mask); // Watch Hi - M - FIXME (More than 1 Watch register) - WatchHiReg watchHi = readMiscRegNoEffect(WatchHi0); + WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0); watchHi.m = cp.CP0_WatchHi_M; - setMiscRegNoEffect(WatchHi0, watchHi); + setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi); // Now, create Write Mask for the IntCtl register MiscReg wh_Mask = 0x7FFF0FFF; replaceBits(wh_Mask, 0, 32, 0); - setRegMask(WatchHi0, wh_Mask); + setRegMask(MISCREG_WATCHHI0, wh_Mask); // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair) - PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(PerfCnt0); + PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0); perfCntCtl.m = cp.CP0_PerfCtr_M; perfCntCtl.w = cp.CP0_PerfCtr_W; - setMiscRegNoEffect(PerfCnt0, perfCntCtl); + setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl); // Now, create Write Mask for the IntCtl register MiscReg pc_Mask = 0x00007FF; replaceBits(pc_Mask, 0, 32, 0); - setRegMask(PerfCnt0, pc_Mask); + setRegMask(MISCREG_PERFCNT0, pc_Mask); // Random - setMiscRegNoEffect(CP0_Random, 63); + setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63); // Now, create Write Mask for the IntCtl register MiscReg random_Mask = 0; replaceBits(random_Mask, 0, 32, 0); - setRegMask(CP0_Random, random_Mask); + setRegMask(MISCREG_CP0_RANDOM, random_Mask); // PageGrain - PageGrainReg pageGrain = readMiscRegNoEffect(PageGrain); + PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN); pageGrain.esp = cp.CP0_Config3_SP; - setMiscRegNoEffect(PageGrain, pageGrain); + setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain); // Now, create Write Mask for the IntCtl register MiscReg pg_Mask = 0x10000000; replaceBits(pg_Mask, 0, 32, 0); - setRegMask(PageGrain, pg_Mask); + setRegMask(MISCREG_PAGEGRAIN, pg_Mask); // Status - StatusReg status = readMiscRegNoEffect(Status); + StatusReg status = readMiscRegNoEffect(MISCREG_STATUS); // Only CU0 and IE are modified on a reset - everything else needs // to be controlled on a per CPU model basis @@ -340,91 +347,90 @@ ISA::reset(std::string core_name, ThreadID num_threads, // Enable BEV bit on a reset status.bev = 1; - setMiscRegNoEffect(Status, status); + setMiscRegNoEffect(MISCREG_STATUS, status); // Now, create Write Mask for the Status register MiscReg stat_Mask = 0xFF78FF17; replaceBits(stat_Mask, 0, 32, 0); - setRegMask(Status, stat_Mask); + setRegMask(MISCREG_STATUS, stat_Mask); // MVPConf0 - MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0); + MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0); mvpConf0.tca = 1; mvpConf0.pvpe = num_vpes - 1; mvpConf0.ptc = num_threads - 1; - setMiscRegNoEffect(MVPConf0, mvpConf0); + setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0); // VPEConf0 - VPEConf0Reg vpeConf0 = readMiscRegNoEffect(VPEConf0); + VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0); vpeConf0.mvp = 1; - setMiscRegNoEffect(VPEConf0, vpeConf0); + setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0); // TCBind for (ThreadID tid = 0; tid < num_threads; tid++) { - TCBindReg tcBind = readMiscRegNoEffect(TCBind, tid); + TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid); tcBind.curTC = tid; - setMiscRegNoEffect(TCBind, tcBind, tid); + setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid); } // TCHalt - TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt); + TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT); tcHalt.h = 0; - setMiscRegNoEffect(TCHalt, tcHalt); + setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt); // TCStatus // Set TCStatus Activated to 1 for the initial thread that is running - TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus); + TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS); tcStatus.a = 1; - setMiscRegNoEffect(TCStatus, tcStatus); + setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus); // Set Dynamically Allocatable bit to 1 for all other threads for (ThreadID tid = 1; tid < num_threads; tid++) { - tcStatus = readMiscRegNoEffect(TCStatus, tid); + tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); tcStatus.da = 1; - setMiscRegNoEffect(TCStatus, tcStatus, tid); + setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid); } - MiscReg Mask = 0x7FFFFFFF; + MiscReg mask = 0x7FFFFFFF; // Now, create Write Mask for the Index register - replaceBits(Mask, 0, 32, 0); - setRegMask(Index, Mask); + replaceBits(mask, 0, 32, 0); + setRegMask(MISCREG_INDEX, mask); - Mask = 0x3FFFFFFF; - replaceBits(Mask, 0, 32, 0); - setRegMask(EntryLo0, Mask); - setRegMask(EntryLo1, Mask); + mask = 0x3FFFFFFF; + replaceBits(mask, 0, 32, 0); + setRegMask(MISCREG_ENTRYLO0, mask); + setRegMask(MISCREG_ENTRYLO1, mask); - Mask = 0xFF800000; - replaceBits(Mask, 0, 32, 0); - setRegMask(Context, Mask); + mask = 0xFF800000; + replaceBits(mask, 0, 32, 0); + setRegMask(MISCREG_CONTEXT, mask); - Mask = 0x1FFFF800; - replaceBits(Mask, 0, 32, 0); - setRegMask(PageMask, Mask); + mask = 0x1FFFF800; + replaceBits(mask, 0, 32, 0); + setRegMask(MISCREG_PAGEMASK, mask); - Mask = 0x0; - replaceBits(Mask, 0, 32, 0); - setRegMask(BadVAddr, Mask); - setRegMask(LLAddr, Mask); + mask = 0x0; + replaceBits(mask, 0, 32, 0); + setRegMask(MISCREG_BADVADDR, mask); + setRegMask(MISCREG_LLADDR, mask); - Mask = 0x08C00300; - replaceBits(Mask, 0, 32, 0); - setRegMask(Cause, Mask); + mask = 0x08C00300; + replaceBits(mask, 0, 32, 0); + setRegMask(MISCREG_CAUSE, mask); } inline unsigned ISA::getVPENum(ThreadID tid) { - TCBindReg tcBind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid]; + TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid]; return tcBind.curVPE; } MiscReg -ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid) +ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n", @@ -437,9 +443,8 @@ ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid) // Status to TCStatus depending on current thread //template <class TC> MiscReg -ISA::readMiscReg(int reg_idx, ThreadContext *tc, ThreadID tid) +ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) { - int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, @@ -451,9 +456,8 @@ ISA::readMiscReg(int reg_idx, ThreadContext *tc, ThreadID tid) } void -ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid) +ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) { - int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, @@ -465,10 +469,8 @@ ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid) } void -ISA::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid) +ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid) { - // return; - int misc_reg = reg_idx - Ctrl_Base_DepTag; unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, @@ -482,10 +484,9 @@ ISA::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid) // be overwritten. Make sure to handle those particular registers // with care! void -ISA::setMiscReg(int reg_idx, const MiscReg &val, +ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, ThreadID tid) { - int misc_reg = reg_idx - Ctrl_Base_DepTag; int reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); @@ -546,12 +547,12 @@ ISA::updateCPU() // EVALUATE CP0 STATE FOR MIPS MT // /////////////////////////////////////////////////////////////////// - MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0); + MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0); ThreadID num_threads = mvpConf0.ptc + 1; for (ThreadID tid = 0; tid < num_threads; tid++) { - TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus, tid); - TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt, tid); + TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); + TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid); //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs if (tcHalt.h == 1 || tcStatus.a == 0) { diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 60bc15513..c531347d2 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -46,8 +46,12 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode FUNCTION_LO { 0x1: decode MOVCI { format BasicOp { - 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }}); - 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }}); + 0: movf({{ + Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; + }}); + 1: movt({{ + Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; + }}); } } @@ -69,8 +73,11 @@ decode OPCODE_HI default Unknown::unknown() { 0x0:decode SRL { 0: srl({{ Rd = Rt.uw >> SA; }}); - //Hardcoded assuming 32-bit ISA, probably need parameter here - 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); + //Hardcoded assuming 32-bit ISA, + //probably need parameter here + 1: rotr({{ + Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA); + }}); } } @@ -93,8 +100,12 @@ decode OPCODE_HI default Unknown::unknown() { 0x6: decode SRLV { 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); - //Hardcoded assuming 32-bit ISA, probably need parameter here - 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); + //Hardcoded assuming 32-bit ISA, + //probably need parameter here + 1: rotrv({{ + Rd = (Rt.uw << (32 - Rs<4:0>)) | + (Rt.uw >> Rs<4:0>); + }}); } 0x7: srav({{ @@ -102,14 +113,13 @@ decode OPCODE_HI default Unknown::unknown() { uint32_t temp = Rt >> shift_amt; - if ( (Rt & 0x80000000) > 0 ) { - uint32_t mask = 0x80000000; - for(int i=0; i < shift_amt; i++) { - temp |= mask; - mask = mask >> 1; - } + if ((Rt & 0x80000000) > 0) { + uint32_t mask = 0x80000000; + for (int i = 0; i < shift_amt; i++) { + temp |= mask; + mask = mask >> 1; } - + } Rd = temp; }}); } @@ -149,9 +159,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); #if FULL_SYSTEM - 0x4: syscall({{ - fault = new SystemCallFault(); - }}); + 0x4: syscall({{ fault = new SystemCallFault(); }}); #else 0x4: syscall({{ xc->syscall(R2); }}, IsSerializeAfter, IsNonSpeculative); @@ -163,9 +171,11 @@ decode OPCODE_HI default Unknown::unknown() { } 0x2: decode FUNCTION_LO { - 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp, IsIprAccess); + 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, + IntMultOp, IsIprAccess); 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); - 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp, IsIprAccess); + 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, + IntMultOp, IsIprAccess); 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); } @@ -176,16 +186,18 @@ decode OPCODE_HI default Unknown::unknown() { } format HiLoOp { - 0x2: div({{ if (Rt.sd != 0) { - HI0 = Rs.sd % Rt.sd; - LO0 = Rs.sd / Rt.sd; - } + 0x2: div({{ + if (Rt.sd != 0) { + HI0 = Rs.sd % Rt.sd; + LO0 = Rs.sd / Rt.sd; + } }}, IntDivOp); - 0x3: divu({{ if (Rt.ud != 0) { - HI0 = Rs.ud % Rt.ud; - LO0 = Rs.ud / Rt.ud; - } + 0x3: divu({{ + if (Rt.ud != 0) { + HI0 = Rs.ud % Rt.ud; + LO0 = Rs.ud / Rt.ud; + } }}, IntDivOp); } } @@ -193,47 +205,51 @@ decode OPCODE_HI default Unknown::unknown() { 0x4: decode HINT { 0x0: decode FUNCTION_LO { format IntOp { - 0x0: add({{ /* More complicated since an ADD can cause an arithmetic overflow exception */ - int64_t Src1 = Rs.sw; - int64_t Src2 = Rt.sw; - int64_t temp_result; -#if FULL_SYSTEM - if(((Src1 >> 31) & 1) == 1) - Src1 |= 0x100000000LL; + 0x0: add({{ + /* More complicated since an ADD can cause + an arithmetic overflow exception */ + int64_t Src1 = Rs.sw; + int64_t Src2 = Rt.sw; + int64_t temp_result; +#if FULL_SYSTEM + if (((Src1 >> 31) & 1) == 1) + Src1 |= 0x100000000LL; #endif - temp_result = Src1 + Src2; -#if FULL_SYSTEM - if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ + temp_result = Src1 + Src2; +#if FULL_SYSTEM + if (bits(temp_result, 31) == + bits(temp_result, 32)) { #endif - Rd.sw = temp_result; -#if FULL_SYSTEM - } else{ - fault = new ArithmeticFault(); - } + Rd.sw = temp_result; +#if FULL_SYSTEM + } else { + fault = new ArithmeticFault(); + } #endif - - }}); + }}); 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 0x2: sub({{ - /* More complicated since an SUB can cause an arithmetic overflow exception */ - int64_t Src1 = Rs.sw; - int64_t Src2 = Rt.sw; - int64_t temp_result = Src1 - Src2; + /* More complicated since an SUB can cause + an arithmetic overflow exception */ + int64_t Src1 = Rs.sw; + int64_t Src2 = Rt.sw; + int64_t temp_result = Src1 - Src2; #if FULL_SYSTEM - if(((temp_result >> 31) & 1) == ((temp_result>>32) & 1)){ + if (bits(temp_result, 31) == + bits(temp_result, 32)) { #endif - Rd.sw = temp_result; + Rd.sw = temp_result; #if FULL_SYSTEM - } else{ - fault = new ArithmeticFault(); - } + } else { + fault = new ArithmeticFault(); + } #endif - }}); - 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); - 0x4: and({{ Rd = Rs & Rt;}}); - 0x5: or({{ Rd = Rs | Rt;}}); - 0x6: xor({{ Rd = Rs ^ Rt;}}); - 0x7: nor({{ Rd = ~(Rs | Rt);}}); + }}); + 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw; }}); + 0x4: and({{ Rd = Rs & Rt; }}); + 0x5: or({{ Rd = Rs | Rt; }}); + 0x6: xor({{ Rd = Rs ^ Rt; }}); + 0x7: nor({{ Rd = ~(Rs | Rt); }}); } } } @@ -241,8 +257,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x5: decode HINT { 0x0: decode FUNCTION_LO { format IntOp{ - 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); - 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); + 0x2: slt({{ Rd.sw = (Rs.sw < Rt.sw) ? 1 : 0 }}); + 0x3: sltu({{ Rd.uw = (Rs.uw < Rt.uw) ? 1 : 0 }}); } } } @@ -272,11 +288,15 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode REGIMM_LO { format TrapImm { 0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }}); - 0x1: tgeiu({{ cond = (Rs.uw >= (uint32_t)((int32_t)((int16_t)INTIMM))); }}); + 0x1: tgeiu({{ + cond = (Rs.uw >= (uint32_t)(int32_t)(int16_t)INTIMM); + }}); 0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }}); - 0x3: tltiu({{ cond = (Rs.uw < (uint32_t)((int32_t)((int16_t)INTIMM))); }}); - 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}}); - 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}}); + 0x3: tltiu({{ + cond = (Rs.uw < (uint32_t)(int32_t)(int16_t)INTIMM); + }}); + 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM); }}); + 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM); }}); } } @@ -293,7 +313,8 @@ decode OPCODE_HI default Unknown::unknown() { } 0x3: decode REGIMM_LO { - // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL) + // from Table 5-4 MIPS32 REGIMM Encoding of rt Field + // (DSP ASE MANUAL) 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); format WarnUnimpl { 0x7: synci(); @@ -302,9 +323,9 @@ decode OPCODE_HI default Unknown::unknown() { } format Jump { - 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); - 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall, - Link); + 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}); + 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, + IsCall, Link); } format Branch { @@ -321,41 +342,47 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode OPCODE_LO { format IntImmOp { 0x0: addi({{ - int64_t Src1 = Rs.sw; - int64_t Src2 = imm; - int64_t temp_result; + int64_t Src1 = Rs.sw; + int64_t Src2 = imm; + int64_t temp_result; #if FULL_SYSTEM - if(((Src1 >> 31) & 1) == 1) - Src1 |= 0x100000000LL; + if (((Src1 >> 31) & 1) == 1) + Src1 |= 0x100000000LL; #endif - temp_result = Src1 + Src2; + temp_result = Src1 + Src2; #if FULL_SYSTEM - if(((temp_result >> 31) & 1) == ((temp_result >> 32) & 1)){ + if (bits(temp_result, 31) == bits(temp_result, 32)) { #endif - Rt.sw = temp_result; + Rt.sw = temp_result; #if FULL_SYSTEM - } else{ - fault = new ArithmeticFault(); - } + } else { + fault = new ArithmeticFault(); + } #endif - }}); - 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); - 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); + }}); + 0x1: addiu({{ Rt.sw = Rs.sw + imm; }}); + 0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }}); //Edited to include MIPS AVP Pass/Fail instructions and //default to the sltiu instruction 0x3: decode RS_RT_INTIMM { - 0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }}); - 0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }}); - default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); + 0xabc1: BasicOp::fail({{ + exitSimLoop("AVP/SRVP Test Failed"); + }}); + 0xabc2: BasicOp::pass({{ + exitSimLoop("AVP/SRVP Test Passed"); + }}); + default: sltiu({{ + Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0; + }}); } - 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); - 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); - 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); + 0x4: andi({{ Rt.sw = Rs.sw & zextImm; }}); + 0x5: ori({{ Rt.sw = Rs.sw | zextImm; }}); + 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm; }}); 0x7: decode RS { - 0x0: lui({{ Rt = imm << 16}}); + 0x0: lui({{ Rt = imm << 16; }}); } } } @@ -364,104 +391,108 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-11 MIPS32 COP0 Encoding of rs Field 0x0: decode RS_MSB { 0x0: decode RS { - format CP0Control { - 0x0: mfc0({{ - Config3Reg config3 = Config3; - PageGrainReg pageGrain = PageGrain; - Rt = CP0_RD_SEL; - /* Hack for PageMask */ - if (RD == 5) { - // PageMask - if(config3.sp == 0 || pageGrain.esp == 0) - Rt &= 0xFFFFE7FF; - } - }}); - 0x4: mtc0({{ - CP0_RD_SEL = Rt; - CauseReg cause = Cause; - IntCtlReg intCtl = IntCtl; - if (RD == 11) { - // Compare - if (cause.ti == 1) { - cause.ti = 0; - int offset = 10; // corresponding to cause.ip0 - offset += intCtl.ipti - 2; - replaceBits(cause, offset, offset, 0); - } - } - Cause = cause; - }}); - } - format CP0Unimpl { - 0x1: dmfc0(); - 0x5: dmtc0(); - default: unknown(); - } - format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions + format CP0Control { + 0x0: mfc0({{ + Config3Reg config3 = Config3; + PageGrainReg pageGrain = PageGrain; + Rt = CP0_RD_SEL; + /* Hack for PageMask */ + if (RD == 5) { + // PageMask + if (config3.sp == 0 || pageGrain.esp == 0) + Rt &= 0xFFFFE7FF; + } + }}); + 0x4: mtc0({{ + CP0_RD_SEL = Rt; + CauseReg cause = Cause; + IntCtlReg intCtl = IntCtl; + if (RD == 11) { + // Compare + if (cause.ti == 1) { + cause.ti = 0; + int offset = 10; // corresponding to cause.ip0 + offset += intCtl.ipti - 2; + replaceBits(cause, offset, offset, 0); + } + } + Cause = cause; + }}); + } + format CP0Unimpl { + 0x1: dmfc0(); + 0x5: dmtc0(); + default: unknown(); + } + format MT_MFTR { + // Decode MIPS MT MFTR instruction into sub-instructions 0x8: decode MT_U { 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) + Ctrl_Base_DepTag); }}); 0x1: decode SEL { - 0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }}); + 0x0: mftgpr({{ + data = xc->readRegOtherThread(RT); + }}); 0x1: decode RT { - 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }}); - 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }}); - 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }}); - 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }}); - 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }}); - 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }}); - 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }}); - 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }}); - 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }}); - 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }}); - 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }}); - 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }}); - 0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }}); - default: CP0Unimpl::unknown(); + 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }}); + 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }}); + 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }}); + 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }}); + 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }}); + 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }}); + 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }}); + 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }}); + 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }}); + 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }}); + 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }}); + 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }}); + 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }}); + default: CP0Unimpl::unknown(); } 0x2: decode MT_H { 0x0: mftc1({{ data = xc->readRegOtherThread(RT + FP_Base_DepTag); - }}); + }}); 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + FP_Base_DepTag); - }}); - } - 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR + + }}); + } + 0x3: cftc1({{ + uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag); - switch (RT) - { - case 0: - data = xc->readRegOtherThread(MipsISA::FIR + - Ctrl_Base_DepTag); - break; - case 25: - data = (fcsr_val & 0xFE000000 >> 24) - | (fcsr_val & 0x00800000 >> 23); - break; - case 26: - data = fcsr_val & 0x0003F07C; - break; - case 28: - data = (fcsr_val & 0x00000F80) - | (fcsr_val & 0x01000000 >> 21) - | (fcsr_val & 0x00000003); - break; - case 31: - data = fcsr_val; - break; - default: - fatal("FP Control Value (%d) Not Valid"); - } - }}); - default: CP0Unimpl::unknown(); - } - } + switch (RT) { + case 0: + data = xc->readRegOtherThread(FLOATREG_FIR + + Ctrl_Base_DepTag); + break; + case 25: + data = (fcsr_val & 0xFE000000 >> 24) | + (fcsr_val & 0x00800000 >> 23); + break; + case 26: + data = fcsr_val & 0x0003F07C; + break; + case 28: + data = (fcsr_val & 0x00000F80) | + (fcsr_val & 0x01000000 >> 21) | + (fcsr_val & 0x00000003); + break; + case 31: + data = fcsr_val; + break; + default: + fatal("FP Control Value (%d) Not Valid"); + } + }}); + default: CP0Unimpl::unknown(); + } + } } - format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions + format MT_MTTR { + // Decode MIPS MT MTTR instruction into sub-instructions 0xC: decode MT_U { 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, Rt); @@ -469,91 +500,90 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode SEL { 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 0x1: decode RT { - 0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt); + 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt); }}); - 0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0, + 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0, Rt); }}); - 0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0, + 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0, Rt); }}); - 0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1, + 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1, Rt); }}); - 0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1, + 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1, Rt); }}); - 0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1, + 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1, Rt); }}); - 0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2, + 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2, Rt); }}); - 0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2, + 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2, Rt); }}); - 0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2, + 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2, Rt); }}); - 0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3, + 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3, Rt); }}); - 0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3, + 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3, Rt); }}); - 0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt); + 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt); }}); - 0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }}); - default: CP0Unimpl::unknown(); + 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); + default: CP0Unimpl::unknown(); } - 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + - FP_Base_DepTag); - data = insertBits(data, top_bit, bottom_bit, Rt); - xc->setRegOtherThread(RD + FP_Base_DepTag, data); - }}); - 0x3: cttc1({{ uint32_t data; - switch (RD) - { - case 25: - data = 0 | (Rt.uw<7:1> << 25) // move 31...25 - | (FCSR & 0x01000000) // bit 24 - | (FCSR & 0x004FFFFF);// bit 22...0 - break; - - case 26: - data = 0 | (FCSR & 0xFFFC0000) // move 31...18 - | Rt.uw<17:12> << 12 // bit 17...12 - | (FCSR & 0x00000F80) << 7// bit 11...7 - | Rt.uw<6:2> << 2 // bit 6...2 - | (FCSR & 0x00000002); // bit 1...0 - break; - - case 28: - data = 0 | (FCSR & 0xFE000000) // move 31...25 - | Rt.uw<2:2> << 24 // bit 24 - | (FCSR & 0x00FFF000) << 23// bit 23...12 - | Rt.uw<11:7> << 7 // bit 24 - | (FCSR & 0x000007E) - | Rt.uw<1:0>;// bit 22...0 - break; - - case 31: - data = Rt.uw; - break; - - default: - panic("FP Control Value (%d) Not Available. Ignoring Access to" - "Floating Control Status Register", FS); - } - xc->setRegOtherThread(FCSR, data); - }}); - default: CP0Unimpl::unknown(); + 0x2: mttc1({{ + uint64_t data = xc->readRegOtherThread(RD + + FP_Base_DepTag); + data = insertBits(data, top_bit, + bottom_bit, Rt); + xc->setRegOtherThread(RD + FP_Base_DepTag, + data); + }}); + 0x3: cttc1({{ + uint32_t data; + switch (RD) { + case 25: + data = (Rt.uw<7:1> << 25) | // move 31-25 + (FCSR & 0x01000000) | // bit 24 + (FCSR & 0x004FFFFF); // bit 22-0 + break; + case 26: + data = (FCSR & 0xFFFC0000) | // move 31-18 + Rt.uw<17:12> << 12 | // bit 17-12 + (FCSR & 0x00000F80) << 7 | // bit 11-7 + Rt.uw<6:2> << 2 | // bit 6-2 + (FCSR & 0x00000002); // bit 1...0 + break; + case 28: + data = (FCSR & 0xFE000000) | // move 31-25 + Rt.uw<2:2> << 24 | // bit 24 + (FCSR & 0x00FFF000) << 23 | // bit 23-12 + Rt.uw<11:7> << 7 | // bit 24 + (FCSR & 0x000007E) | + Rt.uw<1:0>; // bit 22-0 + break; + case 31: + data = Rt.uw; + break; + default: + panic("FP Control Value (%d) " + "Not Available. Ignoring " + "Access to Floating Control " + "Status Register", FS); + } + xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); + }}); + default: CP0Unimpl::unknown(); } } } - - 0xB: decode RD { format MT_Control { 0x0: decode POS { @@ -577,11 +607,10 @@ decode OPCODE_HI default Unknown::unknown() { }}); default:CP0Unimpl::unknown(); } - default:CP0Unimpl::unknown(); + default:CP0Unimpl::unknown(); } - default:CP0Unimpl::unknown(); - } - + default:CP0Unimpl::unknown(); + } 0x1: decode POS { 0xF: decode SEL { 0x1: decode SC { @@ -599,41 +628,41 @@ decode OPCODE_HI default Unknown::unknown() { }}); default:CP0Unimpl::unknown(); } - default:CP0Unimpl::unknown(); + default:CP0Unimpl::unknown(); } default:CP0Unimpl::unknown(); } } 0xC: decode POS { - 0x0: decode SC { - 0x0: CP0Control::di({{ - StatusReg status = Status; - ConfigReg config = Config; - // Rev 2.0 or beyond? - if (config.ar >= 1) { - Rt = status; - status.ie = 0; - } else { - // Enable this else branch once we - // actually set values for Config on init - fault = new ReservedInstructionFault(); - } - Status = status; - }}); - 0x1: CP0Control::ei({{ - StatusReg status = Status; - ConfigReg config = Config; - if (config.ar >= 1) { - Rt = status; - status.ie = 1; - } else { - fault = new ReservedInstructionFault(); - } - }}); - default:CP0Unimpl::unknown(); - } + 0x0: decode SC { + 0x0: CP0Control::di({{ + StatusReg status = Status; + ConfigReg config = Config; + // Rev 2.0 or beyond? + if (config.ar >= 1) { + Rt = status; + status.ie = 0; + } else { + // Enable this else branch once we + // actually set values for Config on init + fault = new ReservedInstructionFault(); + } + Status = status; + }}); + 0x1: CP0Control::ei({{ + StatusReg status = Status; + ConfigReg config = Config; + if (config.ar >= 1) { + Rt = status; + status.ie = 1; + } else { + fault = new ReservedInstructionFault(); + } + }}); + default:CP0Unimpl::unknown(); + } } - default: CP0Unimpl::unknown(); + default: CP0Unimpl::unknown(); } format CP0Control { 0xA: rdpgpr({{ @@ -655,251 +684,264 @@ decode OPCODE_HI default Unknown::unknown() { } }}); } - - } + } //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 0x1: decode FUNCTION { - format CP0Control { - 0x18: eret({{ - StatusReg status = Status; - ConfigReg config = Config; - SRSCtlReg srsCtl = SRSCtl; - DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); - if (status.erl == 1) { - status.erl = 0; - NPC = ErrorEPC; - // Need to adjust NNPC, otherwise things break - NNPC = ErrorEPC + sizeof(MachInst); - } else { - NPC = EPC; - // Need to adjust NNPC, otherwise things break - NNPC = EPC + sizeof(MachInst); - status.exl = 0; - if (config.ar >=1 && - srsCtl.hss > 0 && - status.bev == 0) { - srsCtl.css = srsCtl.pss; - //xc->setShadowSet(srsCtl.pss); + format CP0Control { + 0x18: eret({{ + StatusReg status = Status; + ConfigReg config = Config; + SRSCtlReg srsCtl = SRSCtl; + DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); + if (status.erl == 1) { + status.erl = 0; + NPC = ErrorEPC; + // Need to adjust NNPC, otherwise things break + NNPC = ErrorEPC + sizeof(MachInst); + } else { + NPC = EPC; + // Need to adjust NNPC, otherwise things break + NNPC = EPC + sizeof(MachInst); + status.exl = 0; + if (config.ar >=1 && + srsCtl.hss > 0 && + status.bev == 0) { + srsCtl.css = srsCtl.pss; + //xc->setShadowSet(srsCtl.pss); + } } - } - LLFlag = 0; - Status = status; - SRSCtl = srsCtl; - }},IsReturn,IsSerializing,IsERET); - - 0x1F: deret({{ - DebugReg debug = Debug; - if (debug.dm == 1) { - debug.dm = 1; - debug.iexi = 0; - NPC = DEPC; - } else { - // Undefined; - } - Debug = debug; - }}, IsReturn, IsSerializing, IsERET); - } - format CP0TLB { - 0x01: tlbr({{ - MipsISA::PTE *PTEntry = xc->tcBase()->getITBPtr()->getEntry(Index & 0x7FFFFFFF); - if(PTEntry == NULL) - { - fatal("Invalid PTE Entry received on a TLBR instruction\n"); - } - /* Setup PageMask */ - PageMask = (PTEntry->Mask << 11); // If 1KB pages are not enabled, a read of PageMask must return 0b00 in bits 12, 11 - /* Setup EntryHi */ - EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); - /* Setup Entry Lo0 */ - EntryLo0 = ((PTEntry->PFN0 << 6) | (PTEntry->C0 << 3) | (PTEntry->D0 << 2) | (PTEntry->V0 << 1) | PTEntry->G); - /* Setup Entry Lo1 */ - EntryLo1 = ((PTEntry->PFN1 << 6) | (PTEntry->C1 << 3) | (PTEntry->D1 << 2) | (PTEntry->V1 << 1) | PTEntry->G); - }}); // Need to hook up to TLB - - 0x02: tlbwi({{ - //Create PTE - MipsISA::PTE NewEntry; - //Write PTE - NewEntry.Mask = (Addr)(PageMask >> 11); - NewEntry.VPN = (Addr)(EntryHi >> 11); - /* PageGrain _ ESP Config3 _ SP */ - if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) { - // If 1KB pages are *NOT* enabled, lowest bits of the - // mask are 0b11 for TLB writes - NewEntry.Mask |= 0x3; - // Reset bits 0 and 1 if 1KB pages are not enabled - NewEntry.VPN &= 0xFFFFFFFC; - } - NewEntry.asid = (uint8_t)(EntryHi & 0xFF); - - NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); - NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); - NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); - NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); - NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); - NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); - NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); - NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); - NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); - /* Now, compute the AddrShiftAmount and OffsetMask - TLB - optimizations */ - /* Addr Shift Amount for 1KB or larger pages */ - if ((NewEntry.Mask & 0xFFFF) == 3) { - NewEntry.AddrShiftAmount = 12; - } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) { - NewEntry.AddrShiftAmount = 10; - } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) { - NewEntry.AddrShiftAmount = 14; - } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) { - NewEntry.AddrShiftAmount = 16; - } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) { - NewEntry.AddrShiftAmount = 18; - } else if ((NewEntry.Mask & 0xFF00) == 0x0300) { - NewEntry.AddrShiftAmount = 20; - } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) { - NewEntry.AddrShiftAmount = 22; - } else if ((NewEntry.Mask & 0xF000) == 0x3000) { - NewEntry.AddrShiftAmount = 24; - } else if ((NewEntry.Mask & 0xC000) == 0xC000) { - NewEntry.AddrShiftAmount = 26; - } else if ((NewEntry.Mask & 0x30000) == 0x30000) { - NewEntry.AddrShiftAmount = 28; - } else { - fatal("Invalid Mask Pattern Detected!\n"); - } - NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1); - - MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); - Config3Reg config3 = Config3; - PageGrainReg pageGrain = PageGrain; - int SP = 0; - if (bits(config3, config3.sp) == 1 && - bits(pageGrain, pageGrain.esp) == 1) { - SP = 1; - } - IndexReg index = Index; - Ptr->insertAt(NewEntry, Index & 0x7FFFFFFF, SP); - }}); - 0x06: tlbwr({{ - //Create PTE - MipsISA::PTE NewEntry; - //Write PTE - NewEntry.Mask = (Addr)(PageMask >> 11); - NewEntry.VPN = (Addr)(EntryHi >> 11); - /* PageGrain _ ESP Config3 _ SP */ - if (((PageGrain >> 28) & 1) == 0 || - (( Config3 >> 4) & 1) ==0) { - // If 1KB pages are *NOT* enabled, lowest bits of - // the mask are 0b11 for TLB writes - NewEntry.Mask |= 0x3; - // Reset bits 0 and 1 if 1KB pages are not enabled - NewEntry.VPN &= 0xFFFFFFFC; - } - NewEntry.asid = (uint8_t)(EntryHi & 0xFF); - - NewEntry.PFN0 = (Addr)(EntryLo0 >> 6); - NewEntry.PFN1 = (Addr)(EntryLo1 >> 6); - NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1); - NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1); - NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1); - NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1); - NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); - NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); - NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); - /* Now, compute the AddrShiftAmount and OffsetMask - - TLB optimizations */ - /* Addr Shift Amount for 1KB or larger pages */ - if ((NewEntry.Mask & 0xFFFF) == 3){ - NewEntry.AddrShiftAmount = 12; - } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) { - NewEntry.AddrShiftAmount = 10; - } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) { - NewEntry.AddrShiftAmount = 14; - } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) { - NewEntry.AddrShiftAmount = 16; - } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) { - NewEntry.AddrShiftAmount = 18; - } else if ((NewEntry.Mask & 0xFF00) == 0x0300) { - NewEntry.AddrShiftAmount = 20; - } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) { - NewEntry.AddrShiftAmount = 22; - } else if ((NewEntry.Mask & 0xF000) == 0x3000) { - NewEntry.AddrShiftAmount = 24; - } else if ((NewEntry.Mask & 0xC000) == 0xC000) { - NewEntry.AddrShiftAmount = 26; - } else if ((NewEntry.Mask & 0x30000) == 0x30000) { - NewEntry.AddrShiftAmount = 28; - } else { - fatal("Invalid Mask Pattern Detected!\n"); - } - NewEntry.OffsetMask = ((1 << NewEntry.AddrShiftAmount) - 1); - - MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); - Config3Reg config3 = Config3; - PageGrainReg pageGrain = PageGrain; - int SP = 0; - if (bits(config3, config3.sp) == 1 && - bits(pageGrain, pageGrain.esp) == 1) { - SP = 1; - } - IndexReg index = Index; - Ptr->insertAt(NewEntry, Random, SP); - }}); - - 0x08: tlbp({{ - Config3Reg config3 = Config3; - PageGrainReg pageGrain = PageGrain; - EntryHiReg entryHi = EntryHi; - int TLB_Index; - Addr VPN; - if (pageGrain.esp == 1 && config3.sp ==1) { - VPN = EntryHi >> 11; - } else { - // Mask off lower 2 bits - VPN = ((EntryHi >> 11) & 0xFFFFFFFC); - } - TLB_Index = xc->tcBase()->getITBPtr()-> - probeEntry(VPN, entryHi.asid); - // Check TLB for entry matching EntryHi - if (TLB_Index != -1) { - Index = TLB_Index; - } else { - // else, set Index = 1 << 31 - Index = (1 << 31); - } - }}); - } - format CP0Unimpl { - 0x20: wait(); - } - default: CP0Unimpl::unknown(); + LLFlag = 0; + Status = status; + SRSCtl = srsCtl; + }}, IsReturn, IsSerializing, IsERET); + + 0x1F: deret({{ + DebugReg debug = Debug; + if (debug.dm == 1) { + debug.dm = 1; + debug.iexi = 0; + NPC = DEPC; + } else { + // Undefined; + } + Debug = debug; + }}, IsReturn, IsSerializing, IsERET); + } + format CP0TLB { + 0x01: tlbr({{ + MipsISA::PTE *PTEntry = + xc->tcBase()->getITBPtr()-> + getEntry(Index & 0x7FFFFFFF); + if (PTEntry == NULL) { + fatal("Invalid PTE Entry received on " + "a TLBR instruction\n"); + } + /* Setup PageMask */ + // If 1KB pages are not enabled, a read of PageMask + // must return 0b00 in bits 12, 11 + PageMask = (PTEntry->Mask << 11); + /* Setup EntryHi */ + EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); + /* Setup Entry Lo0 */ + EntryLo0 = ((PTEntry->PFN0 << 6) | + (PTEntry->C0 << 3) | + (PTEntry->D0 << 2) | + (PTEntry->V0 << 1) | + PTEntry->G); + /* Setup Entry Lo1 */ + EntryLo1 = ((PTEntry->PFN1 << 6) | + (PTEntry->C1 << 3) | + (PTEntry->D1 << 2) | + (PTEntry->V1 << 1) | + PTEntry->G); + }}); // Need to hook up to TLB + + 0x02: tlbwi({{ + //Create PTE + MipsISA::PTE newEntry; + //Write PTE + newEntry.Mask = (Addr)(PageMask >> 11); + newEntry.VPN = (Addr)(EntryHi >> 11); + /* PageGrain _ ESP Config3 _ SP */ + if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { + // If 1KB pages are *NOT* enabled, lowest bits of + // the mask are 0b11 for TLB writes + newEntry.Mask |= 0x3; + // Reset bits 0 and 1 if 1KB pages are not enabled + newEntry.VPN &= 0xFFFFFFFC; + } + newEntry.asid = (uint8_t)(EntryHi & 0xFF); + + newEntry.PFN0 = (Addr)(EntryLo0 >> 6); + newEntry.PFN1 = (Addr)(EntryLo1 >> 6); + newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); + newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); + newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); + newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); + newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); + newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); + newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); + /* Now, compute the AddrShiftAmount and OffsetMask - + TLB optimizations */ + /* Addr Shift Amount for 1KB or larger pages */ + if ((newEntry.Mask & 0xFFFF) == 3) { + newEntry.AddrShiftAmount = 12; + } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { + newEntry.AddrShiftAmount = 10; + } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { + newEntry.AddrShiftAmount = 14; + } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { + newEntry.AddrShiftAmount = 16; + } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { + newEntry.AddrShiftAmount = 18; + } else if ((newEntry.Mask & 0xFF00) == 0x0300) { + newEntry.AddrShiftAmount = 20; + } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { + newEntry.AddrShiftAmount = 22; + } else if ((newEntry.Mask & 0xF000) == 0x3000) { + newEntry.AddrShiftAmount = 24; + } else if ((newEntry.Mask & 0xC000) == 0xC000) { + newEntry.AddrShiftAmount = 26; + } else if ((newEntry.Mask & 0x30000) == 0x30000) { + newEntry.AddrShiftAmount = 28; + } else { + fatal("Invalid Mask Pattern Detected!\n"); + } + newEntry.OffsetMask = + (1 << newEntry.AddrShiftAmount) - 1; + + MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); + Config3Reg config3 = Config3; + PageGrainReg pageGrain = PageGrain; + int SP = 0; + if (bits(config3, config3.sp) == 1 && + bits(pageGrain, pageGrain.esp) == 1) { + SP = 1; + } + IndexReg index = Index; + Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); + }}); + 0x06: tlbwr({{ + //Create PTE + MipsISA::PTE newEntry; + //Write PTE + newEntry.Mask = (Addr)(PageMask >> 11); + newEntry.VPN = (Addr)(EntryHi >> 11); + /* PageGrain _ ESP Config3 _ SP */ + if (bits(PageGrain, 28) == 0 || + bits(Config3, 4) == 0) { + // If 1KB pages are *NOT* enabled, lowest bits of + // the mask are 0b11 for TLB writes + newEntry.Mask |= 0x3; + // Reset bits 0 and 1 if 1KB pages are not enabled + newEntry.VPN &= 0xFFFFFFFC; + } + newEntry.asid = (uint8_t)(EntryHi & 0xFF); + + newEntry.PFN0 = (Addr)(EntryLo0 >> 6); + newEntry.PFN1 = (Addr)(EntryLo1 >> 6); + newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); + newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); + newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); + newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); + newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); + newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); + newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); + /* Now, compute the AddrShiftAmount and OffsetMask - + TLB optimizations */ + /* Addr Shift Amount for 1KB or larger pages */ + if ((newEntry.Mask & 0xFFFF) == 3){ + newEntry.AddrShiftAmount = 12; + } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { + newEntry.AddrShiftAmount = 10; + } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { + newEntry.AddrShiftAmount = 14; + } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { + newEntry.AddrShiftAmount = 16; + } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { + newEntry.AddrShiftAmount = 18; + } else if ((newEntry.Mask & 0xFF00) == 0x0300) { + newEntry.AddrShiftAmount = 20; + } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { + newEntry.AddrShiftAmount = 22; + } else if ((newEntry.Mask & 0xF000) == 0x3000) { + newEntry.AddrShiftAmount = 24; + } else if ((newEntry.Mask & 0xC000) == 0xC000) { + newEntry.AddrShiftAmount = 26; + } else if ((newEntry.Mask & 0x30000) == 0x30000) { + newEntry.AddrShiftAmount = 28; + } else { + fatal("Invalid Mask Pattern Detected!\n"); + } + newEntry.OffsetMask = + (1 << newEntry.AddrShiftAmount) - 1; + + MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); + Config3Reg config3 = Config3; + PageGrainReg pageGrain = PageGrain; + int SP = 0; + if (bits(config3, config3.sp) == 1 && + bits(pageGrain, pageGrain.esp) == 1) { + SP = 1; + } + IndexReg index = Index; + Ptr->insertAt(newEntry, Random, SP); + }}); + 0x08: tlbp({{ + Config3Reg config3 = Config3; + PageGrainReg pageGrain = PageGrain; + EntryHiReg entryHi = EntryHi; + int tlbIndex; + Addr vpn; + if (pageGrain.esp == 1 && config3.sp ==1) { + vpn = EntryHi >> 11; + } else { + // Mask off lower 2 bits + vpn = ((EntryHi >> 11) & 0xFFFFFFFC); + } + tlbIndex = xc->tcBase()->getITBPtr()-> + probeEntry(vpn, entryHi.asid); + // Check TLB for entry matching EntryHi + if (tlbIndex != -1) { + Index = tlbIndex; + } else { + // else, set Index = 1 << 31 + Index = (1 << 31); + } + }}); + } + format CP0Unimpl { + 0x20: wait(); + } + default: CP0Unimpl::unknown(); } } //Table A-13 MIPS32 COP1 Encoding of rs Field 0x1: decode RS_MSB { - 0x0: decode RS_HI { 0x0: decode RS_LO { format CP1Control { 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 0x2: cfc1({{ - switch (FS) - { + switch (FS) { case 0: Rt = FIR; break; case 25: - Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; + Rt = (FCSR & 0xFE000000) >> 24 | + (FCSR & 0x00800000) >> 23; break; case 26: - Rt = 0 | (FCSR & 0x0003F07C); + Rt = (FCSR & 0x0003F07C); break; case 28: - Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); + Rt = (FCSR & 0x00000F80) | + (FCSR & 0x01000000) >> 21 | + (FCSR & 0x00000003); break; case 31: Rt = FCSR; @@ -907,46 +949,43 @@ decode OPCODE_HI default Unknown::unknown() { default: warn("FP Control Value (%d) Not Valid"); } - // warn("FCSR: %x, FS: %d, FIR: %x, Rt: %x\n",FCSR, FS, FIR, Rt); }}); - 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); + 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>; }}); - 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); + 0x4: mtc1({{ Fs.uw = Rt.uw; }}); 0x6: ctc1({{ - switch (FS) - { + switch (FS) { case 25: - FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 - | (FCSR & 0x01000000) // bit 24 - | (FCSR & 0x004FFFFF);// bit 22...0 + FCSR = (Rt.uw<7:1> << 25) | // move 31-25 + (FCSR & 0x01000000) | // bit 24 + (FCSR & 0x004FFFFF); // bit 22-0 break; - case 26: - FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 - | Rt.uw<17:12> << 12 // bit 17...12 - | (FCSR & 0x00000F80) << 7// bit 11...7 - | Rt.uw<6:2> << 2 // bit 6...2 - | (FCSR & 0x00000002); // bit 1...0 + FCSR = (FCSR & 0xFFFC0000) | // move 31-18 + Rt.uw<17:12> << 12 | // bit 17-12 + (FCSR & 0x00000F80) << 7 | // bit 11-7 + Rt.uw<6:2> << 2 | // bit 6-2 + (FCSR & 0x00000002); // bit 1-0 break; - case 28: - FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 - | Rt.uw<2:2> << 24 // bit 24 - | (FCSR & 0x00FFF000) << 23// bit 23...12 - | Rt.uw<11:7> << 7 // bit 24 - | (FCSR & 0x000007E) - | Rt.uw<1:0>;// bit 22...0 + FCSR = (FCSR & 0xFE000000) | // move 31-25 + Rt.uw<2:2> << 24 | // bit 24 + (FCSR & 0x00FFF000) << 23 | // bit 23-12 + Rt.uw<11:7> << 7 | // bit 24 + (FCSR & 0x000007E) | + Rt.uw<1:0>; // bit 22-0 break; - case 31: - FCSR = Rt.uw; + FCSR = Rt.uw; break; default: - panic("FP Control Value (%d) Not Available. Ignoring Access to" - "Floating Control Status Register", FS); + panic("FP Control Value (%d) " + "Not Available. Ignoring Access " + "to Floating Control Status " + "Register", FS); } }}); @@ -961,80 +1000,86 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: dmfc1(); 0x5: dmtc1(); } - } - - 0x1: - decode RS_LO { - 0x0: - decode ND { - format Branch { - 0x0: decode TF { - 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; - }}); - 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; - }}); - } - 0x1: decode TF { - 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; - }}, Likely); - 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; - }}, Likely); - } - } - } - format CP1Unimpl { - 0x1: bc1any2(); - 0x2: bc1any4(); - default: unknown(); - } - } + } + + 0x1: decode RS_LO { + 0x0: decode ND { + format Branch { + 0x0: decode TF { + 0x0: bc1f({{ + cond = getCondCode(FCSR, BRANCH_CC) == 0; + }}); + 0x1: bc1t({{ + cond = getCondCode(FCSR, BRANCH_CC) == 1; + }}); + } + 0x1: decode TF { + 0x0: bc1fl({{ + cond = getCondCode(FCSR, BRANCH_CC) == 0; + }}, Likely); + 0x1: bc1tl({{ + cond = getCondCode(FCSR, BRANCH_CC) == 1; + }}, Likely); + } + } + } + format CP1Unimpl { + 0x1: bc1any2(); + 0x2: bc1any4(); + default: unknown(); + } + } } 0x1: decode RS_HI { 0x2: decode RS_LO { - //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S - //(( single-precision floating point)) + //Table A-14 MIPS32 COP1 Encoding of Function Field When + //rs=S (( single-precision floating point)) 0x0: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format FloatOp { - 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); - 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); - 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); - 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); - 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); - 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); - 0x7: neg_s({{ Fd.sf = -Fs.sf;}}); + 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf; }}); + 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf; }}); + 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf; }}); + 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf; }}); + 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf); }}); + 0x5: abs_s({{ Fd.sf = fabs(Fs.sf); }}); + 0x7: neg_s({{ Fd.sf = -Fs.sf; }}); } - - 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}}); + 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf; }}); } - 0x1: decode FUNCTION_LO { format FloatConvertOp { - 0x0: round_l_s({{ val = Fs.sf; }}, ToLong, - Round); - 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong, - Trunc); - 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong, - Ceil); - 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong, - Floor); - 0x4: round_w_s({{ val = Fs.sf; }}, ToWord, - Round); - 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord, - Trunc); - 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord, - Ceil); - 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord, - Floor); + 0x0: round_l_s({{ val = Fs.sf; }}, + ToLong, Round); + 0x1: trunc_l_s({{ val = Fs.sf; }}, + ToLong, Trunc); + 0x2: ceil_l_s({{ val = Fs.sf;}}, + ToLong, Ceil); + 0x3: floor_l_s({{ val = Fs.sf; }}, + ToLong, Floor); + 0x4: round_w_s({{ val = Fs.sf; }}, + ToWord, Round); + 0x5: trunc_w_s({{ val = Fs.sf; }}, + ToWord, Trunc); + 0x6: ceil_w_s({{ val = Fs.sf; }}, + ToWord, Ceil); + 0x7: floor_w_s({{ val = Fs.sf; }}, + ToWord, Floor); } } 0x2: decode FUNCTION_LO { 0x1: decode MOVCF { format BasicOp { - 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }}); - 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }}); + 0x0: movf_s({{ + Fd = (getCondCode(FCSR,CC) == 0) ? + Fs : Fd; + }}); + 0x1: movt_s({{ + Fd = (getCondCode(FCSR,CC) == 1) ? + Fs : Fd; + }}); } } @@ -1045,10 +1090,10 @@ decode OPCODE_HI default Unknown::unknown() { format FloatOp { 0x5: recip_s({{ Fd = 1 / Fs; }}); - 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); + 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); } format CP1Unimpl { - default: unknown(); + default: unknown(); } } 0x3: CP1Unimpl::unknown(); @@ -1061,21 +1106,21 @@ decode OPCODE_HI default Unknown::unknown() { } 0x6: FloatOp::cvt_ps_s({{ - Fd.ud = (uint64_t) Fs.uw << 32 | - (uint64_t) Ft.uw; - }}); + Fd.ud = (uint64_t) Fs.uw << 32 | + (uint64_t) Ft.uw; + }}); format CP1Unimpl { - default: unknown(); + default: unknown(); } } 0x5: CP1Unimpl::unknown(); 0x6: decode FUNCTION_LO { format FloatCompareOp { - 0x0: c_f_s({{ cond = 0; }}, SinglePrecision, - UnorderedFalse); - 0x1: c_un_s({{ cond = 0; }}, SinglePrecision, - UnorderedTrue); + 0x0: c_f_s({{ cond = 0; }}, + SinglePrecision, UnorderedFalse); + 0x1: c_un_s({{ cond = 0; }}, + SinglePrecision, UnorderedTrue); 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, UnorderedFalse); 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, @@ -1097,7 +1142,7 @@ decode OPCODE_HI default Unknown::unknown() { UnorderedFalse, QnanException); 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, UnorderedTrue, QnanException); - 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}}, + 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf); }}, UnorderedFalse, QnanException); 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, UnorderedTrue, QnanException); @@ -1113,7 +1158,8 @@ decode OPCODE_HI default Unknown::unknown() { } } - //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D + //Table A-15 MIPS32 COP1 Encoding of Function Field When + //rs=D 0x1: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format FloatOp { @@ -1121,58 +1167,63 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); - 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); - 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); - 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); + 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); + 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); + 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); } - - 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); + 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); } 0x1: decode FUNCTION_LO { format FloatConvertOp { - 0x0: round_l_d({{ val = Fs.df; }}, ToLong, - Round); - 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong, - Trunc); - 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong, - Ceil); - 0x3: floor_l_d({{ val = Fs.df; }}, ToLong, - Floor); - 0x4: round_w_d({{ val = Fs.df; }}, ToWord, - Round); - 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord, - Trunc); - 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord, - Ceil); - 0x7: floor_w_d({{ val = Fs.df; }}, ToWord, - Floor); + 0x0: round_l_d({{ val = Fs.df; }}, + ToLong, Round); + 0x1: trunc_l_d({{ val = Fs.df; }}, + ToLong, Trunc); + 0x2: ceil_l_d({{ val = Fs.df; }}, + ToLong, Ceil); + 0x3: floor_l_d({{ val = Fs.df; }}, + ToLong, Floor); + 0x4: round_w_d({{ val = Fs.df; }}, + ToWord, Round); + 0x5: trunc_w_d({{ val = Fs.df; }}, + ToWord, Trunc); + 0x6: ceil_w_d({{ val = Fs.df; }}, + ToWord, Ceil); + 0x7: floor_w_d({{ val = Fs.df; }}, + ToWord, Floor); } } 0x2: decode FUNCTION_LO { 0x1: decode MOVCF { format BasicOp { - 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ? + 0x0: movf_d({{ + Fd.df = (getCondCode(FCSR,CC) == 0) ? Fs.df : Fd.df; - }}); - 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ? + }}); + 0x1: movt_d({{ + Fd.df = (getCondCode(FCSR,CC) == 1) ? Fs.df : Fd.df; - }}); + }}); } } format BasicOp { - 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }}); - 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }}); + 0x2: movz_d({{ + Fd.df = (Rt == 0) ? Fs.df : Fd.df; + }}); + 0x3: movn_d({{ + Fd.df = (Rt != 0) ? Fs.df : Fd.df; + }}); } format FloatOp { - 0x5: recip_d({{ Fd.df = 1 / Fs.df }}); - 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); + 0x5: recip_d({{ Fd.df = 1 / Fs.df; }}); + 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df); }}); } format CP1Unimpl { - default: unknown(); + default: unknown(); } } @@ -1182,15 +1233,15 @@ decode OPCODE_HI default Unknown::unknown() { 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); } - default: CP1Unimpl::unknown(); + default: CP1Unimpl::unknown(); } 0x6: decode FUNCTION_LO { format FloatCompareOp { - 0x0: c_f_d({{ cond = 0; }}, DoublePrecision, - UnorderedFalse); - 0x1: c_un_d({{ cond = 0; }}, DoublePrecision, - UnorderedTrue); + 0x0: c_f_d({{ cond = 0; }}, + DoublePrecision, UnorderedFalse); + 0x1: c_un_d({{ cond = 0; }}, + DoublePrecision, UnorderedTrue); 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, UnorderedFalse); 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, @@ -1226,37 +1277,40 @@ decode OPCODE_HI default Unknown::unknown() { UnorderedTrue, QnanException); } } - default: CP1Unimpl::unknown(); + default: CP1Unimpl::unknown(); } 0x2: CP1Unimpl::unknown(); 0x3: CP1Unimpl::unknown(); 0x7: CP1Unimpl::unknown(); - //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W + //Table A-16 MIPS32 COP1 Encoding of Function + //Field When rs=W 0x4: decode FUNCTION { format FloatConvertOp { 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 0x26: CP1Unimpl::cvt_ps_w(); } - default: CP1Unimpl::unknown(); + default: CP1Unimpl::unknown(); } - //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 - //Note: "1. Format type L is legal only if 64-bit floating point operations - //are enabled." + //Table A-16 MIPS32 COP1 Encoding of Function Field + //When rs=L1 + //Note: "1. Format type L is legal only if 64-bit + //floating point operations are enabled." 0x5: decode FUNCTION_HI { format FloatConvertOp { 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 0x26: CP1Unimpl::cvt_ps_l(); } - default: CP1Unimpl::unknown(); + default: CP1Unimpl::unknown(); } - //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 - //Note: "1. Format type PS is legal only if 64-bit floating point operations - //are enabled. " + //Table A-17 MIPS64 COP1 Encoding of Function Field + //When rs=PS1 + //Note: "1. Format type PS is legal only if 64-bit + //floating point operations are enabled. " 0x6: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format Float64Op { @@ -1284,7 +1338,7 @@ decode OPCODE_HI default Unknown::unknown() { Fd1.sf = -(Fs1.sf); Fd2.sf = -(Fs2.sf); }}); - default: CP1Unimpl::unknown(); + default: CP1Unimpl::unknown(); } } 0x1: CP1Unimpl::unknown(); @@ -1320,8 +1374,7 @@ decode OPCODE_HI default Unknown::unknown() { Fs2 : Fd2; }}); } - default: CP1Unimpl::unknown(); - + default: CP1Unimpl::unknown(); } 0x3: CP1Unimpl::unknown(); 0x4: decode FUNCTION_LO { @@ -1331,20 +1384,19 @@ decode OPCODE_HI default Unknown::unknown() { 0x5: decode FUNCTION_LO { 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); - format Float64Op { - 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | - Ft1.uw; - }}); - 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | - Ft2.uw; - }}); - 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | - Ft1.uw; - }}); - 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | - Ft2.uw; - }}); + 0x4: pll({{ + Fd.ud = (uint64_t)Fs1.uw << 32 | Ft1.uw; + }}); + 0x5: plu({{ + Fd.ud = (uint64_t)Fs1.uw << 32 | Ft2.uw; + }}); + 0x6: pul({{ + Fd.ud = (uint64_t)Fs2.uw << 32 | Ft1.uw; + }}); + 0x7: puu({{ + Fd.ud = (uint64_t)Fs2.uw << 32 | Ft2.uw; + }}); } default: CP1Unimpl::unknown(); } @@ -1405,7 +1457,7 @@ decode OPCODE_HI default Unknown::unknown() { } } } - default: CP1Unimpl::unknown(); + default: CP1Unimpl::unknown(); } } @@ -1420,28 +1472,27 @@ decode OPCODE_HI default Unknown::unknown() { 0x4: mtc2(); 0x6: ctc2(); 0x7: mftc2(); - default: unknown(); + default: unknown(); } 0x1: decode ND { 0x0: decode TF { 0x0: bc2f(); 0x1: bc2t(); - default: unknown(); + default: unknown(); } 0x1: decode TF { 0x0: bc2fl(); 0x1: bc2tl(); - default: unknown(); + default: unknown(); } - default: unknown(); + default: unknown(); - } - default: unknown(); - - } - default: unknown(); + } + default: unknown(); + } + default: unknown(); } } @@ -1451,39 +1502,37 @@ decode OPCODE_HI default Unknown::unknown() { 0x3: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { format LoadIndexedMemory { - 0x0: lwxc1({{ Fd.uw = Mem.uw;}}); - 0x1: ldxc1({{ Fd.ud = Mem.ud;}}); - 0x5: luxc1({{ Fd.ud = Mem.ud;}}, + 0x0: lwxc1({{ Fd.uw = Mem.uw; }}); + 0x1: ldxc1({{ Fd.ud = Mem.ud; }}); + 0x5: luxc1({{ Fd.ud = Mem.ud; }}, {{ EA = (Rs + Rt) & ~7; }}); } } 0x1: decode FUNCTION_LO { format StoreIndexedMemory { - 0x0: swxc1({{ Mem.uw = Fs.uw;}}); - 0x1: sdxc1({{ Mem.ud = Fs.ud;}}); - 0x5: suxc1({{ Mem.ud = Fs.ud;}}, + 0x0: swxc1({{ Mem.uw = Fs.uw; }}); + 0x1: sdxc1({{ Mem.ud = Fs.ud; }}); + 0x5: suxc1({{ Mem.ud = Fs.ud; }}, {{ EA = (Rs + Rt) & ~7; }}); } - 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); } 0x3: decode FUNCTION_LO { - 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) { - Fd.ud = Fs.ud; - } else if (Rs<2:0> == 4) { - #if BYTE_ORDER == BIG_ENDIAN - Fd.ud = Fs.ud<31:0> << 32 | - Ft.ud<63:32>; - #elif BYTE_ORDER == LITTLE_ENDIAN - Fd.ud = Ft.ud<31:0> << 32 | - Fs.ud<63:32>; - #endif - } else { - Fd.ud = Fd.ud; - } - }}); + 0x6: Float64Op::alnv_ps({{ + if (Rs<2:0> == 0) { + Fd.ud = Fs.ud; + } else if (Rs<2:0> == 4) { +#if BYTE_ORDER == BIG_ENDIAN + Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>; +#elif BYTE_ORDER == LITTLE_ENDIAN + Fd.ud = Ft.ud<31:0> << 32 | Fs.ud<63:32>; +#endif + } else { + Fd.ud = Fd.ud; + } + }}); } format FloatAccOp { @@ -1522,7 +1571,6 @@ decode OPCODE_HI default Unknown::unknown() { Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); }}); } - } } @@ -1538,38 +1586,53 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 0x4: decode FUNCTION_HI { 0x0: decode FUNCTION_LO { - 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; - Rd.sw = temp1<31:0>; - }}, IntMultOp); + 0x2: IntOp::mul({{ + int64_t temp1 = Rs.sd * Rt.sd; + Rd.sw = temp1<31:0>; + }}, IntMultOp); format HiLoRdSelValOp { - 0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }}, IntMultOp); - 0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }}, IntMultOp); - 0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }}, IntMultOp); - 0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }}, IntMultOp); + 0x0: madd({{ + val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + + (Rs.sd * Rt.sd); + }}, IntMultOp); + 0x1: maddu({{ + val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + + (Rs.ud * Rt.ud); + }}, IntMultOp); + 0x4: msub({{ + val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - + (Rs.sd * Rt.sd); + }}, IntMultOp); + 0x5: msubu({{ + val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - + (Rs.ud * Rt.ud); + }}, IntMultOp); } } 0x4: decode FUNCTION_LO { format BasicOp { - 0x0: clz({{ int cnt = 32; - for (int idx = 31; idx >= 0; idx--) { - if( Rs<idx:idx> == 1) { - cnt = 31 - idx; - break; - } - } - Rd.uw = cnt; - }}); - 0x1: clo({{ int cnt = 32; - for (int idx = 31; idx >= 0; idx--) { - if( Rs<idx:idx> == 0) { - cnt = 31 - idx; - break; - } - } - Rd.uw = cnt; - }}); + 0x0: clz({{ + int cnt = 32; + for (int idx = 31; idx >= 0; idx--) { + if (Rs<idx:idx> == 1) { + cnt = 31 - idx; + break; + } + } + Rd.uw = cnt; + }}); + 0x1: clo({{ + int cnt = 32; + for (int idx = 31; idx >= 0; idx--) { + if (Rs<idx:idx> == 0) { + cnt = 31 - idx; + break; + } + } + Rd.uw = cnt; + }}); } } @@ -1584,19 +1647,23 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode FUNCTION_LO { format BasicOp { 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); - 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | - bits(Rs.uw, MSB-LSB, 0) << LSB | - bits(Rt.uw, LSB-1, 0); - }}); + 0x4: ins({{ + Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | + bits(Rs.uw, MSB-LSB, 0) << LSB | + bits(Rt.uw, LSB-1, 0); + }}); } } 0x1: decode FUNCTION_LO { format MT_Control { - 0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }}, - UserMode); - 0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }}, - UserMode); + 0x0: fork({{ + forkThread(xc->tcBase(), fault, RD, Rs, Rt); + }}, UserMode); + 0x1: yield({{ + Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, + YQMask); + }}, UserMode); } //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) @@ -1609,267 +1676,451 @@ decode OPCODE_HI default Unknown::unknown() { } } } - 0x4: DspIntOp::insv({{ int pos = dspctl<5:0>; - int size = dspctl<12:7>-1; - Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }}); + 0x4: DspIntOp::insv({{ + int pos = dspctl<5:0>; + int size = dspctl<12:7> - 1; + Rt.uw = insertBits(Rt.uw, pos+size, + pos, Rs.uw<size:0>); + }}); } 0x2: decode FUNCTION_LO { - //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL) + //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field + //(DSP ASE MANUAL) 0x0: decode OP_HI { 0x0: decode OP_LO { format DspIntOp { - 0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, - NOSATURATE, UNSIGNED, &dspctl ); }}); - 0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, - NOSATURATE, UNSIGNED, &dspctl ); }}); - 0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB, - SATURATE, UNSIGNED, &dspctl ); }}); - 0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB, - SATURATE, UNSIGNED, &dspctl ); }}); - 0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, - MODE_L, &dspctl ); }}, IntMultOp); - 0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw, - MODE_R, &dspctl ); }}, IntMultOp); + 0x0: addu_qb({{ + Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, + NOSATURATE, UNSIGNED, &dspctl); + }}); + 0x1: subu_qb({{ + Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, + NOSATURATE, UNSIGNED, &dspctl); + }}); + 0x4: addu_s_qb({{ + Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_QB, + SATURATE, UNSIGNED, &dspctl); + }}); + 0x5: subu_s_qb({{ + Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_QB, + SATURATE, UNSIGNED, &dspctl); + }}); + 0x6: muleu_s_ph_qbl({{ + Rd.uw = dspMuleu(Rs.uw, Rt.uw, + MODE_L, &dspctl); + }}, IntMultOp); + 0x7: muleu_s_ph_qbr({{ + Rd.uw = dspMuleu(Rs.uw, Rt.uw, + MODE_R, &dspctl); + }}, IntMultOp); } } 0x1: decode OP_LO { format DspIntOp { - 0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, - NOSATURATE, UNSIGNED, &dspctl ); }}); - 0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, - NOSATURATE, UNSIGNED, &dspctl ); }}); - 0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, - NOSATURATE, SIGNED, &dspctl ); }}); - 0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, - NOSATURATE, SIGNED, &dspctl ); }}); - 0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, - SATURATE, UNSIGNED, &dspctl ); }}); - 0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, - SATURATE, UNSIGNED, &dspctl ); }}); - 0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH, - SATURATE, SIGNED, &dspctl ); }}); - 0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH, - SATURATE, SIGNED, &dspctl ); }}); + 0x0: addu_ph({{ + Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, + NOSATURATE, UNSIGNED, &dspctl); + }}); + 0x1: subu_ph({{ + Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, + NOSATURATE, UNSIGNED, &dspctl); + }}); + 0x2: addq_ph({{ + Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, + NOSATURATE, SIGNED, &dspctl); + }}); + 0x3: subq_ph({{ + Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, + NOSATURATE, SIGNED, &dspctl); + }}); + 0x4: addu_s_ph({{ + Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, + SATURATE, UNSIGNED, &dspctl); + }}); + 0x5: subu_s_ph({{ + Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, + SATURATE, UNSIGNED, &dspctl); + }}); + 0x6: addq_s_ph({{ + Rd.uw = dspAdd(Rs.uw, Rt.uw, SIMD_FMT_PH, + SATURATE, SIGNED, &dspctl); + }}); + 0x7: subq_s_ph({{ + Rd.uw = dspSub(Rs.uw, Rt.uw, SIMD_FMT_PH, + SATURATE, SIGNED, &dspctl); + }}); } } 0x2: decode OP_LO { format DspIntOp { - 0x0: addsc({{ int64_t dresult; - dresult = Rs.ud + Rt.ud; - Rd.sw = dresult<31:0>; - dspctl = insertBits( dspctl, 13, 13, - dresult<32:32> ); }}); - 0x1: addwc({{ int64_t dresult; - dresult = Rs.sd + Rt.sd + dspctl<13:13>; - Rd.sw = dresult<31:0>; - if( dresult<32:32> != dresult<31:31> ) - dspctl = insertBits( dspctl, 20, 20, 1 ); }}); - 0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }}); - 0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + - Rs.uw<15:8> + Rs.uw<7:0>; }}); - 0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W, - SATURATE, SIGNED, &dspctl ); }}); - 0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W, - SATURATE, SIGNED, &dspctl ); }}); + 0x0: addsc({{ + int64_t dresult; + dresult = Rs.ud + Rt.ud; + Rd.sw = dresult<31:0>; + dspctl = insertBits(dspctl, 13, 13, + dresult<32:32>); + }}); + 0x1: addwc({{ + int64_t dresult; + dresult = Rs.sd + Rt.sd + dspctl<13:13>; + Rd.sw = dresult<31:0>; + if (dresult<32:32> != dresult<31:31>) + dspctl = insertBits(dspctl, 20, 20, 1); + }}); + 0x2: modsub({{ + Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : + Rs.sw - Rt.sw<7:0>; + }}); + 0x4: raddu_w_qb({{ + Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> + + Rs.uw<15:8> + Rs.uw<7:0>; + }}); + 0x6: addq_s_w({{ + Rd.sw = dspAdd(Rs.sw, Rt.sw, SIMD_FMT_W, + SATURATE, SIGNED, &dspctl); + }}); + 0x7: subq_s_w({{ + Rd.sw = dspSub(Rs.sw, Rt.sw, SIMD_FMT_W, + SATURATE, SIGNED, &dspctl); + }}); } } 0x3: decode OP_LO { format DspIntOp { - 0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, - MODE_L, &dspctl ); }}, IntMultOp); - 0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw, - MODE_R, &dspctl ); }}, IntMultOp); - 0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, - SATURATE, NOROUND, &dspctl ); }}, IntMultOp); - 0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH, - SATURATE, ROUND, &dspctl ); }}, IntMultOp); + 0x4: muleq_s_w_phl({{ + Rd.sw = dspMuleq(Rs.sw, Rt.sw, + MODE_L, &dspctl); + }}, IntMultOp); + 0x5: muleq_s_w_phr({{ + Rd.sw = dspMuleq(Rs.sw, Rt.sw, + MODE_R, &dspctl); + }}, IntMultOp); + 0x6: mulq_s_ph({{ + Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, + SATURATE, NOROUND, &dspctl); + }}, IntMultOp); + 0x7: mulq_rs_ph({{ + Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_PH, + SATURATE, ROUND, &dspctl); + }}, IntMultOp); } } } - //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL) + //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field + //(DSP ASE MANUAL) 0x1: decode OP_HI { 0x0: decode OP_LO { format DspIntOp { - 0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, - UNSIGNED, CMP_EQ, &dspctl ); }}); - 0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, - UNSIGNED, CMP_LT, &dspctl ); }}); - 0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB, - UNSIGNED, CMP_LE, &dspctl ); }}); - 0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw, - SIMD_FMT_QB, &dspctl ); }}); - 0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, - UNSIGNED, CMP_EQ ); }}); - 0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, - UNSIGNED, CMP_LT ); }}); - 0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB, - UNSIGNED, CMP_LE ); }}); + 0x0: cmpu_eq_qb({{ + dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_EQ, &dspctl); + }}); + 0x1: cmpu_lt_qb({{ + dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LT, &dspctl); + }}); + 0x2: cmpu_le_qb({{ + dspCmp(Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LE, &dspctl); + }}); + 0x3: pick_qb({{ + Rd.uw = dspPick(Rs.uw, Rt.uw, + SIMD_FMT_QB, &dspctl); + }}); + 0x4: cmpgu_eq_qb({{ + Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_EQ ); + }}); + 0x5: cmpgu_lt_qb({{ + Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LT); + }}); + 0x6: cmpgu_le_qb({{ + Rd.uw = dspCmpg(Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LE); + }}); } } 0x1: decode OP_LO { format DspIntOp { - 0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, - SIGNED, CMP_EQ, &dspctl ); }}); - 0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, - SIGNED, CMP_LT, &dspctl ); }}); - 0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH, - SIGNED, CMP_LE, &dspctl ); }}); - 0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw, - SIMD_FMT_PH, &dspctl ); }}); - 0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 | - Rs.uw<15:8> << 16 | - Rt.uw<31:24> << 8 | - Rt.uw<15:8>; }}); - 0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 | - Rs.uw<7:0> << 16 | - Rt.uw<23:16> << 8 | - Rt.uw<7:0>; }}); - 0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw, - SIMD_FMT_PH ); }}); - 0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }}); + 0x0: cmp_eq_ph({{ + dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, + SIGNED, CMP_EQ, &dspctl); + }}); + 0x1: cmp_lt_ph({{ + dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, + SIGNED, CMP_LT, &dspctl); + }}); + 0x2: cmp_le_ph({{ + dspCmp(Rs.uw, Rt.uw, SIMD_FMT_PH, + SIGNED, CMP_LE, &dspctl); + }}); + 0x3: pick_ph({{ + Rd.uw = dspPick(Rs.uw, Rt.uw, + SIMD_FMT_PH, &dspctl); + }}); + 0x4: precrq_qb_ph({{ + Rd.uw = Rs.uw<31:24> << 24 | + Rs.uw<15:8> << 16 | + Rt.uw<31:24> << 8 | + Rt.uw<15:8>; + }}); + 0x5: precr_qb_ph({{ + Rd.uw = Rs.uw<23:16> << 24 | + Rs.uw<7:0> << 16 | + Rt.uw<23:16> << 8 | + Rt.uw<7:0>; + }}); + 0x6: packrl_ph({{ + Rd.uw = dspPack(Rs.uw, Rt.uw, SIMD_FMT_PH); + }}); + 0x7: precrqu_s_qb_ph({{ + Rd.uw = dspPrecrqu(Rs.uw, Rt.uw, &dspctl); + }}); } } 0x2: decode OP_LO { format DspIntOp { - 0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }}); - 0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }}); + 0x4: precrq_ph_w({{ + Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; + }}); + 0x5: precrq_rs_ph_w({{ + Rd.uw = dspPrecrq(Rs.uw, Rt.uw, + SIMD_FMT_W, &dspctl); + }}); } } 0x3: decode OP_LO { format DspIntOp { - 0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, - UNSIGNED, CMP_EQ, &dspctl ); }}); - 0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, - UNSIGNED, CMP_LT, &dspctl ); }}); - 0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB, - UNSIGNED, CMP_LE, &dspctl ); }}); - 0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, - SIMD_FMT_W, NOROUND ); }}); - 0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD, - SIMD_FMT_W, ROUND ); }}); + 0x0: cmpgdu_eq_qb({{ + Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_EQ, &dspctl); + }}); + 0x1: cmpgdu_lt_qb({{ + Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LT, &dspctl); + }}); + 0x2: cmpgdu_le_qb({{ + Rd.uw = dspCmpgd(Rs.uw, Rt.uw, SIMD_FMT_QB, + UNSIGNED, CMP_LE, &dspctl); + }}); + 0x6: precr_sra_ph_w({{ + Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, + SIMD_FMT_W, NOROUND); + }}); + 0x7: precr_sra_r_ph_w({{ + Rt.uw = dspPrecrSra(Rt.uw, Rs.uw, RD, + SIMD_FMT_W, ROUND); + }}); } } } - //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL) + //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field + //(DSP ASE MANUAL) 0x2: decode OP_HI { 0x0: decode OP_LO { format DspIntOp { - 0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}}); - 0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 | - RS_RT<7:0> << 16 | - RS_RT<7:0> << 8 | - RS_RT<7:0>; }}); - 0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 | - Rt.uw<7:0> << 16 | - Rt.uw<7:0> << 8 | - Rt.uw<7:0>; }}); - 0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, - SIMD_FMT_PH, SIGNED, MODE_L ); }}); - 0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, - SIMD_FMT_PH, SIGNED, MODE_R ); }}); - 0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, - SIMD_FMT_PH, SIGNED, MODE_LA ); }}); - 0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, - SIMD_FMT_PH, SIGNED, MODE_RA ); }}); + 0x1: absq_s_qb({{ + Rd.sw = dspAbs(Rt.sw, SIMD_FMT_QB, &dspctl); + }}); + 0x2: repl_qb({{ + Rd.uw = RS_RT<7:0> << 24 | + RS_RT<7:0> << 16 | + RS_RT<7:0> << 8 | + RS_RT<7:0>; + }}); + 0x3: replv_qb({{ + Rd.sw = Rt.uw<7:0> << 24 | + Rt.uw<7:0> << 16 | + Rt.uw<7:0> << 8 | + Rt.uw<7:0>; + }}); + 0x4: precequ_ph_qbl({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, SIGNED, MODE_L); + }}); + 0x5: precequ_ph_qbr({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, SIGNED, MODE_R); + }}); + 0x6: precequ_ph_qbla({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, SIGNED, MODE_LA); + }}); + 0x7: precequ_ph_qbra({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, UNSIGNED, + SIMD_FMT_PH, SIGNED, MODE_RA); + }}); } } 0x1: decode OP_LO { format DspIntOp { - 0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }}); - 0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | - (sext<10>(RS_RT))<15:0>; }}); - 0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 | - Rt.uw<15:0>; }}); - 0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, - SIMD_FMT_W, SIGNED, MODE_L ); }}); - 0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED, - SIMD_FMT_W, SIGNED, MODE_R ); }}); + 0x1: absq_s_ph({{ + Rd.sw = dspAbs(Rt.sw, SIMD_FMT_PH, &dspctl); + }}); + 0x2: repl_ph({{ + Rd.uw = (sext<10>(RS_RT))<15:0> << 16 | + (sext<10>(RS_RT))<15:0>; + }}); + 0x3: replv_ph({{ + Rd.uw = Rt.uw<15:0> << 16 | + Rt.uw<15:0>; + }}); + 0x4: preceq_w_phl({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, + SIMD_FMT_W, SIGNED, MODE_L); + }}); + 0x5: preceq_w_phr({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_PH, SIGNED, + SIMD_FMT_W, SIGNED, MODE_R); + }}); } } 0x2: decode OP_LO { format DspIntOp { - 0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }}); + 0x1: absq_s_w({{ + Rd.sw = dspAbs(Rt.sw, SIMD_FMT_W, &dspctl); + }}); } } 0x3: decode OP_LO { - 0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }}); + 0x3: IntOp::bitrev({{ + Rd.uw = bitrev( Rt.uw<15:0> ); + }}); format DspIntOp { - 0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, - SIMD_FMT_PH, UNSIGNED, MODE_L ); }}); - 0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, - SIMD_FMT_PH, UNSIGNED, MODE_R ); }}); - 0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, - SIMD_FMT_PH, UNSIGNED, MODE_LA ); }}); - 0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED, - SIMD_FMT_PH, UNSIGNED, MODE_RA ); }}); + 0x4: preceu_ph_qbl({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, + UNSIGNED, SIMD_FMT_PH, + UNSIGNED, MODE_L); + }}); + 0x5: preceu_ph_qbr({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, + UNSIGNED, SIMD_FMT_PH, + UNSIGNED, MODE_R ); + }}); + 0x6: preceu_ph_qbla({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, + UNSIGNED, SIMD_FMT_PH, + UNSIGNED, MODE_LA ); + }}); + 0x7: preceu_ph_qbra({{ + Rd.uw = dspPrece(Rt.uw, SIMD_FMT_QB, + UNSIGNED, SIMD_FMT_PH, + UNSIGNED, MODE_RA); + }}); } } } - //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL) + //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field + //(DSP ASE MANUAL) 0x3: decode OP_HI { 0x0: decode OP_LO { format DspIntOp { - 0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB, - NOSATURATE, UNSIGNED, &dspctl ); }}); - 0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB, - UNSIGNED ); }}); - 0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB, - NOSATURATE, UNSIGNED, &dspctl ); }}); - 0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB, - UNSIGNED ); }}); - 0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, - NOROUND, SIGNED, &dspctl ); }}); - 0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB, - ROUND, SIGNED, &dspctl ); }}); - 0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, - NOROUND, SIGNED, &dspctl ); }}); - 0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB, - ROUND, SIGNED, &dspctl ); }}); + 0x0: shll_qb({{ + Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_QB, + NOSATURATE, UNSIGNED, &dspctl); + }}); + 0x1: shrl_qb({{ + Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_QB, + UNSIGNED); + }}); + 0x2: shllv_qb({{ + Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_QB, + NOSATURATE, UNSIGNED, &dspctl); + }}); + 0x3: shrlv_qb({{ + Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_QB, + UNSIGNED); + }}); + 0x4: shra_qb({{ + Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, + NOROUND, SIGNED, &dspctl); + }}); + 0x5: shra_r_qb({{ + Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_QB, + ROUND, SIGNED, &dspctl); + }}); + 0x6: shrav_qb({{ + Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, + NOROUND, SIGNED, &dspctl); + }}); + 0x7: shrav_r_qb({{ + Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_QB, + ROUND, SIGNED, &dspctl); + }}); } } 0x1: decode OP_LO { format DspIntOp { - 0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH, - NOSATURATE, SIGNED, &dspctl ); }}); - 0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, - NOROUND, SIGNED, &dspctl ); }}); - 0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, - NOSATURATE, SIGNED, &dspctl ); }}); - 0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, - NOROUND, SIGNED, &dspctl ); }}); - 0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH, - SATURATE, SIGNED, &dspctl ); }}); - 0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH, - ROUND, SIGNED, &dspctl ); }}); - 0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH, - SATURATE, SIGNED, &dspctl ); }}); - 0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH, - ROUND, SIGNED, &dspctl ); }}); + 0x0: shll_ph({{ + Rd.uw = dspShll(Rt.uw, RS, SIMD_FMT_PH, + NOSATURATE, SIGNED, &dspctl); + }}); + 0x1: shra_ph({{ + Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, + NOROUND, SIGNED, &dspctl); + }}); + 0x2: shllv_ph({{ + Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, + NOSATURATE, SIGNED, &dspctl); + }}); + 0x3: shrav_ph({{ + Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, + NOROUND, SIGNED, &dspctl); + }}); + 0x4: shll_s_ph({{ + Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_PH, + SATURATE, SIGNED, &dspctl); + }}); + 0x5: shra_r_ph({{ + Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_PH, + ROUND, SIGNED, &dspctl); + }}); + 0x6: shllv_s_ph({{ + Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_PH, + SATURATE, SIGNED, &dspctl); + }}); + 0x7: shrav_r_ph({{ + Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_PH, + ROUND, SIGNED, &dspctl); + }}); } } 0x2: decode OP_LO { format DspIntOp { - 0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W, - SATURATE, SIGNED, &dspctl ); }}); - 0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W, - ROUND, SIGNED, &dspctl ); }}); - 0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W, - SATURATE, SIGNED, &dspctl ); }}); - 0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W, - ROUND, SIGNED, &dspctl ); }}); + 0x4: shll_s_w({{ + Rd.sw = dspShll(Rt.sw, RS, SIMD_FMT_W, + SATURATE, SIGNED, &dspctl); + }}); + 0x5: shra_r_w({{ + Rd.sw = dspShra(Rt.sw, RS, SIMD_FMT_W, + ROUND, SIGNED, &dspctl); + }}); + 0x6: shllv_s_w({{ + Rd.sw = dspShll(Rt.sw, Rs.sw, SIMD_FMT_W, + SATURATE, SIGNED, &dspctl); + }}); + 0x7: shrav_r_w({{ + Rd.sw = dspShra(Rt.sw, Rs.sw, SIMD_FMT_W, + ROUND, SIGNED, &dspctl); + }}); } } 0x3: decode OP_LO { format DspIntOp { - 0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH, - UNSIGNED ); }}); - 0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH, - UNSIGNED ); }}); + 0x1: shrl_ph({{ + Rd.sw = dspShrl(Rt.sw, RS, SIMD_FMT_PH, + UNSIGNED); + }}); + 0x3: shrlv_ph({{ + Rd.sw = dspShrl(Rt.sw, Rs.sw, SIMD_FMT_PH, + UNSIGNED); + }}); } } } @@ -1877,51 +2128,83 @@ decode OPCODE_HI default Unknown::unknown() { 0x3: decode FUNCTION_LO { - //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual) + //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field + //(DSP ASE Rev2 Manual) 0x0: decode OP_HI { 0x0: decode OP_LO { format DspIntOp { - 0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, - NOROUND, UNSIGNED ); }}); - 0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, - NOROUND, UNSIGNED ); }}); - 0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB, - ROUND, UNSIGNED ); }}); - 0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB, - ROUND, UNSIGNED ); }}); + 0x0: adduh_qb({{ + Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, + NOROUND, UNSIGNED); + }}); + 0x1: subuh_qb({{ + Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, + NOROUND, UNSIGNED); + }}); + 0x2: adduh_r_qb({{ + Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_QB, + ROUND, UNSIGNED); + }}); + 0x3: subuh_r_qb({{ + Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_QB, + ROUND, UNSIGNED); + }}); } } 0x1: decode OP_LO { format DspIntOp { - 0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, - NOROUND, SIGNED ); }}); - 0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, - NOROUND, SIGNED ); }}); - 0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH, - ROUND, SIGNED ); }}); - 0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH, - ROUND, SIGNED ); }}); - 0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, - NOSATURATE, &dspctl ); }}, IntMultOp); - 0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH, - SATURATE, &dspctl ); }}, IntMultOp); - + 0x0: addqh_ph({{ + Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, + NOROUND, SIGNED); + }}); + 0x1: subqh_ph({{ + Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, + NOROUND, SIGNED); + }}); + 0x2: addqh_r_ph({{ + Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_PH, + ROUND, SIGNED); + }}); + 0x3: subqh_r_ph({{ + Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_PH, + ROUND, SIGNED); + }}); + 0x4: mul_ph({{ + Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, + NOSATURATE, &dspctl); + }}, IntMultOp); + 0x6: mul_s_ph({{ + Rd.sw = dspMul(Rs.sw, Rt.sw, SIMD_FMT_PH, + SATURATE, &dspctl); + }}, IntMultOp); } } 0x2: decode OP_LO { format DspIntOp { - 0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, - NOROUND, SIGNED ); }}); - 0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, - NOROUND, SIGNED ); }}); - 0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W, - ROUND, SIGNED ); }}); - 0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W, - ROUND, SIGNED ); }}); - 0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, - SATURATE, NOROUND, &dspctl ); }}, IntMultOp); - 0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W, - SATURATE, ROUND, &dspctl ); }}, IntMultOp); + 0x0: addqh_w({{ + Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, + NOROUND, SIGNED); + }}); + 0x1: subqh_w({{ + Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, + NOROUND, SIGNED); + }}); + 0x2: addqh_r_w({{ + Rd.uw = dspAddh(Rs.sw, Rt.sw, SIMD_FMT_W, + ROUND, SIGNED); + }}); + 0x3: subqh_r_w({{ + Rd.uw = dspSubh(Rs.sw, Rt.sw, SIMD_FMT_W, + ROUND, SIGNED); + }}); + 0x6: mulq_s_w({{ + Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, + SATURATE, NOROUND, &dspctl); + }}, IntMultOp); + 0x7: mulq_rs_w({{ + Rd.sw = dspMulq(Rs.sw, Rt.sw, SIMD_FMT_W, + SATURATE, ROUND, &dspctl); + }}, IntMultOp); } } } @@ -1930,10 +2213,11 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-10 MIPS32 BSHFL Encoding of sa Field 0x4: decode SA { format BasicOp { - 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | - Rt.uw<31:24> << 16 | - Rt.uw<7:0> << 8 | - Rt.uw<15:8>; + 0x02: wsbh({{ + Rd.uw = Rt.uw<23:16> << 24 | + Rt.uw<31:24> << 16 | + Rt.uw<7:0> << 8 | + Rt.uw<15:8>; }}); 0x10: seb({{ Rd.sw = Rt.sb; }}); 0x18: seh({{ Rd.sw = Rt.sh; }}); @@ -1942,66 +2226,132 @@ decode OPCODE_HI default Unknown::unknown() { 0x6: decode FUNCTION_LO { - //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL) + //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field + //(DSP ASE MANUAL) 0x0: decode OP_HI { 0x0: decode OP_LO { format DspHiLoOp { - 0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, - SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); - 0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, - SIMD_FMT_PH, SIGNED, MODE_L ); }}, IntMultOp); - 0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw, - ACDST, SIMD_FMT_PH ); }}, IntMultOp); - 0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, - SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); - 0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, - SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); - 0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, - SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }}, IntMultOp); - 0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw, - ACDST, SIMD_FMT_PH, &dspctl ); }}, IntMultOp); - 0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, - SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); + 0x0: dpa_w_ph({{ + dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_PH, SIGNED, MODE_L); + }}, IntMultOp); + 0x1: dps_w_ph({{ + dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_PH, SIGNED, MODE_L); + }}, IntMultOp); + 0x2: mulsa_w_ph({{ + dspac = dspMulsa(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH ); + }}, IntMultOp); + 0x3: dpau_h_qbl({{ + dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_QB, UNSIGNED, MODE_L); + }}, IntMultOp); + 0x4: dpaq_s_w_ph({{ + dspac = dspDpaq(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH, + SIMD_FMT_W, NOSATURATE, + MODE_L, &dspctl); + }}, IntMultOp); + 0x5: dpsq_s_w_ph({{ + dspac = dspDpsq(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH, + SIMD_FMT_W, NOSATURATE, + MODE_L, &dspctl); + }}, IntMultOp); + 0x6: mulsaq_s_w_ph({{ + dspac = dspMulsaq(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH, + &dspctl); + }}, IntMultOp); + 0x7: dpau_h_qbr({{ + dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_QB, UNSIGNED, MODE_R); + }}, IntMultOp); } } 0x1: decode OP_LO { format DspHiLoOp { - 0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST, - SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); - 0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, - SIMD_FMT_PH, SIGNED, MODE_X ); }}, IntMultOp); - 0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, - SIMD_FMT_QB, UNSIGNED, MODE_L ); }}, IntMultOp); - 0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, - SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); - 0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W, - SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }}, IntMultOp); - 0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST, - SIMD_FMT_QB, UNSIGNED, MODE_R ); }}, IntMultOp); + 0x0: dpax_w_ph({{ + dspac = dspDpa(dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_PH, SIGNED, MODE_X); + }}, IntMultOp); + 0x1: dpsx_w_ph({{ + dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_PH, SIGNED, MODE_X); + }}, IntMultOp); + 0x3: dpsu_h_qbl({{ + dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_QB, UNSIGNED, MODE_L); + }}, IntMultOp); + 0x4: dpaq_sa_l_w({{ + dspac = dspDpaq(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_W, + SIMD_FMT_L, SATURATE, + MODE_L, &dspctl); + }}, IntMultOp); + 0x5: dpsq_sa_l_w({{ + dspac = dspDpsq(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_W, + SIMD_FMT_L, SATURATE, + MODE_L, &dspctl); + }}, IntMultOp); + 0x7: dpsu_h_qbr({{ + dspac = dspDps(dspac, Rs.sw, Rt.sw, ACDST, + SIMD_FMT_QB, UNSIGNED, MODE_R); + }}, IntMultOp); } } 0x2: decode OP_LO { format DspHiLoOp { - 0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, - MODE_L, SATURATE, &dspctl ); }}, IntMultOp); - 0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, - MODE_R, SATURATE, &dspctl ); }}, IntMultOp); - 0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, - MODE_L, NOSATURATE, &dspctl ); }}, IntMultOp); - 0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH, - MODE_R, NOSATURATE, &dspctl ); }}, IntMultOp); + 0x0: maq_sa_w_phl({{ + dspac = dspMaq(dspac, Rs.uw, Rt.uw, + ACDST, SIMD_FMT_PH, + MODE_L, SATURATE, &dspctl); + }}, IntMultOp); + 0x2: maq_sa_w_phr({{ + dspac = dspMaq(dspac, Rs.uw, Rt.uw, + ACDST, SIMD_FMT_PH, + MODE_R, SATURATE, &dspctl); + }}, IntMultOp); + 0x4: maq_s_w_phl({{ + dspac = dspMaq(dspac, Rs.uw, Rt.uw, + ACDST, SIMD_FMT_PH, + MODE_L, NOSATURATE, &dspctl); + }}, IntMultOp); + 0x6: maq_s_w_phr({{ + dspac = dspMaq(dspac, Rs.uw, Rt.uw, + ACDST, SIMD_FMT_PH, + MODE_R, NOSATURATE, &dspctl); + }}, IntMultOp); } } 0x3: decode OP_LO { format DspHiLoOp { - 0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, - SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); - 0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, - SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }}, IntMultOp); - 0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, - SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); - 0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH, - SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }}, IntMultOp); + 0x0: dpaqx_s_w_ph({{ + dspac = dspDpaq(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH, + SIMD_FMT_W, NOSATURATE, + MODE_X, &dspctl); + }}, IntMultOp); + 0x1: dpsqx_s_w_ph({{ + dspac = dspDpsq(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH, + SIMD_FMT_W, NOSATURATE, + MODE_X, &dspctl); + }}, IntMultOp); + 0x2: dpaqx_sa_w_ph({{ + dspac = dspDpaq(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH, + SIMD_FMT_W, SATURATE, + MODE_X, &dspctl); + }}, IntMultOp); + 0x3: dpsqx_sa_w_ph({{ + dspac = dspDpsq(dspac, Rs.sw, Rt.sw, + ACDST, SIMD_FMT_PH, + SIMD_FMT_W, SATURATE, + MODE_X, &dspctl); + }}, IntMultOp); } } } @@ -2010,13 +2360,21 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: decode OP_HI { 0x0: decode OP_LO { format IntOp { - 0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }}); - 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw, RD - 1, 0) << (32 - RD)); }}); + 0x0: append({{ + Rt.uw = (Rt.uw << RD) | bits(Rs.uw, RD - 1, 0); + }}); + 0x1: prepend({{ + Rt.uw = (Rt.uw >> RD) | + (bits(Rs.uw, RD - 1, 0) << (32 - RD)); + }}); } } 0x2: decode OP_LO { format IntOp { - 0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }}); + 0x0: balign({{ + Rt.uw = (Rt.uw << (8 * BP)) | + (Rs.uw >> (8 * (4 - BP))); + }}); } } } @@ -2024,56 +2382,97 @@ decode OPCODE_HI default Unknown::unknown() { } 0x7: decode FUNCTION_LO { - //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL) + //Table 5-11 MIPS32 EXTR.W Encoding of the op Field + //(DSP ASE MANUAL) 0x0: decode OP_HI { 0x0: decode OP_LO { format DspHiLoOp { - 0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, - NOROUND, NOSATURATE, &dspctl ); }}); - 0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, - NOROUND, NOSATURATE, &dspctl ); }}); - 0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }}); - 0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }}); - 0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, - ROUND, NOSATURATE, &dspctl ); }}); - 0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, - ROUND, NOSATURATE, &dspctl ); }}); - 0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS, - ROUND, SATURATE, &dspctl ); }}); - 0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw, - ROUND, SATURATE, &dspctl ); }}); + 0x0: extr_w({{ + Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, + NOROUND, NOSATURATE, &dspctl); + }}); + 0x1: extrv_w({{ + Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, + NOROUND, NOSATURATE, &dspctl); + }}); + 0x2: extp({{ + Rt.uw = dspExtp(dspac, RS, &dspctl); + }}); + 0x3: extpv({{ + Rt.uw = dspExtp(dspac, Rs.uw, &dspctl); + }}); + 0x4: extr_r_w({{ + Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, + ROUND, NOSATURATE, &dspctl); + }}); + 0x5: extrv_r_w({{ + Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, + ROUND, NOSATURATE, &dspctl); + }}); + 0x6: extr_rs_w({{ + Rt.uw = dspExtr(dspac, SIMD_FMT_W, RS, + ROUND, SATURATE, &dspctl); + }}); + 0x7: extrv_rs_w({{ + Rt.uw = dspExtr(dspac, SIMD_FMT_W, Rs.uw, + ROUND, SATURATE, &dspctl); + }}); } } 0x1: decode OP_LO { format DspHiLoOp { - 0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }}); - 0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }}); - 0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS, - NOROUND, SATURATE, &dspctl ); }}); - 0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw, - NOROUND, SATURATE, &dspctl ); }}); + 0x2: extpdp({{ + Rt.uw = dspExtpd(dspac, RS, &dspctl); + }}); + 0x3: extpdpv({{ + Rt.uw = dspExtpd(dspac, Rs.uw, &dspctl); + }}); + 0x6: extr_s_h({{ + Rt.uw = dspExtr(dspac, SIMD_FMT_PH, RS, + NOROUND, SATURATE, &dspctl); + }}); + 0x7: extrv_s_h({{ + Rt.uw = dspExtr(dspac, SIMD_FMT_PH, Rs.uw, + NOROUND, SATURATE, &dspctl); + }}); } } 0x2: decode OP_LO { format DspIntOp { - 0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }}); - 0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }}); + 0x2: rddsp({{ + Rd.uw = readDSPControl(&dspctl, RDDSPMASK); + }}); + 0x3: wrdsp({{ + writeDSPControl(&dspctl, Rs.uw, WRDSPMASK); + }}); } } 0x3: decode OP_LO { format DspHiLoOp { - 0x2: shilo({{ if( sext<6>(HILOSA) < 0 ) - dspac = (uint64_t)dspac << -sext<6>(HILOSA); - else - dspac = (uint64_t)dspac >> sext<6>(HILOSA); }}); - 0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 ) - dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>); - else - dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }}); - 0x7: mthlip({{ dspac = dspac << 32; - dspac |= Rs.uw; - dspctl = insertBits( dspctl, 5, 0, - dspctl<5:0>+32 ); }}); + 0x2: shilo({{ + if (sext<6>(HILOSA) < 0) { + dspac = (uint64_t)dspac << + -sext<6>(HILOSA); + } else { + dspac = (uint64_t)dspac >> + sext<6>(HILOSA); + } + }}); + 0x3: shilov({{ + if (sext<6>(Rs.sw<5:0>) < 0) { + dspac = (uint64_t)dspac << + -sext<6>(Rs.sw<5:0>); + } else { + dspac = (uint64_t)dspac >> + sext<6>(Rs.sw<5:0>); + } + }}); + 0x7: mthlip({{ + dspac = dspac << 32; + dspac |= Rs.uw; + dspctl = insertBits(dspctl, 5, 0, + dspctl<5:0> + 32); + }}); } } } @@ -2092,44 +2491,49 @@ decode OPCODE_HI default Unknown::unknown() { 0x1: lh({{ Rt.sw = Mem.sh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); 0x3: lw({{ Rt.sw = Mem.sw; }}); 0x4: lbu({{ Rt.uw = Mem.ub;}}, mem_flags = NO_ALIGN_FAULT); - 0x5: lhu({{ Rt.uw = Mem.uh; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); + 0x5: lhu({{ Rt.uw = Mem.uh; }}, + mem_flags = NO_HALF_WORD_ALIGN_FAULT); } format LoadUnalignedMemory { - 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); - Rt.uw = mem_word << mem_shift | - (Rt.uw & mask(mem_shift)); - }}); - 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; - Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | - (mem_word >> mem_shift); - }}); - } + 0x2: lwl({{ + uint32_t mem_shift = 24 - (8 * byte_offset); + Rt.uw = mem_word << mem_shift | (Rt.uw & mask(mem_shift)); + }}); + 0x6: lwr({{ + uint32_t mem_shift = 8 * byte_offset; + Rt.uw = (Rt.uw & (mask(mem_shift) << (32 - mem_shift))) | + (mem_word >> mem_shift); + }}); + } } 0x5: decode OPCODE_LO { format StoreMemory { 0x0: sb({{ Mem.ub = Rt<7:0>; }}, mem_flags = NO_ALIGN_FAULT); - 0x1: sh({{ Mem.uh = Rt<15:0>; }}, mem_flags = NO_HALF_WORD_ALIGN_FAULT); + 0x1: sh({{ Mem.uh = Rt<15:0>; }}, + mem_flags = NO_HALF_WORD_ALIGN_FAULT); 0x3: sw({{ Mem.uw = Rt<31:0>; }}); } format StoreUnalignedMemory { - 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); - uint32_t mem_shift = 32 - reg_shift; - mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | - (Rt.uw >> reg_shift); - }}); - 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; - mem_word = Rt.uw << reg_shift | - (mem_word & (mask(reg_shift))); - }}); + 0x2: swl({{ + uint32_t reg_shift = 24 - (8 * byte_offset); + uint32_t mem_shift = 32 - reg_shift; + mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | + (Rt.uw >> reg_shift); + }}); + 0x6: swr({{ + uint32_t reg_shift = 8 * byte_offset; + mem_word = Rt.uw << reg_shift | + (mem_word & (mask(reg_shift))); + }}); } format CP0Control { 0x7: cache({{ //Addr CacheEA = Rs.uw + OFFSET; - //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); - }}); + //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); + }}); } } @@ -2146,19 +2550,17 @@ decode OPCODE_HI default Unknown::unknown() { 0x7: decode OPCODE_LO { - 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, + 0x0: StoreCond::sc({{ Mem.uw = Rt.uw; }}, {{ uint64_t tmp = write_result; Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; - }}, mem_flags=LLSC, inst_flags = IsStoreConditional); - + }}, mem_flags=LLSC, + inst_flags = IsStoreConditional); format StoreMemory { - 0x1: swc1({{ Mem.uw = Ft.uw;}}); - 0x5: sdc1({{ Mem.ud = Ft.ud;}}); + 0x1: swc1({{ Mem.uw = Ft.uw; }}); + 0x5: sdc1({{ Mem.ud = Ft.ud; }}); } - 0x2: CP2Unimpl::swc2(); 0x6: CP2Unimpl::sdc2(); - } } diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa index c8eddb1ad..cb5b4372f 100644 --- a/src/arch/mips/isa/formats/control.isa +++ b/src/arch/mips/isa/formats/control.isa @@ -180,12 +180,12 @@ output exec {{ #if !FULL_SYSTEM return true; #else - MiscReg Stat = xc->readMiscReg(MipsISA::Status); + MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); switch(cop_num) { case 0: { - MiscReg Dbg = xc->readMiscReg(MipsISA::Debug); + MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG); if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode @@ -216,8 +216,8 @@ output exec {{ bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status); - MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug); + MiscReg Stat = xc->readMiscRegNoEffect(MISCREG_STATUS); + MiscReg Dbg = xc->readMiscRegNoEffect(MISCREG_DEBUG); if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode @@ -232,7 +232,7 @@ output exec {{ bool isMMUTLB(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80) + if((xc->readMiscRegNoEffect(MISCREG_CONFIG) & 0x00000380)==0x80) return true; #endif return false; diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa index 1874d37b2..7d16b4162 100755 --- a/src/arch/mips/isa/formats/dsp.isa +++ b/src/arch/mips/isa/formats/dsp.isa @@ -143,7 +143,7 @@ output exec {{ bool isDspEnabled(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - if( bits( xc->readMiscReg(MipsISA::Status), 24, 24 ) == 0 ) + if( bits( xc->readMiscReg(MISCREG_STATUS), 24, 24 ) == 0 ) return false; #else //printf("Syscall Emulation Mode: isDspEnabled() check defaults to TRUE\n"); @@ -156,7 +156,7 @@ output exec {{ bool isDspPresent(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - if( bits( xc->readMiscReg(MipsISA::Config3), 10, 10 ) == 0 ) + if( bits( xc->readMiscReg(MISCREG_CONFIG3), 10, 10 ) == 0 ) return false; #else //printf("Syscall Emulation Mode: isDspPresent() check defaults to TRUE\n"); diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index 52fcd0724..72d87f997 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -135,12 +135,13 @@ output exec {{ cpu->setFloatRegOperandBits(inst, 0, mips_nan); //Read FCSR from FloatRegFile - uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr_bits = + cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); uint32_t new_fcsr = genInvalidVector(fcsr_bits); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr); + cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr); if (traceData) { traceData->setData(mips_nan); } return true; @@ -153,13 +154,13 @@ output exec {{ fpResetCauseBits(%(CPU_exec_context)s *cpu) { //Read FCSR from FloatRegFile - uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, fcsr); + cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr); } }}; diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 4f2d33709..9d354c46a 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -90,16 +90,16 @@ output exec {{ TCBindReg &tc_bind, VPEControlReg &vpe_control, MVPConf0Reg &mvp_conf0) { - vpe_conf0 = xc->readMiscReg(VPEConf0); - tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag); - tc_bind = xc->readMiscReg(TCBind); - vpe_control = xc->readMiscReg(VPEControl); - mvp_conf0 = xc->readMiscReg(MVPConf0); + vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); + tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag); + tc_bind = xc->readMiscReg(MISCREG_TC_BIND); + vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); + mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); } void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3) { - config3 = xc->readMiscReg(Config3); + config3 = xc->readMiscReg(MISCREG_CONFIG3); } }}; diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 1af8857cc..50726cd30 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -56,29 +56,29 @@ def operands {{ 'R2': ('IntReg', 'uw','2', 'IsInteger', 5), #Special Integer Reg operands - 'LO0': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6), - 'HI0': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7), + 'LO0': ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6), + 'HI0': ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7), #Bitfield-dependent HI/LO Register Access - 'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6), - 'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7), - 'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6), - 'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7), + 'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6), + 'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7), + 'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6), + 'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7), #DSP Special Purpose Integer Operands - 'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8), - 'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1), - 'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1), - 'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1), - 'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1), - 'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1), - 'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1), - 'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1), - 'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1), - 'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1), - 'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1), - 'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1), - 'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1), + 'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8), + 'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1), + 'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1), + 'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1), + 'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1), + 'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1), + 'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1), + 'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1), + 'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1), + 'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1), + 'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1), + 'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1), + 'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1), #Floating Point Reg Operands 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1), @@ -87,11 +87,11 @@ def operands {{ 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3), #Special Purpose Floating Point Control Reg Operands - 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1), - 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2), - 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3), - 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3), - 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3), + 'FIR': ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1), + 'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2), + 'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3), + 'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3), + 'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3), #Operands For Paired Singles FP Operations 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4), @@ -104,44 +104,45 @@ def operands {{ 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7), #Status Control Reg - 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1), + 'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1), #LL Flag - 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1), + 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1), # Index Register - 'Index':('ControlReg','uw','MipsISA::Index',None,1), + 'Index':('ControlReg','uw','MISCREG_INDEX',None,1), 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1), #MT Control Regs - 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), - 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1), - 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1), - 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1), - 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1), - 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1), - 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1), - 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1), + 'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1), + 'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1), + 'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1), + 'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1), + 'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1), + 'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1), + 'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1), + 'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1), #CP0 Control Regs - 'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1), - 'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1), - 'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1), - 'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1), - 'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1), - 'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1), - 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1), - 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1), - 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1), - 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1), - 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1), - 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1), - 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1), - 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1), - 'Debug': ('ControlReg','uw', 'MipsISA::Debug',None,1), - 'Cause': ('ControlReg','uw', 'MipsISA::Cause',None,1), + 'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1), + 'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1), + 'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1), + 'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1), + 'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1), + 'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1), + 'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1), + 'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1), + 'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1), + 'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1), + 'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1), + 'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1), + 'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1), + 'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1), + 'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1), + 'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1), + 'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1), #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh index 3c81bc249..8cf94df98 100644 --- a/src/arch/mips/locked_mem.hh +++ b/src/arch/mips/locked_mem.hh @@ -50,8 +50,8 @@ template <class XC> inline void handleLockedRead(XC *xc, Request *req) { - xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf); - xc->setMiscRegNoEffect(LLFlag, true); + xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf); + xc->setMiscRegNoEffect(MISCREG_LLFLAG, true); DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link" " Address set to %x.\n", req->threadId(), req->getPaddr() & ~0xf); @@ -67,14 +67,14 @@ handleLockedWrite(XC *xc, Request *req) req->setExtraData(2); } else { // standard store conditional - bool lock_flag = xc->readMiscRegNoEffect(LLFlag); - Addr lock_addr = xc->readMiscRegNoEffect(LLAddr); + bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LLFLAG); + Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LLADDR); if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { // Lock flag not set or addr mismatch in CPU; // don't even bother sending to memory system req->setExtraData(0); - xc->setMiscRegNoEffect(LLFlag, false); + xc->setMiscRegNoEffect(MISCREG_LLFLAG, false); // the rest of this code is not architectural; // it's just a debugging aid to help detect @@ -83,17 +83,12 @@ handleLockedWrite(XC *xc, Request *req) int stCondFailures = xc->readStCondFailures(); stCondFailures++; xc->setStCondFailures(stCondFailures); - if (stCondFailures % 10 == 0) { + if (stCondFailures % 100000 == 0) { warn("%i: context %d: %d consecutive " "store conditional failures\n", curTick, xc->contextId(), stCondFailures); } - if (stCondFailures == 5000) { - panic("Max (5000) Store Conditional Fails Reached. " - "Check Code For Deadlock.\n"); - } - if (!lock_flag){ DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, " "Store Conditional Failed.\n", diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh index a6363e191..7217c335e 100755 --- a/src/arch/mips/mt.hh +++ b/src/arch/mips/mt.hh @@ -55,7 +55,7 @@ template <class TC> inline unsigned getVirtProcNum(TC *tc) { - TCBindReg tcbind = tc->readMiscRegNoEffect(TCBind); + TCBindReg tcbind = tc->readMiscRegNoEffect(MISCREG_TC_BIND); return tcbind.curVPE; } @@ -63,7 +63,7 @@ template <class TC> inline unsigned getTargetThread(TC *tc) { - VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(VPEControl); + VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL); return vpeCtrl.targTC; } @@ -77,7 +77,7 @@ haltThread(TC *tc) // Save last known PC in TCRestart // @TODO: Needs to check if this is a branch and if so, // take previous instruction - tc->setMiscReg(TCRestart, tc->readNextPC()); + tc->setMiscReg(MISCREG_TC_RESTART, tc->readNextPC()); warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(), @@ -91,7 +91,7 @@ restoreThread(TC *tc) { if (tc->status() != TC::Active) { // Restore PC from TCRestart - IntReg pc = tc->readMiscRegNoEffect(TCRestart); + IntReg pc = tc->readMiscRegNoEffect(MISCREG_TC_RESTART); // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY tc->setPC(pc); @@ -109,31 +109,33 @@ template <class TC> void forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt) { - MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MVPConf0); + MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0); int num_threads = mvpConf.ptc + 1; int success = 0; for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) { TCBindReg tidTCBind = - tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid); - TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind); + tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag, tid); + TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND); - if (tidTCBind.curVPE = tcBind.curVPE) { + if (tidTCBind.curVPE == tcBind.curVPE) { TCStatusReg tidTCStatus = - tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag,tid); + tc->readRegOtherThread(MISCREG_TC_STATUS + + Ctrl_Base_DepTag,tid); TCHaltReg tidTCHalt = - tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag,tid); + tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,tid); if (tidTCStatus.da == 1 && tidTCHalt.h == 0 && tidTCStatus.a == 0 && success == 0) { - tc->setRegOtherThread(TCRestart + Ctrl_Base_DepTag, Rs, tid); + tc->setRegOtherThread(MISCREG_TC_RESTART + + Ctrl_Base_DepTag, Rs, tid); tc->setRegOtherThread(Rd_bits, Rt, tid); - StatusReg status = tc->readMiscReg(Status); - TCStatusReg tcStatus = tc->readMiscReg(TCStatus); + StatusReg status = tc->readMiscReg(MISCREG_STATUS); + TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS); // Set Run-State to Running tidTCStatus.rnst = 0; @@ -149,7 +151,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt) tidTCStatus.asid = tcStatus.asid; // Write Status Register - tc->setRegOtherThread(TCStatus + Ctrl_Base_DepTag, + tc->setRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag, tidTCStatus, tid); // Mark As Successful Fork @@ -161,9 +163,10 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt) } if (success == 0) { - VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl); + VPEControlReg vpeControl = + tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL); vpeControl.excpt = 1; - tc->setMiscReg(VPEControl, vpeControl); + tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl); fault = new ThreadFault(); } } @@ -174,21 +177,24 @@ int yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask) { if (src_reg == 0) { - MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MVPConf0); + MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0); ThreadID num_threads = mvpConf0.ptc + 1; int ok = 0; // Get Current VPE & TC numbers from calling thread - TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind); + TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND); for (ThreadID tid = 0; tid < num_threads; tid++) { TCStatusReg tidTCStatus = - tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag, tid); + tc->readRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag, + tid); TCHaltReg tidTCHalt = - tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag, tid); + tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag, + tid); TCBindReg tidTCBind = - tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid); + tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag, + tid); if (tidTCBind.curVPE == tcBind.curVPE && tidTCBind.curTC == tcBind.curTC && @@ -200,23 +206,24 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask) } if (ok == 1) { - TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus); + TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); tcStatus.a = 0; - tc->setMiscReg(TCStatus, tcStatus); + tc->setMiscReg(MISCREG_TC_STATUS, tcStatus); warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId()); } } else if (src_reg > 0) { if (src_reg && !yield_mask != 0) { - VPEControlReg vpeControl = tc->readMiscReg(VPEControl); + VPEControlReg vpeControl = tc->readMiscReg(MISCREG_VPE_CONTROL); vpeControl.excpt = 2; - tc->setMiscReg(VPEControl, vpeControl); + tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl); fault = new ThreadFault(); } else { } } else if (src_reg != -2) { - TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus); - VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl); + TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); + VPEControlReg vpeControl = + tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL); if (vpeControl.ysi == 1 && tcStatus.dt == 1 ) { vpeControl.excpt = 4; @@ -237,14 +244,14 @@ updateStatusView(TC *tc) { // TCStatus' register view must be the same as // Status register view for CU, MX, KSU bits - TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus); - StatusReg status = tc->readMiscRegNoEffect(Status); + TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); + StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); status.cu = tcStatus.tcu; status.mx = tcStatus.tmx; status.ksu = tcStatus.tksu; - tc->setMiscRegNoEffect(Status, status); + tc->setMiscRegNoEffect(MISCREG_STATUS, status); } // TC will usually be a object derived from ThreadContext @@ -255,14 +262,14 @@ updateTCStatusView(TC *tc) { // TCStatus' register view must be the same as // Status register view for CU, MX, KSU bits - TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus); - StatusReg status = tc->readMiscRegNoEffect(Status); + TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); + StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); tcStatus.tcu = status.cu; tcStatus.tmx = status.mx; tcStatus.tksu = status.ksu; - tc->setMiscRegNoEffect(TCStatus, tcStatus); + tc->setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus); } } // namespace MipsISA diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index b996b4717..fdb04b131 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -58,11 +58,11 @@ const uint32_t MIPS32_QNAN = 0x7fbfffff; const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff); enum FPControlRegNums { - FIR = NumFloatArchRegs, - FCCR, - FEXR, - FENR, - FCSR + FLOATREG_FIR = NumFloatArchRegs, + FLOATREG_FCCR, + FLOATREG_FEXR, + FLOATREG_FENR, + FLOATREG_FCSR }; enum FCSRBits { @@ -81,21 +81,21 @@ enum FCSRFields { }; enum MiscIntRegNums { - LO = NumIntArchRegs, - HI, - DSPACX0, - DSPLo1, - DSPHi1, - DSPACX1, - DSPLo2, - DSPHi2, - DSPACX2, - DSPLo3, - DSPHi3, - DSPACX3, - DSPControl, - DSPLo0 = LO, - DSPHi0 = HI + INTREG_LO = NumIntArchRegs, + INTREG_DSP_LO0 = INTREG_LO, + INTREG_HI, + INTREG_DSP_HI0 = INTREG_HI, + INTREG_DSP_ACX0, + INTREG_DSP_LO1, + INTREG_DSP_HI1, + INTREG_DSP_ACX1, + INTREG_DSP_LO2, + INTREG_DSP_HI2, + INTREG_DSP_ACX2, + INTREG_DSP_LO3, + INTREG_DSP_HI3, + INTREG_DSP_ACX3, + INTREG_DSP_CONTROL }; // semantically meaningful register indices @@ -130,158 +130,158 @@ const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; // The first set of names classify the CP0 names as Register Banks // for easy indexing when using the 'RD + SEL' index combination // in CP0 instructions. -enum MiscRegTags { - Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3 - MVPControl, - MVPConf0, - MVPConf1, - - CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15 - VPEControl, - VPEConf0, - VPEConf1, - YQMask, - VPESchedule, - VPEScheFBack, - VPEOpt, - - EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23 - TCStatus, - TCBind, - TCRestart, - TCHalt, - TCContext, - TCSchedule, - TCScheFBack, - - EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24 - - Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33 - ContextConfig, - - PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41 - PageGrain = Ctrl_Base_DepTag + 41, - - Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55 - SRSConf0, - SRSConf1, - SRSConf2, - SRSConf3, - SRSConf4, - - HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63 - - BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71 - - Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79 - - EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87 - - Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95 - - Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103 - IntCtl, - SRSCtl, - SRSMap, - - Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111 - - EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119 - - PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127, - EBase, - - Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135 - Config1, - Config2, - Config3, - Config4, - Config5, - Config6, - Config7, - - - LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143 - - WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151 - WatchLo1, - WatchLo2, - WatchLo3, - WatchLo4, - WatchLo5, - WatchLo6, - WatchLo7, - - WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159 - WatchHi1, - WatchHi2, - WatchHi3, - WatchHi4, - WatchHi5, - WatchHi6, - WatchHi7, - - XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167 +enum MiscRegIndex{ + MISCREG_INDEX = 0, //Bank 0: 0 - 3 + MISCREG_MVP_CONTROL, + MISCREG_MVP_CONF0, + MISCREG_MVP_CONF1, + + MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15 + MISCREG_VPE_CONTROL, + MISCREG_VPE_CONF0, + MISCREG_VPE_CONF1, + MISCREG_YQMASK, + MISCREG_VPE_SCHEDULE, + MISCREG_VPE_SCHEFBACK, + MISCREG_VPE_OPT, + + MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23 + MISCREG_TC_STATUS, + MISCREG_TC_BIND, + MISCREG_TC_RESTART, + MISCREG_TC_HALT, + MISCREG_TC_CONTEXT, + MISCREG_TC_SCHEDULE, + MISCREG_TC_SCHEFBACK, + + MISCREG_ENTRYLO1 = 24, // Bank 3: 24 + + MISCREG_CONTEXT = 32, // Bank 4: 32 - 33 + MISCREG_CONTEXT_CONFIG, + + MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41 + MISCREG_PAGEGRAIN = 41, + + MISCREG_WIRED = 48, //Bank 6:48-55 + MISCREG_SRS_CONF0, + MISCREG_SRS_CONF1, + MISCREG_SRS_CONF2, + MISCREG_SRS_CONF3, + MISCREG_SRS_CONF4, + + MISCREG_HWRENA = 56, //Bank 7: 56-63 + + MISCREG_BADVADDR = 64, //Bank 8: 64-71 + + MISCREG_COUNT = 72, //Bank 9: 72-79 + + MISCREG_ENTRYHI = 80, //Bank 10: 80-87 + + MISCREG_COMPARE = 88, //Bank 11: 88-95 + + MISCREG_STATUS = 96, //Bank 12: 96-103 + MISCREG_INTCTL, + MISCREG_SRSCTL, + MISCREG_SRSMAP, + + MISCREG_CAUSE = 104, //Bank 13: 104-111 + + MISCREG_EPC = 112, //Bank 14: 112-119 + + MISCREG_PRID = 120, //Bank 15: 120-127, + MISCREG_EBASE, + + MISCREG_CONFIG = 128, //Bank 16: 128-135 + MISCREG_CONFIG1, + MISCREG_CONFIG2, + MISCREG_CONFIG3, + MISCREG_CONFIG4, + MISCREG_CONFIG5, + MISCREG_CONFIG6, + MISCREG_CONFIG7, + + + MISCREG_LLADDR = 136, //Bank 17: 136-143 + + MISCREG_WATCHLO0 = 144, //Bank 18: 144-151 + MISCREG_WATCHLO1, + MISCREG_WATCHLO2, + MISCREG_WATCHLO3, + MISCREG_WATCHLO4, + MISCREG_WATCHLO5, + MISCREG_WATCHLO6, + MISCREG_WATCHLO7, + + MISCREG_WATCHHI0 = 152, //Bank 19: 152-159 + MISCREG_WATCHHI1, + MISCREG_WATCHHI2, + MISCREG_WATCHHI3, + MISCREG_WATCHHI4, + MISCREG_WATCHHI5, + MISCREG_WATCHHI6, + MISCREG_WATCHHI7, + + MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167 //Bank 21: 168-175 //Bank 22: 176-183 - Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191 - TraceControl1, - TraceControl2, - UserTraceData, - TraceBPC, + MISCREG_DEBUG = 184, //Bank 23: 184-191 + MISCREG_TRACE_CONTROL1, + MISCREG_TRACE_CONTROL2, + MISCREG_USER_TRACE_DATA, + MISCREG_TRACE_BPC, - DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199 + MISCREG_DEPC = 192, //Bank 24: 192-199 - PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207 - PerfCnt1, - PerfCnt2, - PerfCnt3, - PerfCnt4, - PerfCnt5, - PerfCnt6, - PerfCnt7, + MISCREG_PERFCNT0 = 200, //Bank 25: 200-207 + MISCREG_PERFCNT1, + MISCREG_PERFCNT2, + MISCREG_PERFCNT3, + MISCREG_PERFCNT4, + MISCREG_PERFCNT5, + MISCREG_PERFCNT6, + MISCREG_PERFCNT7, - ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215 + MISCREG_ERRCTL = 208, //Bank 26: 208-215 - CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223 - CacheErr1, - CacheErr2, - CacheErr3, + MISCREG_CACHEERR0 = 216, //Bank 27: 216-223 + MISCREG_CACHEERR1, + MISCREG_CACHEERR2, + MISCREG_CACHEERR3, - TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231 - DataLo1, - TagLo2, - DataLo3, - TagLo4, - DataLo5, - TagLo6, - DataLo7, + MISCREG_TAGLO0 = 224, //Bank 28: 224-231 + MISCREG_DATALO1, + MISCREG_TAGLO2, + MISCREG_DATALO3, + MISCREG_TAGLO4, + MISCREG_DATALO5, + MISCREG_TAGLO6, + MISCREG_DATALO7, - TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239 - DataHi1, - TagHi2, - DataHi3, - TagHi4, - DataHi5, - TagHi6, - DataHi7, + MISCREG_TAGHI0 = 232, //Bank 29: 232-239 + MISCREG_DATAHI1, + MISCREG_TAGHI2, + MISCREG_DATAHI3, + MISCREG_TAGHI4, + MISCREG_DATAHI5, + MISCREG_TAGHI6, + MISCREG_DATAHI7, - ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247 + MISCREG_ERROR_EPC = 240, //Bank 30: 240-247 - DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256 + MISCREG_DESAVE = 248, //Bank 31: 248-256 - LLFlag = Ctrl_Base_DepTag + 257, + MISCREG_LLFLAG = 257, - NumControlRegs + MISCREG_NUMREGS }; const int TotalDataRegs = NumIntRegs + NumFloatRegs; -const int NumMiscRegs = NumControlRegs; +const int NumMiscRegs = MISCREG_NUMREGS; const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 37c1ecee3..e01c06ae5 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -311,7 +311,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) if (IsKSeg0(req->getVaddr())) { // Address will not be translated through TLB, set response, and go! req->setPaddr(KSeg02Phys(req->getVaddr())); - if (getOperatingMode(tc->readMiscReg(Status)) != mode_kernel || + if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel || req->isMisaligned()) { AddressErrorFault *Flt = new AddressErrorFault(); /* BadVAddr must be set */ @@ -386,7 +386,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) } } else { // Didn't find any match, return a TLB Refill Exception - ItbRefillFault *Flt=new ItbRefillFault(); + ItbRefillFault *Flt = new ItbRefillFault(); /* EntryHi VPN, ASID fields must be set */ Flt->entryHiAsid = Asid; Flt->entryHiVPN2 = (VPN >> 2); @@ -431,7 +431,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) if (IsKSeg0(req->getVaddr())) { // Address will not be translated through TLB, set response, and go! req->setPaddr(KSeg02Phys(req->getVaddr())); - if (getOperatingMode(tc->readMiscReg(Status)) != mode_kernel || + if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel || req->isMisaligned()) { StoreAddressErrorFault *Flt = new StoreAddressErrorFault(); /* BadVAddr must be set */ diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 37cd838e5..1e58238e9 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -66,8 +66,8 @@ bool isSnan(void *val_ptr, int size); static inline bool inUserMode(ThreadContext *tc) { - MiscReg Stat = tc->readMiscReg(MipsISA::Status); - MiscReg Dbg = tc->readMiscReg(MipsISA::Debug); + MiscReg Stat = tc->readMiscReg(MISCREG_STATUS); + MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG); if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc index 6e894e8df..02d4f4dbf 100644 --- a/src/arch/sparc/nativetrace.cc +++ b/src/arch/sparc/nativetrace.cc @@ -36,7 +36,7 @@ namespace Trace { -static char *intRegNames[SparcISA::NumIntArchRegs] = { +static const char *intRegNames[SparcISA::NumIntArchRegs] = { //Global registers "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", //Output registers @@ -58,7 +58,7 @@ Trace::SparcNativeTrace::check(NativeTraceRecord *record) // I doubt a real SPARC will describe more integer registers than this. assert(SparcISA::NumIntArchRegs == 32); - char **regName = intRegNames; + const char **regName = intRegNames; for (int i = 0; i < SparcISA::NumIntArchRegs; i++) { regVal = tc->readIntReg(i); read(&realRegVal, sizeof(realRegVal)); diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 1b84a0784..41b0f2043 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -837,7 +837,7 @@ handleSparcErrorRegAccess: regAccessOk: handleMmuRegAccess: DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); - req->setMmapedIpr(true); + req->setFlags(Request::MMAPED_IPR); req->setPaddr(req->getVaddr()); return NoFault; }; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index cabdc2172..698216139 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -517,34 +517,38 @@ let {{ class Xor(LogicRegOp): code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' - # Neither of these is quite correct because it assumes that right shifting - # a signed or unsigned value does sign or zero extension respectively. - # The C standard says that what happens on a right shift with a 1 in the - # MSB position is undefined. On x86 and under likely most compilers the - # "right thing" happens, but this isn't a guarantee. class Mul1s(WrRegOp): code = ''' ProdLow = psrc1 * op2; int halfSize = (dataSize * 8) / 2; - int64_t spsrc1_h = spsrc1 >> halfSize; - int64_t spsrc1_l = spsrc1 & mask(halfSize); - int64_t spsrc2_h = sop2 >> halfSize; - int64_t spsrc2_l = sop2 & mask(halfSize); - ProdHi = ((spsrc1_l * spsrc2_h + spsrc1_h * spsrc2_l + - ((spsrc1_l * spsrc2_l) >> halfSize)) >> halfSize) + - spsrc1_h * spsrc2_h; + uint64_t shifter = (1ULL << halfSize); + uint64_t hiResult; + uint64_t psrc1_h = psrc1 / shifter; + uint64_t psrc1_l = psrc1 & mask(halfSize); + uint64_t psrc2_h = op2 / shifter; + uint64_t psrc2_l = op2 & mask(halfSize); + hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + + ((psrc1_l * psrc2_l) / shifter)) /shifter) + + psrc1_h * psrc2_h; + if (spsrc1 < 0) + hiResult -= op2; + int64_t bigSop2 = sop2; + if (bigSop2 < 0) + hiResult -= psrc1; + ProdHi = hiResult; ''' class Mul1u(WrRegOp): code = ''' ProdLow = psrc1 * op2; int halfSize = (dataSize * 8) / 2; - uint64_t psrc1_h = psrc1 >> halfSize; + uint64_t shifter = (1ULL << halfSize); + uint64_t psrc1_h = psrc1 / shifter; uint64_t psrc1_l = psrc1 & mask(halfSize); - uint64_t psrc2_h = op2 >> halfSize; + uint64_t psrc2_h = op2 / shifter; uint64_t psrc2_l = op2 & mask(halfSize); ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + - ((psrc1_l * psrc2_l) >> halfSize)) >> halfSize) + + ((psrc1_l * psrc2_l) / shifter)) / shifter) + psrc1_h * psrc2_h; ''' diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 418f6ffb2..5280b9ba8 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -197,7 +197,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc) panic("CPUID memory space not yet implemented!\n"); } else if (prefix == IntAddrPrefixMSR) { vaddr = vaddr >> 3; - req->setMmapedIpr(true); + req->setFlags(Request::MMAPED_IPR); Addr regNum = 0; switch (vaddr & ~IntAddrPrefixMask) { case 0x10: @@ -526,7 +526,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc) // space. assert(!(IOPort & ~0xFFFF)); if (IOPort == 0xCF8 && req->getSize() == 4) { - req->setMmapedIpr(true); + req->setFlags(Request::MMAPED_IPR); req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); } else if ((IOPort & ~mask(2)) == 0xCFC) { Addr configAddress = diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index 16fc698dd..15ad88f76 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -107,7 +107,6 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) { case ELFOSABI_LINUX: - case ELFOSABI_ARM: opSys = ObjectFile::Linux; break; case ELFOSABI_SOLARIS: @@ -116,6 +115,9 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) case ELFOSABI_TRU64: opSys = ObjectFile::Tru64; break; + case ELFOSABI_ARM: + opSys = ObjectFile::LinuxArmOABI; + break; default: opSys = ObjectFile::UnknownOpSys; } diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh index 73df5caf6..e511451b7 100644 --- a/src/base/loader/object_file.hh +++ b/src/base/loader/object_file.hh @@ -59,7 +59,8 @@ class ObjectFile UnknownOpSys, Tru64, Linux, - Solaris + Solaris, + LinuxArmOABI }; protected: diff --git a/src/cpu/NativeTrace.py b/src/cpu/NativeTrace.py index 7fd240543..dba6de067 100644 --- a/src/cpu/NativeTrace.py +++ b/src/cpu/NativeTrace.py @@ -28,9 +28,9 @@ from m5.SimObject import SimObject from m5.params import * -from InstTracer import InstTracer +from ExeTracer import ExeTracer -class NativeTrace(InstTracer): +class NativeTrace(ExeTracer): abstract = True type = 'NativeTrace' cxx_class = 'Trace::NativeTrace' diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index c6e57b612..f4ff88209 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -857,9 +857,8 @@ inline Fault BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) { reqMade = true; - Request *req = new Request(); - req->setVirt(asid, addr, sizeof(T), flags, this->PC); - req->setThreadContext(thread->contextId(), threadNumber); + Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, + thread->contextId(), threadNumber); fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read); @@ -913,9 +912,8 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) } reqMade = true; - Request *req = new Request(); - req->setVirt(asid, addr, sizeof(T), flags, this->PC); - req->setThreadContext(thread->contextId(), threadNumber); + Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, + thread->contextId(), threadNumber); fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc index 47c58434f..8c17eb825 100644 --- a/src/cpu/nativetrace.cc +++ b/src/cpu/nativetrace.cc @@ -38,7 +38,7 @@ using namespace std; namespace Trace { NativeTrace::NativeTrace(const Params *p) - : InstTracer(p) + : ExeTracer(p) { if (ListenSocket::allDisabled()) fatal("All listeners are disabled!"); diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh index 34869f263..6ad6b0242 100644 --- a/src/cpu/nativetrace.hh +++ b/src/cpu/nativetrace.hh @@ -37,8 +37,8 @@ #include "base/socket.hh" #include "base/trace.hh" #include "base/types.hh" +#include "cpu/exetrace.hh" #include "cpu/static_inst.hh" -#include "sim/insttracer.hh" class ThreadContext; @@ -46,7 +46,7 @@ namespace Trace { class NativeTrace; -class NativeTraceRecord : public InstRecord +class NativeTraceRecord : public ExeTracerRecord { protected: NativeTrace * parent; @@ -56,7 +56,7 @@ class NativeTraceRecord : public InstRecord Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, Addr _pc, bool spec, const StaticInstPtr _macroStaticInst = NULL, MicroPC _upc = 0) - : InstRecord(_when, _thread, _staticInst, _pc, spec, + : ExeTracerRecord(_when, _thread, _staticInst, _pc, spec, _macroStaticInst, _upc), parent(_parent) { @@ -65,7 +65,7 @@ class NativeTraceRecord : public InstRecord void dump(); }; -class NativeTrace : public InstTracer +class NativeTrace : public ExeTracer { protected: int fd; diff --git a/src/cpu/o3/cpu_builder.cc b/src/cpu/o3/cpu_builder.cc index a433235a0..097dc7181 100644 --- a/src/cpu/o3/cpu_builder.cc +++ b/src/cpu/o3/cpu_builder.cc @@ -51,14 +51,17 @@ DerivO3CPUParams::create() // Full-system only supports a single thread for the moment. ThreadID actual_num_threads = 1; #else + if (workload.size() > numThreads) { + fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU", + workload.size(), numThreads); + } else if (workload.size() == 0) { + fatal("Must specify at least one workload!"); + } + // In non-full-system mode, we infer the number of threads from // the workload if it's not explicitly specified. ThreadID actual_num_threads = (numThreads >= workload.size()) ? numThreads : workload.size(); - - if (workload.size() == 0) { - fatal("Must specify at least one workload!"); - } #endif numThreads = actual_num_threads; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index a76e07576..3781113bd 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -596,9 +596,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. - RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0, - fetch_PC, cpu->thread[tid]->contextId(), - tid); + RequestPtr mem_req = + new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, + fetch_PC, cpu->thread[tid]->contextId(), tid); memReq[tid] = mem_req; diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index dd9e23f97..f242645a2 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -211,7 +211,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags) memReq->cmd = Read; memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -252,7 +251,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) // memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -293,7 +291,6 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx) req->time = curTick; assert(!req->data); req->data = new uint8_t[64]; - req->flags &= ~INST_FETCH; Fault fault = cpu->read(req, data); memcpy(req->data, &data, sizeof(T)); @@ -363,7 +360,6 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx) memcpy(req->data,(uint8_t *)&data,req->size); req->completionEvent = NULL; req->time = curTick; - req->flags &= ~INST_FETCH; MemAccessResult result = dcacheInterface->access(req); // Ugly hack to get an event scheduled *only* if the access is diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 921c8c19d..732bb637b 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -282,7 +282,6 @@ BaseSimpleCPU::copy(Addr dest) memReq->dest = dest_addr; memReq->size = 64; memReq->time = curTick; - memReq->flags &= ~INST_FETCH; dcacheInterface->access(memReq); } } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index d9d624e77..8a44eba37 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -262,7 +262,9 @@ class SimpleThread : public ThreadState { int flatIndex = isa.flattenIntIndex(reg_idx); assert(flatIndex < TheISA::NumIntRegs); - return intRegs[flatIndex]; + uint64_t regVal = intRegs[flatIndex]; + DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal); + return regVal; } FloatReg readFloatReg(int reg_idx) @@ -283,6 +285,7 @@ class SimpleThread : public ThreadState { int flatIndex = isa.flattenIntIndex(reg_idx); assert(flatIndex < TheISA::NumIntRegs); + DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val); intRegs[flatIndex] = val; } diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc index 3d4e71888..a8cceda1f 100644 --- a/src/dev/ide_ctrl.cc +++ b/src/dev/ide_ctrl.cc @@ -107,6 +107,9 @@ IdeController::IdeController(Params *p) } primary.select(false); secondary.select(false); + + ioEnabled = (config.command & htole(PCI_CMD_IOSE)); + bmEnabled = (config.command & htole(PCI_CMD_BME)); } bool diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index d89ed9dc6..2d1827998 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -86,7 +86,8 @@ class SouthBridge(SimObject): ide.BAR3Size = '3B' ide.BAR3LegacyIO = True ide.BAR4 = 1 - ide.Command = 1 + ide.Command = 0 + ide.ProgIF = 0x80 ide.InterruptLine = 14 ide.InterruptPin = 1 diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 0940893bc..80b7c545c 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -268,8 +268,9 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, blk = tags->accessBlock(pkt->getAddr(), lat); - DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(), - (blk) ? "hit" : "miss"); + DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(), + pkt->req->isInstFetch() ? " (ifetch)" : "", + pkt->getAddr(), (blk) ? "hit" : "miss"); if (blk != NULL) { diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 5680fd970..d87ad3b22 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -211,8 +211,8 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt) #define CASE(A, T) \ case sizeof(T): \ - DPRINTF(MemoryAccess, A " of size %i on address 0x%x data 0x%x\n", \ - pkt->getSize(), pkt->getAddr(), pkt->get<T>()); \ + DPRINTF(MemoryAccess,"%s of size %i on address 0x%x data 0x%x\n", \ + A, pkt->getSize(), pkt->getAddr(), pkt->get<T>()); \ break @@ -224,8 +224,8 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt) CASE(A, uint16_t); \ CASE(A, uint8_t); \ default: \ - DPRINTF(MemoryAccess, A " of size %i on address 0x%x\n", \ - pkt->getSize(), pkt->getAddr()); \ + DPRINTF(MemoryAccess, "%s of size %i on address 0x%x\n", \ + A, pkt->getSize(), pkt->getAddr()); \ } \ } while (0) @@ -281,6 +281,7 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt) if (overwrite_mem) std::memcpy(hostAddr, &overwrite_val, pkt->getSize()); + assert(!pkt->req->isInstFetch()); TRACE_PACKET("Read/Write"); } else if (pkt->isRead()) { assert(!pkt->isWrite()); @@ -289,11 +290,12 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt) } if (pmemAddr) memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); - TRACE_PACKET("Read"); + TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read"); } else if (pkt->isWrite()) { if (writeOK(pkt)) { if (pmemAddr) memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize()); + assert(!pkt->req->isInstFetch()); TRACE_PACKET("Write"); } } else if (pkt->isInvalidate()) { diff --git a/src/mem/request.hh b/src/mem/request.hh index 870930317..c8c31ffcd 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -132,17 +132,17 @@ class Request : public FastAlloc * The physical address of the request. Valid only if validPaddr * is set. */ - Addr paddr; + Addr _paddr; /** * The size of the request. This field must be set when vaddr or * paddr is written via setVirt() or setPhys(), so it is always * valid as long as one of the address fields is valid. */ - int size; + int _size; /** Flag structure for the request. */ - Flags flags; + Flags _flags; /** Private flags for field validity checking. */ PrivateFlags privateFlags; @@ -155,15 +155,15 @@ class Request : public FastAlloc Tick _time; /** The address space ID. */ - int asid; + int _asid; /** The virtual address of the request. */ - Addr vaddr; + Addr _vaddr; /** * Extra data for the request, such as the return value of * store conditional or the compare value for a CAS. */ - uint64_t extraData; + uint64_t _extraData; /** The context ID (for statistics, typically). */ int _contextId; @@ -171,10 +171,13 @@ class Request : public FastAlloc int _threadId; /** program counter of initiating access; for tracing/debugging */ - Addr pc; + Addr _pc; public: - /** Minimal constructor. No fields are initialized. */ + /** Minimal constructor. No fields are initialized. + * (Note that _flags and privateFlags are cleared by Flags + * default constructor.) + */ Request() {} @@ -218,23 +221,23 @@ class Request : public FastAlloc * allocated Request object. */ void - setPhys(Addr _paddr, int _size, Flags _flags, Tick time) + setPhys(Addr paddr, int size, Flags flags, Tick time) { - assert(_size >= 0); - paddr = _paddr; - size = _size; + assert(size >= 0); + _paddr = paddr; + _size = size; _time = time; - flags.clear(~STICKY_FLAGS); - flags.set(_flags); + _flags.clear(~STICKY_FLAGS); + _flags.set(flags); privateFlags.clear(~STICKY_PRIVATE_FLAGS); privateFlags.set(VALID_PADDR|VALID_SIZE); } void - setPhys(Addr _paddr, int _size, Flags _flags) + setPhys(Addr paddr, int size, Flags flags) { - setPhys(_paddr, _size, _flags, curTick); + setPhys(paddr, size, flags, curTick); } /** @@ -242,18 +245,17 @@ class Request : public FastAlloc * allocated Request object. */ void - setVirt(int _asid, Addr _vaddr, int _size, Flags _flags, Addr _pc) + setVirt(int asid, Addr vaddr, int size, Flags flags, Addr pc) { - assert(_size >= 0); - asid = _asid; - vaddr = _vaddr; - size = _size; - flags = _flags; - pc = _pc; + assert(size >= 0); + _asid = asid; + _vaddr = vaddr; + _size = size; + _pc = pc; _time = curTick; - flags.clear(~STICKY_FLAGS); - flags.set(_flags); + _flags.clear(~STICKY_FLAGS); + _flags.set(flags); privateFlags.clear(~STICKY_PRIVATE_FLAGS); privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC); } @@ -265,10 +267,10 @@ class Request : public FastAlloc * to guarantee that the size and flags are also set. */ void - setPaddr(Addr _paddr) + setPaddr(Addr paddr) { assert(privateFlags.isSet(VALID_VADDR)); - paddr = _paddr; + _paddr = paddr; privateFlags.set(VALID_PADDR); } @@ -280,14 +282,14 @@ class Request : public FastAlloc { assert(privateFlags.isSet(VALID_VADDR)); assert(privateFlags.noneSet(VALID_PADDR)); - assert(split_addr > vaddr && split_addr < vaddr + size); + assert(split_addr > _vaddr && split_addr < _vaddr + _size); req1 = new Request; *req1 = *this; req2 = new Request; *req2 = *this; - req1->size = split_addr - vaddr; - req2->vaddr = split_addr; - req2->size = size - req1->size; + req1->_size = split_addr - _vaddr; + req2->_vaddr = split_addr; + req2->_size = _size - req1->_size; } /** @@ -303,7 +305,7 @@ class Request : public FastAlloc getPaddr() { assert(privateFlags.isSet(VALID_PADDR)); - return paddr; + return _paddr; } /** @@ -319,7 +321,7 @@ class Request : public FastAlloc getSize() { assert(privateFlags.isSet(VALID_SIZE)); - return size; + return _size; } /** Accessor for time. */ @@ -342,14 +344,18 @@ class Request : public FastAlloc getFlags() { assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); - return flags; + return _flags; } + /** Note that unlike other accessors, this function sets *specific + flags* (ORs them in); it does not assign its argument to the + _flags field. Thus this method should rightly be called + setFlags() and not just flags(). */ void - setFlags(Flags _flags) + setFlags(Flags flags) { assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR)); - flags.set(_flags); + _flags.set(flags); } /** Accessor function for vaddr.*/ @@ -357,7 +363,7 @@ class Request : public FastAlloc getVaddr() { assert(privateFlags.isSet(VALID_VADDR)); - return vaddr; + return _vaddr; } /** Accessor function for asid.*/ @@ -365,7 +371,7 @@ class Request : public FastAlloc getAsid() { assert(privateFlags.isSet(VALID_VADDR)); - return asid; + return _asid; } /** Accessor function for asi.*/ @@ -373,22 +379,7 @@ class Request : public FastAlloc getAsi() { assert(privateFlags.isSet(VALID_VADDR)); - return flags & ASI_BITS; - } - - /** Accessor function for MMAPED_IPR flag. */ - bool - isMmapedIpr() - { - assert(privateFlags.isSet(VALID_PADDR)); - return flags.isSet(MMAPED_IPR); - } - - void - setMmapedIpr(bool r) - { - assert(VALID_VADDR); - flags.set(MMAPED_IPR); + return _flags & ASI_BITS; } /** Accessor function to check if sc result is valid. */ @@ -403,14 +394,14 @@ class Request : public FastAlloc getExtraData() const { assert(privateFlags.isSet(VALID_EXTRA_DATA)); - return extraData; + return _extraData; } /** Accessor function for store conditional return value.*/ void - setExtraData(uint64_t _extraData) + setExtraData(uint64_t extraData) { - extraData = _extraData; + _extraData = extraData; privateFlags.set(VALID_EXTRA_DATA); } @@ -447,31 +438,33 @@ class Request : public FastAlloc getPC() const { assert(privateFlags.isSet(VALID_PC)); - return pc; + return _pc; } - /** Accessor Function to Check Cacheability. */ - bool isUncacheable() const { return flags.isSet(UNCACHEABLE); } - bool isInstFetch() const { return flags.isSet(INST_FETCH); } - bool isPrefetch() const { return flags.isSet(PREFETCH); } - bool isLLSC() const { return flags.isSet(LLSC); } - bool isLocked() const { return flags.isSet(LOCKED); } - bool isSwap() const { return flags.isSet(MEM_SWAP|MEM_SWAP_COND); } - bool isCondSwap() const { return flags.isSet(MEM_SWAP_COND); } + /** Accessor functions for flags. Note that these are for testing + only; setting flags should be done via setFlags(). */ + bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); } + bool isInstFetch() const { return _flags.isSet(INST_FETCH); } + bool isPrefetch() const { return _flags.isSet(PREFETCH); } + bool isLLSC() const { return _flags.isSet(LLSC); } + bool isLocked() const { return _flags.isSet(LOCKED); } + bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); } + bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); } + bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); } bool isMisaligned() const { - if (flags.isSet(NO_ALIGN_FAULT)) + if (_flags.isSet(NO_ALIGN_FAULT)) return false; - if ((vaddr & 0x1)) + if ((_vaddr & 0x1)) return true; - if (flags.isSet(NO_HALF_WORD_ALIGN_FAULT)) + if (_flags.isSet(NO_HALF_WORD_ALIGN_FAULT)) return false; - if ((vaddr & 0x2)) + if ((_vaddr & 0x2)) return true; return false; diff --git a/src/mem/ruby/tester/DetermGETXGenerator.cc b/src/mem/ruby/tester/DetermGETXGenerator.cc index 1eb9cb3ee..934b6d4e5 100644 --- a/src/mem/ruby/tester/DetermGETXGenerator.cc +++ b/src/mem/ruby/tester/DetermGETXGenerator.cc @@ -1,58 +1,30 @@ - /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/DetermGETXGenerator.hh b/src/mem/ruby/tester/DetermGETXGenerator.hh index 7d7e9ea70..567177c6d 100644 --- a/src/mem/ruby/tester/DetermGETXGenerator.hh +++ b/src/mem/ruby/tester/DetermGETXGenerator.hh @@ -1,58 +1,30 @@ - /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/DetermInvGenerator.cc b/src/mem/ruby/tester/DetermInvGenerator.cc index 73ef8b66a..bf1f3c3d1 100644 --- a/src/mem/ruby/tester/DetermInvGenerator.cc +++ b/src/mem/ruby/tester/DetermInvGenerator.cc @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/DetermInvGenerator.hh b/src/mem/ruby/tester/DetermInvGenerator.hh index fc334c0e3..521ac8710 100644 --- a/src/mem/ruby/tester/DetermInvGenerator.hh +++ b/src/mem/ruby/tester/DetermInvGenerator.hh @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ @@ -73,7 +46,6 @@ #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" #include "mem/protocol/DetermInvGeneratorStatus.hh" -#include "Address_Tester.hh" #include "mem/ruby/tester/SpecifiedGenerator.hh" class DeterministicDriver; diff --git a/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc b/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc index 47a4eda0d..8663fb90c 100644 --- a/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc +++ b/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh b/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh index e2034bde1..51d1638f6 100644 --- a/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh +++ b/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/DeterministicDriver.cc b/src/mem/ruby/tester/DeterministicDriver.cc index b6eb79497..e09f633b5 100644 --- a/src/mem/ruby/tester/DeterministicDriver.cc +++ b/src/mem/ruby/tester/DeterministicDriver.cc @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ @@ -169,8 +142,6 @@ bool DeterministicDriver::isStoreReady(NodeID node) bool DeterministicDriver::isStoreReady(NodeID node, Address addr) { - int addr_number = addr.getAddress()/DATA_BLOCK_BYTES; - return isAddrReady(node, m_store_vector, addr); } diff --git a/src/mem/ruby/tester/DeterministicDriver.hh b/src/mem/ruby/tester/DeterministicDriver.hh index 61c028f0c..7c77666be 100644 --- a/src/mem/ruby/tester/DeterministicDriver.hh +++ b/src/mem/ruby/tester/DeterministicDriver.hh @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/RaceyDriver.cc b/src/mem/ruby/tester/RaceyDriver.cc index 2cde0d432..57445d252 100644 --- a/src/mem/ruby/tester/RaceyDriver.cc +++ b/src/mem/ruby/tester/RaceyDriver.cc @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2005 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Ross Dickson, Pacia Harper, Milo Martin, Michael Marty, - Carl Mauer, Kevin Moore, Manoj Plakal, Daniel Sorin, Min Xu, and - Luke Yen. - - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/RaceyDriver.hh b/src/mem/ruby/tester/RaceyDriver.hh index d7a5c278d..e9b4e3425 100644 --- a/src/mem/ruby/tester/RaceyDriver.hh +++ b/src/mem/ruby/tester/RaceyDriver.hh @@ -1,58 +1,30 @@ - /* - Copyright (C) 1999-2005 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Ross Dickson, Pacia Harper, Milo Martin, Michael Marty, - Carl Mauer, Kevin Moore, Manoj Plakal, Daniel Sorin, Min Xu, and - Luke Yen. - - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/RaceyPseudoThread.cc b/src/mem/ruby/tester/RaceyPseudoThread.cc index 7d23b7286..79f6d1550 100644 --- a/src/mem/ruby/tester/RaceyPseudoThread.cc +++ b/src/mem/ruby/tester/RaceyPseudoThread.cc @@ -1,20 +1,30 @@ /* - * Copyright (c) 1999 by Mark Hill and David Wood for the Wisconsin - * Multifacet Project. ALL RIGHTS RESERVED. + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. * - * ##HEADER## + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. * - * This software is furnished under a license and may be used and - * copied only in accordance with the terms of such license and the - * inclusion of the above copyright notice. This software or any - * other copies thereof or any derivative works may not be provided or - * otherwise made available to any other persons. Title to and - * ownership of the software is retained by Mark Hill and David Wood. - * Any use of this software must include the above copyright notice. - * - * THIS SOFTWARE IS PROVIDED "AS IS". THE LICENSOR MAKES NO - * WARRANTIES ABOUT ITS CORRECTNESS OR PERFORMANCE. - * */ + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * Description: see RaceyPseudoThread.h @@ -262,7 +272,6 @@ void RaceyPseudoThread::store_sig(unsigned index, unsigned value) { m_read = false; m_value = value; uint8_t * write_data = new uint8_t[4]; - uint8_t * read_data = new uint8_t[4]; memcpy(write_data, &value, 4); @@ -273,8 +282,6 @@ void RaceyPseudoThread::store_sig(unsigned index, unsigned value) { // pc is zero, problem? int64_t request_id = libruby_issue_request(libruby_get_port_by_name(port_name), RubyRequest(sig(index), write_data, 4, 0, RubyRequestType_ST, RubyAccessMode_User)); - //int64_t request_id = libruby_issue_request(libruby_get_port_by_name(port_name), RubyRequest(sig(index), read_data, 4, 0, RubyRequestType_RMW_Read, RubyAccessMode_User)); - //int64_t request_id = libruby_issue_request(libruby_get_port_by_name(port_name), RubyRequest(sig(index), write_data, 4, 0, RubyRequestType_RMW_Write, RubyAccessMode_User)); ASSERT(m_driver.requests.find(request_id) == m_driver.requests.end()); @@ -296,7 +303,6 @@ void RaceyPseudoThread::store_m(unsigned index, unsigned value) { m_read = false; m_value = value; uint8_t * write_data = new uint8_t[4]; - uint8_t * read_data = new uint8_t[4]; memcpy(write_data, &value, 4); char name [] = "Sequencer_"; @@ -305,8 +311,6 @@ void RaceyPseudoThread::store_m(unsigned index, unsigned value) { // pc is zero, problem? int64_t request_id = libruby_issue_request(libruby_get_port_by_name(port_name), RubyRequest(m(index), write_data, 4, 0, RubyRequestType_ST, RubyAccessMode_User)); - //int64_t request_id = libruby_issue_request(libruby_get_port_by_name(port_name), RubyRequest(m(index), read_data, 4, 0, RubyRequestType_RMW_Read, RubyAccessMode_User)); - //int64_t request_id = libruby_issue_request(libruby_get_port_by_name(port_name), RubyRequest(m(index), write_data, 4, 0, RubyRequestType_RMW_Write, RubyAccessMode_User)); ASSERT(m_driver.requests.find(request_id) == m_driver.requests.end()); diff --git a/src/mem/ruby/tester/RaceyPseudoThread.hh b/src/mem/ruby/tester/RaceyPseudoThread.hh index 381cc1d87..103e42111 100644 --- a/src/mem/ruby/tester/RaceyPseudoThread.hh +++ b/src/mem/ruby/tester/RaceyPseudoThread.hh @@ -1,20 +1,30 @@ /* - * Copyright (c) 1999 by Mark Hill and David Wood for the Wisconsin - * Multifacet Project. ALL RIGHTS RESERVED. + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. * - * ##HEADER## + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. * - * This software is furnished under a license and may be used and - * copied only in accordance with the terms of such license and the - * inclusion of the above copyright notice. This software or any - * other copies thereof or any derivative works may not be provided or - * otherwise made available to any other persons. Title to and - * ownership of the software is retained by Mark Hill and David Wood. - * Any use of this software must include the above copyright notice. - * - * THIS SOFTWARE IS PROVIDED "AS IS". THE LICENSOR MAKES NO - * WARRANTIES ABOUT ITS CORRECTNESS OR PERFORMANCE. - * */ + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * Description: This implements a pseudo racey thread which drives ruby timing diff --git a/src/mem/ruby/tester/SConscript b/src/mem/ruby/tester/SConscript index 9c65ed794..cf3d60794 100644 --- a/src/mem/ruby/tester/SConscript +++ b/src/mem/ruby/tester/SConscript @@ -37,4 +37,9 @@ if not env['RUBY']: #Source('DetermInvGenerator.cc') #Source('DetermSeriesGETSGenerator.cc') #Source('DeterministicDriver.cc') -#ource('SpecifiedGenerator.cc') +#Source('SpecifiedGenerator.cc') +#Source('getopt.cc') +#Source('main.cc') +#Source('test_framework.cc') +#Source('RaceyDriver.cc') +#Source('RaceyPseudoThread.cc') diff --git a/src/mem/ruby/tester/SpecifiedGenerator.cc b/src/mem/ruby/tester/SpecifiedGenerator.cc index 15a1e046f..f82cb1533 100644 --- a/src/mem/ruby/tester/SpecifiedGenerator.cc +++ b/src/mem/ruby/tester/SpecifiedGenerator.cc @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2005 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Ross Dickson, Pacia Harper, Milo Martin, Michael Marty, - Carl Mauer, Kevin Moore, Manoj Plakal, Daniel Sorin, Min Xu, and - Luke Yen. - - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/SpecifiedGenerator.hh b/src/mem/ruby/tester/SpecifiedGenerator.hh index dffb699ea..3287a4055 100644 --- a/src/mem/ruby/tester/SpecifiedGenerator.hh +++ b/src/mem/ruby/tester/SpecifiedGenerator.hh @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2005 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Ross Dickson, Pacia Harper, Milo Martin, Michael Marty, - Carl Mauer, Kevin Moore, Manoj Plakal, Daniel Sorin, Min Xu, and - Luke Yen. - - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ +* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/Tester_Globals.hh b/src/mem/ruby/tester/Tester_Globals.hh index cecedeaad..a893d7d25 100644 --- a/src/mem/ruby/tester/Tester_Globals.hh +++ b/src/mem/ruby/tester/Tester_Globals.hh @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/getopt.cc b/src/mem/ruby/tester/getopt.cc new file mode 100644 index 000000000..f0fbe6473 --- /dev/null +++ b/src/mem/ruby/tester/getopt.cc @@ -0,0 +1,945 @@ +/* Getopt for GNU. + NOTE: getopt is now part of the C library, so if you don't know what + "Keep this file name-space clean" means, talk to roland@gnu.ai.mit.edu + before changing it! + + Copyright (C) 1987, 88, 89, 90, 91, 92, 93, 94, 95 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This tells Alpha OSF/1 not to define a getopt prototype in <stdio.h>. + Ditto for AIX 3.2 and <stdlib.h>. */ +#ifndef _NO_PROTO +#define _NO_PROTO +#endif + +#ifdef HAVE_CONFIG_H +#include <config.h> +#endif + +#if !defined (__STDC__) || !__STDC__ +/* This is a separate conditional since some stdc systems + reject `defined (const)'. */ +#ifndef const +#define const +#endif +#endif + +#include <stdio.h> + +/* Comment out all this code if we are using the GNU C Library, and are not + actually compiling the library itself. This code is part of the GNU C + Library, but also included in many other GNU distributions. Compiling + and linking in this code is a waste when using the GNU C library + (especially if it is a shared library). Rather than having every GNU + program understand `configure --with-gnu-libc' and omit the object files, + it is simpler to just do this in the source for each such file. */ + +#if defined (_LIBC) || !defined (__GNU_LIBRARY__) + + +/* This needs to come after some library #include + to get __GNU_LIBRARY__ defined. */ +#ifdef __GNU_LIBRARY__ +/* Don't include stdlib.h for non-GNU C libraries because some of them + contain conflicting prototypes for getopt. */ +#include <stdlib.h> +#endif /* GNU C library. */ + +/* This is for other GNU distributions with internationalized messages. + The GNU C Library itself does not yet support such messages. */ +#if HAVE_LIBINTL_H +# include <libintl.h> +#else +# define gettext(msgid) (msgid) +#endif + +/* This version of `getopt' appears to the caller like standard Unix `getopt' + but it behaves differently for the user, since it allows the user + to intersperse the options with the other arguments. + + As `getopt' works, it permutes the elements of ARGV so that, + when it is done, all the options precede everything else. Thus + all application programs are extended to handle flexible argument order. + + Setting the environment variable POSIXLY_CORRECT disables permutation. + Then the behavior is completely standard. + + GNU application programs can use a third alternative mode in which + they can distinguish the relative order of options and other arguments. */ + +#include "mem/ruby/tester/getopt.hh" + +/* For communication from `getopt' to the caller. + When `getopt' finds an option that takes an argument, + the argument value is returned here. + Also, when `ordering' is RETURN_IN_ORDER, + each non-option ARGV-element is returned here. */ + +char *optarg = NULL; + +/* Index in ARGV of the next element to be scanned. + This is used for communication to and from the caller + and for communication between successive calls to `getopt'. + + On entry to `getopt', zero means this is the first call; initialize. + + When `getopt' returns EOF, this is the index of the first of the + non-option elements that the caller should itself scan. + + Otherwise, `optind' communicates from one call to the next + how much of ARGV has been scanned so far. */ + +/* XXX 1003.2 says this must be 1 before any call. */ +int optind = 0; + +/* The next char to be scanned in the option-element + in which the last option character we returned was found. + This allows us to pick up the scan where we left off. + + If this is zero, or a null string, it means resume the scan + by advancing to the next ARGV-element. */ + +static char *nextchar; + +/* Callers store zero here to inhibit the error message + for unrecognized options. */ + +int opterr = 1; + +/* Set to an option character which was unrecognized. + This must be initialized on some systems to avoid linking in the + system's own getopt implementation. */ + +int optopt = '?'; + +/* Describe how to deal with options that follow non-option ARGV-elements. + + If the caller did not specify anything, + the default is REQUIRE_ORDER if the environment variable + POSIXLY_CORRECT is defined, PERMUTE otherwise. + + REQUIRE_ORDER means don't recognize them as options; + stop option processing when the first non-option is seen. + This is what Unix does. + This mode of operation is selected by either setting the environment + variable POSIXLY_CORRECT, or using `+' as the first character + of the list of option characters. + + PERMUTE is the default. We permute the contents of ARGV as we scan, + so that eventually all the non-options are at the end. This allows options + to be given in any order, even with programs that were not written to + expect this. + + RETURN_IN_ORDER is an option available to programs that were written + to expect options and other ARGV-elements in any order and that care about + the ordering of the two. We describe each non-option ARGV-element + as if it were the argument of an option with character code 1. + Using `-' as the first character of the list of option characters + selects this mode of operation. + + The special argument `--' forces an end of option-scanning regardless + of the value of `ordering'. In the case of RETURN_IN_ORDER, only + `--' can cause `getopt' to return EOF with `optind' != ARGC. */ + +static enum +{ + REQUIRE_ORDER, PERMUTE, RETURN_IN_ORDER +} ordering; + +/* Value of POSIXLY_CORRECT environment variable. */ +static char *posixly_correct; + +#ifdef __GNU_LIBRARY__ +/* We want to avoid inclusion of string.h with non-GNU libraries + because there are many ways it can cause trouble. + On some systems, it contains special magic macros that don't work + in GCC. */ +#include <string.h> +#define my_index strchr +#else + +/* Avoid depending on library functions or files + whose names are inconsistent. */ + +#include <stdlib.h> +#include <string.h> +//char *getenv(); + +static char * +my_index ( + const char *str, + int chr ) +{ + while (*str) + { + if (*str == chr) + return (char *) str; + str++; + } + return 0; +} + +/* If using GCC, we can safely declare strlen this way. + If not using GCC, it is ok not to declare it. */ +#ifdef __GNUC__ +/* Note that Motorola Delta 68k R3V7 comes with GCC but not stddef.h. + That was relevant to code that was here before. */ +#if !defined (__STDC__) || !__STDC__ +/* gcc with -traditional declares the built-in strlen to return int, + and has done so at least since version 2.4.5. -- rms. */ +extern int strlen (const char *); +#endif /* not __STDC__ */ +#endif /* __GNUC__ */ + +#endif /* not __GNU_LIBRARY__ */ + +/* Handle permutation of arguments. */ + +/* Describe the part of ARGV that contains non-options that have + been skipped. `first_nonopt' is the index in ARGV of the first of them; + `last_nonopt' is the index after the last of them. */ + +static int first_nonopt; +static int last_nonopt; + +/* Exchange two adjacent subsequences of ARGV. + One subsequence is elements [first_nonopt,last_nonopt) + which contains all the non-options that have been skipped so far. + The other is elements [last_nonopt,optind), which contains all + the options processed since those non-options were skipped. + + `first_nonopt' and `last_nonopt' are relocated so that they describe + the new indices of the non-options in ARGV after they are moved. */ + +static void +exchange ( + char **argv ) +{ + int bottom = first_nonopt; + int middle = last_nonopt; + int top = optind; + char *tem; + + /* Exchange the shorter segment with the far end of the longer segment. + That puts the shorter segment into the right place. + It leaves the longer segment in the right place overall, + but it consists of two parts that need to be swapped next. */ + + while (top > middle && middle > bottom) + { + if (top - middle > middle - bottom) + { + /* Bottom segment is the short one. */ + int len = middle - bottom; + register int i; + + /* Swap it with the top part of the top segment. */ + for (i = 0; i < len; i++) + { + tem = argv[bottom + i]; + argv[bottom + i] = argv[top - (middle - bottom) + i]; + argv[top - (middle - bottom) + i] = tem; + } + /* Exclude the moved bottom segment from further swapping. */ + top -= len; + } + else + { + /* Top segment is the short one. */ + int len = top - middle; + register int i; + + /* Swap it with the bottom part of the bottom segment. */ + for (i = 0; i < len; i++) + { + tem = argv[bottom + i]; + argv[bottom + i] = argv[middle + i]; + argv[middle + i] = tem; + } + /* Exclude the moved top segment from further swapping. */ + bottom += len; + } + } + + /* Update records for the slots the non-options now occupy. */ + + first_nonopt += (optind - last_nonopt); + last_nonopt = optind; +} + +/* Initialize the internal data when the first call is made. */ + +static const char * +_getopt_initialize ( + const char *optstring ) +{ + /* Start processing options with ARGV-element 1 (since ARGV-element 0 + is the program name); the sequence of previously skipped + non-option ARGV-elements is empty. */ + + first_nonopt = last_nonopt = optind = 1; + + nextchar = NULL; + + posixly_correct = getenv ("POSIXLY_CORRECT"); + + /* Determine how to handle the ordering of options and nonoptions. */ + + if (optstring[0] == '-') + { + ordering = RETURN_IN_ORDER; + ++optstring; + } + else if (optstring[0] == '+') + { + ordering = REQUIRE_ORDER; + ++optstring; + } + else if (posixly_correct != NULL) + ordering = REQUIRE_ORDER; + else + ordering = PERMUTE; + + return optstring; +} + +/* Scan elements of ARGV (whose length is ARGC) for option characters + given in OPTSTRING. + + If an element of ARGV starts with '-', and is not exactly "-" or "--", + then it is an option element. The characters of this element + (aside from the initial '-') are option characters. If `getopt' + is called repeatedly, it returns successively each of the option characters + from each of the option elements. + + If `getopt' finds another option character, it returns that character, + updating `optind' and `nextchar' so that the next call to `getopt' can + resume the scan with the following option character or ARGV-element. + + If there are no more option characters, `getopt' returns `EOF'. + Then `optind' is the index in ARGV of the first ARGV-element + that is not an option. (The ARGV-elements have been permuted + so that those that are not options now come last.) + + OPTSTRING is a string containing the legitimate option characters. + If an option character is seen that is not listed in OPTSTRING, + return '?' after printing an error message. If you set `opterr' to + zero, the error message is suppressed but we still return '?'. + + If a char in OPTSTRING is followed by a colon, that means it wants an arg, + so the following text in the same ARGV-element, or the text of the following + ARGV-element, is returned in `optarg'. Two colons mean an option that + wants an optional arg; if there is text in the current ARGV-element, + it is returned in `optarg', otherwise `optarg' is set to zero. + + If OPTSTRING starts with `-' or `+', it requests different methods of + handling the non-option ARGV-elements. + See the comments about RETURN_IN_ORDER and REQUIRE_ORDER, above. + + Long-named options begin with `--' instead of `-'. + Their names may be abbreviated as long as the abbreviation is unique + or is an exact match for some defined option. If they have an + argument, it follows the option name in the same ARGV-element, separated + from the option name by a `=', or else the in next ARGV-element. + When `getopt' finds a long-named option, it returns 0 if that option's + `flag' field is nonzero, the value of the option's `val' field + if the `flag' field is zero. + + The elements of ARGV aren't really const, because we permute them. + But we pretend they're const in the prototype to be compatible + with other systems. + + LONGOPTS is a vector of `struct option' terminated by an + element containing a name which is zero. + + LONGIND returns the index in LONGOPT of the long-named option found. + It is only valid when a long-named option has been found by the most + recent call. + + If LONG_ONLY is nonzero, '-' as well as '--' can introduce + long-named options. */ + +int +_getopt_internal ( + int argc, + char *const *argv, + const char *optstring, + const struct option *longopts, + int *longind, + int long_only ) +{ + optarg = NULL; + + if (optind == 0) + { + optstring = _getopt_initialize (optstring); + optind = 1; /* Don't scan ARGV[0], the program name. */ + } + + if (nextchar == NULL || *nextchar == '\0') + { + /* Advance to the next ARGV-element. */ + + if (ordering == PERMUTE) + { + /* If we have just processed some options following some non-options, + exchange them so that the options come first. */ + + if (first_nonopt != last_nonopt && last_nonopt != optind) + exchange ((char **) argv); + else if (last_nonopt != optind) + first_nonopt = optind; + + /* Skip any additional non-options + and extend the range of non-options previously skipped. */ + + while (optind < argc + && (argv[optind][0] != '-' || argv[optind][1] == '\0')) + optind++; + last_nonopt = optind; + } + + /* The special ARGV-element `--' means premature end of options. + Skip it like a null option, + then exchange with previous non-options as if it were an option, + then skip everything else like a non-option. */ + + if (optind != argc && !strcmp (argv[optind], "--")) + { + optind++; + + if (first_nonopt != last_nonopt && last_nonopt != optind) + exchange ((char **) argv); + else if (first_nonopt == last_nonopt) + first_nonopt = optind; + last_nonopt = argc; + + optind = argc; + } + + /* If we have done all the ARGV-elements, stop the scan + and back over any non-options that we skipped and permuted. */ + + if (optind == argc) + { + /* Set the next-arg-index to point at the non-options + that we previously skipped, so the caller will digest them. */ + if (first_nonopt != last_nonopt) + optind = first_nonopt; + return EOF; + } + + /* If we have come to a non-option and did not permute it, + either stop the scan or describe it to the caller and pass it by. */ + + if ((argv[optind][0] != '-' || argv[optind][1] == '\0')) + { + if (ordering == REQUIRE_ORDER) + return EOF; + optarg = argv[optind++]; + return 1; + } + + /* We have found another option-ARGV-element. + Skip the initial punctuation. */ + + nextchar = (argv[optind] + 1 + + (longopts != NULL && argv[optind][1] == '-')); + } + + /* Decode the current option-ARGV-element. */ + + /* Check whether the ARGV-element is a long option. + + If long_only and the ARGV-element has the form "-f", where f is + a valid short option, don't consider it an abbreviated form of + a long option that starts with f. Otherwise there would be no + way to give the -f short option. + + On the other hand, if there's a long option "fubar" and + the ARGV-element is "-fu", do consider that an abbreviation of + the long option, just like "--fu", and not "-f" with arg "u". + + This distinction seems to be the most useful approach. */ + + if (longopts != NULL + && (argv[optind][1] == '-' + || (long_only && (argv[optind][2] || !my_index (optstring, argv[optind][1]))))) + { + char *nameend; + const struct option *p; + const struct option *pfound = NULL; + int exact = 0; + int ambig = 0; + int indfound = 0; + int option_index; + + for (nameend = nextchar; *nameend && *nameend != '='; nameend++) + /* Do nothing. */ ; + + /* Test all long options for either exact match + or abbreviated matches. */ + for (p = longopts, option_index = 0; p->name; p++, option_index++) + if (!strncmp (p->name, nextchar, nameend - nextchar)) + { + if (nameend - nextchar == int(strlen (p->name))) + { + /* Exact match found. */ + pfound = p; + indfound = option_index; + exact = 1; + break; + } + else if (pfound == NULL) + { + /* First nonexact match found. */ + pfound = p; + indfound = option_index; + } + else + /* Second or later nonexact match found. */ + ambig = 1; + } + + if (ambig && !exact) + { + if (opterr) + fprintf (stderr, gettext ("%s: option `%s' is ambiguous\n"), + argv[0], argv[optind]); + nextchar += strlen (nextchar); + optind++; + return '?'; + } + + if (pfound != NULL) + { + option_index = indfound; + optind++; + if (*nameend) + { + /* Don't test has_arg with >, because some C compilers don't + allow it to be used on enums. */ + if (pfound->has_arg) + optarg = nameend + 1; + else + { + if (opterr) + if (argv[optind - 1][1] == '-') + /* --option */ + fprintf (stderr, + gettext ("%s: option `--%s' doesn't allow an argument\n"), + argv[0], pfound->name); + else + /* +option or -option */ + fprintf (stderr, + gettext ("%s: option `%c%s' doesn't allow an argument\n"), + argv[0], argv[optind - 1][0], pfound->name); + + nextchar += strlen (nextchar); + return '?'; + } + } + else if (pfound->has_arg == 1) + { + if (optind < argc) + optarg = argv[optind++]; + else + { + if (opterr) + fprintf (stderr, + gettext ("%s: option `%s' requires an argument\n"), + argv[0], argv[optind - 1]); + nextchar += strlen (nextchar); + return optstring[0] == ':' ? ':' : '?'; + } + } + nextchar += strlen (nextchar); + if (longind != NULL) + *longind = option_index; + if (pfound->flag) + { + *(pfound->flag) = pfound->val; + return 0; + } + return pfound->val; + } + + /* Can't find it as a long option. If this is not getopt_long_only, + or the option starts with '--' or is not a valid short + option, then it's an error. + Otherwise interpret it as a short option. */ + if (!long_only || argv[optind][1] == '-' + || my_index (optstring, *nextchar) == NULL) + { + if (opterr) + { + if (argv[optind][1] == '-') + /* --option */ + fprintf (stderr, gettext ("%s: unrecognized option `--%s'\n"), + argv[0], nextchar); + else + /* +option or -option */ + fprintf (stderr, gettext ("%s: unrecognized option `%c%s'\n"), + argv[0], argv[optind][0], nextchar); + } + nextchar = (char *) ""; + optind++; + return '?'; + } + } + + /* Look at and handle the next short option-character. */ + + { + char c = *nextchar++; + char *temp = my_index (optstring, c); + + /* Increment `optind' when we start to process its last character. */ + if (*nextchar == '\0') + ++optind; + + if (temp == NULL || c == ':') + { + if (opterr) + { + if (posixly_correct) + /* 1003.2 specifies the format of this message. */ + fprintf (stderr, gettext ("%s: illegal option -- %c\n"), + argv[0], c); + else + fprintf (stderr, gettext ("%s: invalid option -- %c\n"), + argv[0], c); + } + optopt = c; + return '?'; + } + if (temp[1] == ':') + { + if (temp[2] == ':') + { + /* This is an option that accepts an argument optionally. */ + if (*nextchar != '\0') + { + optarg = nextchar; + optind++; + } + else + optarg = NULL; + nextchar = NULL; + } + else + { + /* This is an option that requires an argument. */ + if (*nextchar != '\0') + { + optarg = nextchar; + /* If we end this ARGV-element by taking the rest as an arg, + we must advance to the next element now. */ + optind++; + } + else if (optind == argc) + { + if (opterr) + { + /* 1003.2 specifies the format of this message. */ + fprintf (stderr, + gettext ("%s: option requires an argument -- %c\n"), + argv[0], c); + } + optopt = c; + if (optstring[0] == ':') + c = ':'; + else + c = '?'; + } + else + /* We already incremented `optind' once; + increment it again when taking next ARGV-elt as argument. */ + optarg = argv[optind++]; + nextchar = NULL; + } + } + return c; + } +} + +int +getopt_gnu ( + int argc, + char *const *argv, + const char *optstring ) +{ + return _getopt_internal (argc, argv, optstring, + (const struct option *) 0, + (int *) 0, + 0); +} + +#endif /* _LIBC or not __GNU_LIBRARY__. */ + +#ifdef TEST + +/* Compile with -DTEST to make an executable for use in testing + the above definition of `getopt'. */ + +int +main ( + int argc, + char **argv ) +{ + int c; + int digit_optind = 0; + + while (1) + { + int this_option_optind = optind ? optind : 1; + + c = getopt_gnu (argc, argv, "abc:d:0123456789"); + if (c == EOF) + break; + + switch (c) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (digit_optind != 0 && digit_optind != this_option_optind) + printf ("digits occur in two different argv-elements.\n"); + digit_optind = this_option_optind; + printf ("option %c\n", c); + break; + + case 'a': + printf ("option a\n"); + break; + + case 'b': + printf ("option b\n"); + break; + + case 'c': + printf ("option c with value `%s'\n", optarg); + break; + + case '?': + break; + + default: + printf ("?? getopt returned character code 0%o ??\n", c); + } + } + + if (optind < argc) + { + printf ("non-option ARGV-elements: "); + while (optind < argc) + printf ("%s ", argv[optind++]); + printf ("\n"); + } + + exit (0); +} + +#endif /* TEST */ + +/* getopt_long and getopt_long_only entry points for GNU getopt. + Copyright (C) 1987, 88, 89, 90, 91, 92, 1993, 1994 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifdef HAVE_CONFIG_H +#include <config.h> +#endif + +#include "mem/ruby/tester/getopt.hh" + +#if !defined (__STDC__) || !__STDC__ +/* This is a separate conditional since some stdc systems + reject `defined (const)'. */ +#ifndef const +#define const +#endif +#endif + +#include <stdio.h> + +/* Comment out all this code if we are using the GNU C Library, and are not + actually compiling the library itself. This code is part of the GNU C + Library, but also included in many other GNU distributions. Compiling + and linking in this code is a waste when using the GNU C library + (especially if it is a shared library). Rather than having every GNU + program understand `configure --with-gnu-libc' and omit the object files, + it is simpler to just do this in the source for each such file. */ + +#if defined (_LIBC) || !defined (__GNU_LIBRARY__) + + +/* This needs to come after some library #include + to get __GNU_LIBRARY__ defined. */ +#ifdef __GNU_LIBRARY__ +#include <stdlib.h> +#else + +#endif + +#ifndef NULL +#define NULL 0 +#endif + +int +getopt_long ( + int argc, + char *const *argv, + const char *options, + const struct option *long_options, + int *opt_index ) +{ + return _getopt_internal (argc, argv, options, long_options, opt_index, 0); +} + +/* Like getopt_long, but '-' as well as '--' can indicate a long option. + If an option that starts with '-' (not '--') doesn't match a long option, + but does match a short option, it is parsed as a short option + instead. */ + +int +getopt_long_only ( + int argc, + char *const *argv, + const char *options, + const struct option *long_options, + int *opt_index ) +{ + return _getopt_internal (argc, argv, options, long_options, opt_index, 1); +} + + +#endif /* _LIBC or not __GNU_LIBRARY__. */ + +#ifdef TEST + +#include <stdio.h> + +int +main (argc, argv) + int argc; + char **argv; +{ + int c; + int digit_optind = 0; + + while (1) + { + int this_option_optind = optind ? optind : 1; + int option_index = 0; + static struct option long_options[] = + { + {"add", 1, 0, 0}, + {"append", 0, 0, 0}, + {"delete", 1, 0, 0}, + {"verbose", 0, 0, 0}, + {"create", 0, 0, 0}, + {"file", 1, 0, 0}, + {0, 0, 0, 0} + }; + + c = getopt_long (argc, argv, "abc:d:0123456789", + long_options, &option_index); + if (c == EOF) + break; + + switch (c) + { + case 0: + printf ("option %s", long_options[option_index].name); + if (optarg) + printf (" with arg %s", optarg); + printf ("\n"); + break; + + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (digit_optind != 0 && digit_optind != this_option_optind) + printf ("digits occur in two different argv-elements.\n"); + digit_optind = this_option_optind; + printf ("option %c\n", c); + break; + + case 'a': + printf ("option a\n"); + break; + + case 'b': + printf ("option b\n"); + break; + + case 'c': + printf ("option c with value `%s'\n", optarg); + break; + + case 'd': + printf ("option d with value `%s'\n", optarg); + break; + + case '?': + break; + + default: + printf ("?? getopt returned character code 0%o ??\n", c); + } + } + + if (optind < argc) + { + printf ("non-option ARGV-elements: "); + while (optind < argc) + printf ("%s ", argv[optind++]); + printf ("\n"); + } + + exit (0); +} + +#endif /* TEST */ diff --git a/src/mem/ruby/tester/getopt.hh b/src/mem/ruby/tester/getopt.hh new file mode 100644 index 000000000..621b449f9 --- /dev/null +++ b/src/mem/ruby/tester/getopt.hh @@ -0,0 +1,129 @@ +/* Declarations for getopt. + Copyright (C) 1989, 90, 91, 92, 93, 94 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef _GETOPT_H +#define _GETOPT_H 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* For communication from `getopt' to the caller. + When `getopt' finds an option that takes an argument, + the argument value is returned here. + Also, when `ordering' is RETURN_IN_ORDER, + each non-option ARGV-element is returned here. */ + +extern char *optarg; + +/* Index in ARGV of the next element to be scanned. + This is used for communication to and from the caller + and for communication between successive calls to `getopt'. + + On entry to `getopt', zero means this is the first call; initialize. + + When `getopt' returns EOF, this is the index of the first of the + non-option elements that the caller should itself scan. + + Otherwise, `optind' communicates from one call to the next + how much of ARGV has been scanned so far. */ + +extern int optind; + +/* Callers store zero here to inhibit the error message `getopt' prints + for unrecognized options. */ + +extern int opterr; + +/* Set to an option character which was unrecognized. */ + +extern int optopt; + +/* Describe the long-named options requested by the application. + The LONG_OPTIONS argument to getopt_long or getopt_long_only is a vector + of `struct option' terminated by an element containing a name which is + zero. + + The field `has_arg' is: + no_argument (or 0) if the option does not take an argument, + required_argument (or 1) if the option requires an argument, + optional_argument (or 2) if the option takes an optional argument. + + If the field `flag' is not NULL, it points to a variable that is set + to the value given in the field `val' when the option is found, but + left unchanged if the option is not found. + + To have a long-named option do something other than set an `int' to + a compiled-in constant, such as set a value from `optarg', set the + option's `flag' field to zero and its `val' field to a nonzero + value (the equivalent single-letter option character, if there is + one). For long options that have a zero `flag' field, `getopt' + returns the contents of the `val' field. */ + +struct option +{ +#if defined (__STDC__) && __STDC__ + const char *name; +#else + char *name; +#endif + /* has_arg can't be an enum because some compilers complain about + type mismatches in all the code that assumes it is an int. */ + int has_arg; + int *flag; + int val; +}; + +/* Names for the values of the `has_arg' field of `struct option'. */ + +#define no_argument 0 +#define required_argument 1 +#define optional_argument 2 + +#if defined (__STDC__) && __STDC__ +#ifdef __GNU_LIBRARY__ +/* Many other libraries have conflicting prototypes for getopt, with + differences in the consts, in stdlib.h. To avoid compilation + errors, only prototype getopt for the GNU C library. */ +extern int getopt_gnu (int argc, char *const *argv, const char *shortopts); +#else /* not __GNU_LIBRARY__ */ +extern int getopt_gnu (); +#endif /* __GNU_LIBRARY__ */ +extern int getopt_long (int argc, char *const *argv, const char *shortopts, + const struct option *longopts, int *longind); +extern int getopt_long_only (int argc, char *const *argv, + const char *shortopts, + const struct option *longopts, int *longind); + +/* Internal only. Users should not call this directly. */ +extern int _getopt_internal (int argc, char *const *argv, + const char *shortopts, + const struct option *longopts, int *longind, + int long_only); +#else /* not __STDC__ */ +extern int getopt_gnu (); +extern int getopt_long (); +extern int getopt_long_only (); + +extern int _getopt_internal (); +#endif /* __STDC__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GETOPT_H */ diff --git a/src/mem/ruby/tester/main.cc b/src/mem/ruby/tester/main.cc index a37827521..849206de9 100644 --- a/src/mem/ruby/tester/main.cc +++ b/src/mem/ruby/tester/main.cc @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/main.hh b/src/mem/ruby/tester/main.hh index a5fa2b995..a6a0d73b6 100644 --- a/src/mem/ruby/tester/main.hh +++ b/src/mem/ruby/tester/main.hh @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/ruby/tester/test_framework.cc b/src/mem/ruby/tester/test_framework.cc index cc11abe8a..99d11887f 100644 --- a/src/mem/ruby/tester/test_framework.cc +++ b/src/mem/ruby/tester/test_framework.cc @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ @@ -312,7 +285,6 @@ static void parseOptions(int argc, char **argv) char c; /* Parse command line options. */ - bool error; while ((c = getopt_long (argc, argv, short_options.c_str(), long_options, (int *) 0)) != EOF) { switch (c) { case 0: diff --git a/src/mem/ruby/tester/test_framework.hh b/src/mem/ruby/tester/test_framework.hh index afdd146a9..625abe459 100644 --- a/src/mem/ruby/tester/test_framework.hh +++ b/src/mem/ruby/tester/test_framework.hh @@ -1,58 +1,31 @@ /* - Copyright (C) 1999-2008 by Mark D. Hill and David A. Wood for the - Wisconsin Multifacet Project. Contact: gems@cs.wisc.edu - http://www.cs.wisc.edu/gems/ - - -------------------------------------------------------------------- - - This file is part of the Ruby Multiprocessor Memory System Simulator, - a component of the Multifacet GEMS (General Execution-driven - Multiprocessor Simulator) software toolset originally developed at - the University of Wisconsin-Madison. - - Ruby was originally developed primarily by Milo Martin and Daniel - Sorin with contributions from Ross Dickson, Carl Mauer, and Manoj - Plakal. - - Substantial further development of Multifacet GEMS at the - University of Wisconsin was performed by Alaa Alameldeen, Brad - Beckmann, Jayaram Bobba, Ross Dickson, Dan Gibson, Pacia Harper, - Derek Hower, Milo Martin, Michael Marty, Carl Mauer, Michelle Moravan, - Kevin Moore, Andrew Phelps, Manoj Plakal, Daniel Sorin, Haris Volos, - Min Xu, and Luke Yen. - -------------------------------------------------------------------- - - If your use of this software contributes to a published paper, we - request that you (1) cite our summary paper that appears on our - website (http://www.cs.wisc.edu/gems/) and (2) e-mail a citation - for your published paper to gems@cs.wisc.edu. - - If you redistribute derivatives of this software, we request that - you notify us and either (1) ask people to register with us at our - website (http://www.cs.wisc.edu/gems/) or (2) collect registration - information and periodically send it to us. - - -------------------------------------------------------------------- - - Multifacet GEMS is free software; you can redistribute it and/or - modify it under the terms of version 2 of the GNU General Public - License as published by the Free Software Foundation. - - Multifacet GEMS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with the Multifacet GEMS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307, USA - - The GNU General Public License is contained in the file LICENSE. - -### END HEADER ### -*/ + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ /* * $Id$ diff --git a/src/mem/slicc/symbols/StateMachine.cc b/src/mem/slicc/symbols/StateMachine.cc index e042f9aa0..4a9ee3714 100644 --- a/src/mem/slicc/symbols/StateMachine.cc +++ b/src/mem/slicc/symbols/StateMachine.cc @@ -832,17 +832,21 @@ void StateMachine::printCWakeup(ostream& out, string component) locked_read_request = addr; \n \ } \n \ else if (addr == locked_read_request) { \n \ - assert (servicing_atomic); \n \ - //servicing_atomic = m_version; \n \ + ; // do nothing \n\ } \n \ - else { \n \ - postpone = true; \n \ - g_eventQueue_ptr->scheduleEvent(this, 1); \n \ + else { \n \ + assert(0); // should never be here if servicing one request at a time \n\ } \n \ } \n \ else if (addr != locked_read_request) { \n \ - postpone = true; \n \ - g_eventQueue_ptr->scheduleEvent(this, 1); \n \ + // this is probably caused by shift optimizations \n \ + locked_read_request = addr; \n\ + } \n \ + } \n \ + else { \n \ + if (locked_read_request != Address(-1)) { \n \ + locked_read_request = Address(-1); \n \ + servicing_atomic = false; \n \ } \n \ } \n \ if (!postpone) { \n \ diff --git a/src/sim/process.cc b/src/sim/process.cc index c12101069..55bd2f209 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -748,7 +748,9 @@ LiveProcess::create(LiveProcessParams * params) case ObjectFile::Linux: process = new ArmLinuxProcess(params, objFile); break; - + case ObjectFile::LinuxArmOABI: + fatal("M5 does not support ARM OABI binaries. Please recompile with an" + " EABI compiler."); default: fatal("Unknown/unsupported operating system."); } diff --git a/src/sim/process.hh b/src/sim/process.hh index 0d5421dcd..05a48071a 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -295,6 +295,10 @@ class LiveProcess : public Process M5_AT_CLKTCK = 17, M5_AT_SECURE = 23, + M5_BASE_PLATFORM = 24, + M5_AT_RANDOM = 25, + + M5_AT_EXECFN = 31, M5_AT_VECTOR_SIZE = 44 }; |