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-rw-r--r--src/arch/sparc/asi.cc6
-rw-r--r--src/arch/sparc/asi.hh1
-rw-r--r--src/arch/sparc/tlb.cc3
3 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/sparc/asi.cc b/src/arch/sparc/asi.cc
index d8cd84af5..254635bff 100644
--- a/src/arch/sparc/asi.cc
+++ b/src/arch/sparc/asi.cc
@@ -247,7 +247,8 @@ namespace SparcISA
bool AsiIsCmt(ASI asi)
{
return
- (asi == ASI_CMT_PER_STRAND);
+ (asi == ASI_CMT_PER_STRAND) ||
+ (asi == ASI_CMT_SHARED);
}
bool AsiIsQueue(ASI asi)
@@ -295,7 +296,8 @@ namespace SparcISA
bool AsiIsReg(ASI asi)
{
return AsiIsMmu(asi) || AsiIsScratchPad(asi) ||
- AsiIsSparcError(asi) || AsiIsInterrupt(asi);
+ AsiIsSparcError(asi) || AsiIsInterrupt(asi)
+ || AsiIsCmt(asi);
}
bool AsiIsSparcError(ASI asi)
diff --git a/src/arch/sparc/asi.hh b/src/arch/sparc/asi.hh
index 166c3867e..eba2d518f 100644
--- a/src/arch/sparc/asi.hh
+++ b/src/arch/sparc/asi.hh
@@ -115,6 +115,7 @@ namespace SparcISA
ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E,
ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F,
ASI_STREAM_MA = 0x40,
+ ASI_CMT_SHARED = 0x41,
//0x41 implementation dependent
ASI_SPARC_BIST_CONTROL = 0x42,
ASI_INST_MASK_REG = 0x42,
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index c39969769..09266fd6e 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -693,6 +693,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
if (AsiIsPartialStore(asi))
panic("Partial Store ASIs not supported\n");
+ if (AsiIsCmt(asi))
+ panic("Cmt ASI registers not implmented\n");
+
if (AsiIsInterrupt(asi))
goto handleIntRegAccess;
if (AsiIsMmu(asi))