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-rw-r--r--src/arch/alpha/vtophys.cc4
-rw-r--r--src/cpu/simple/atomic.cc2
-rw-r--r--src/cpu/simple/timing.cc3
-rw-r--r--src/mem/tport.cc36
-rw-r--r--src/python/m5/SimObject.py7
-rw-r--r--src/python/m5/__init__.py7
-rw-r--r--src/sim/main.cc12
-rw-r--r--src/sim/sim_object.hh7
-rw-r--r--src/sim/system.hh14
9 files changed, 45 insertions, 47 deletions
diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc
index f7fd92c15..fd8f781e4 100644
--- a/src/arch/alpha/vtophys.cc
+++ b/src/arch/alpha/vtophys.cc
@@ -141,12 +141,12 @@ void
AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
{
int len = 0;
+ char *start = dst;
VirtualPort *vp = tc->getVirtPort(tc);
do {
vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
- len++;
- } while (len < maxlen && dst[len] != 0 );
+ } while (len < maxlen && start[len++] != 0 );
tc->delVirtPort(vp);
dst[len] = 0;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 490be20ae..fe421ae6c 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -182,9 +182,9 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
void
AtomicSimpleCPU::resume()
{
- assert(system->getMemoryMode() == System::Atomic);
changeState(SimObject::Running);
if (thread->status() == ThreadContext::Active) {
+ assert(system->getMemoryMode() == System::Atomic);
if (!tickEvent.scheduled())
tickEvent.schedule(curTick);
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 33f673cbc..ad5c0e5d6 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -147,6 +147,8 @@ void
TimingSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
+ assert(system->getMemoryMode() == System::Timing);
+
// Delete the old event if it existed.
if (fetchEvent) {
if (fetchEvent->scheduled())
@@ -160,7 +162,6 @@ TimingSimpleCPU::resume()
fetchEvent->schedule(curTick);
}
- assert(system->getMemoryMode() == System::Timing);
changeState(SimObject::Running);
previousTick = curTick;
}
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 50aab31c4..21907c0ca 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -36,41 +36,19 @@ SimpleTimingPort::recvFunctional(Packet *pkt)
//First check queued events
std::list<Packet *>::iterator i = transmitList.begin();
std::list<Packet *>::iterator end = transmitList.end();
- for (; i != end; ++i) {
+ bool cont = true;
+
+ while (i != end && cont) {
Packet * target = *i;
// If the target contains data, and it overlaps the
// probed request, need to update data
- if (target->intersect(pkt)) {
- uint8_t* pkt_data;
- uint8_t* write_data;
- int data_size;
- if (target->getAddr() < pkt->getAddr()) {
- int offset = pkt->getAddr() - target->getAddr();
- pkt_data = pkt->getPtr<uint8_t>();
- write_data = target->getPtr<uint8_t>() + offset;
- data_size = target->getSize() - offset;
- assert(data_size > 0);
- if (data_size > pkt->getSize())
- data_size = pkt->getSize();
- } else {
- int offset = target->getAddr() - pkt->getAddr();
- pkt_data = pkt->getPtr<uint8_t>() + offset;
- write_data = target->getPtr<uint8_t>();
- data_size = pkt->getSize() - offset;
- assert(data_size > pkt->getSize());
- if (data_size > target->getSize())
- data_size = target->getSize();
- }
+ if (target->intersect(pkt))
+ fixPacket(pkt, target);
- if (pkt->isWrite()) {
- memcpy(pkt_data, write_data, data_size);
- } else {
- memcpy(write_data, pkt_data, data_size);
- }
- }
}
//Then just do an atomic access and throw away the returned latency
- recvAtomic(pkt);
+ if (cont)
+ recvAtomic(pkt);
}
bool
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index a0d66e643..716f584b0 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -726,7 +726,12 @@ class SimObject(object):
child.resume()
def changeTiming(self, mode):
- if isinstance(self, System):
+ if isinstance(self, m5.objects.System):
+ # i don't know if there's a better way to do this - calling
+ # setMemoryMode directly from self._ccObject results in calling
+ # SimObject::setMemoryMode, not the System::setMemoryMode
+## system_ptr = cc_main.convertToSystemPtr(self._ccObject)
+## system_ptr.setMemoryMode(mode)
self._ccObject.setMemoryMode(mode)
for child in self._children.itervalues():
child.changeTiming(mode)
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index 5717b49b6..03e0508fb 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -144,7 +144,7 @@ def restoreCheckpoint(root, dir):
resume(root)
def changeToAtomic(system):
- if not isinstance(system, objects.Root) and not isinstance(system, System):
+ if not isinstance(system, objects.Root) and not isinstance(system, objects.System):
raise TypeError, "Object is not a root or system object. Checkpoint must be "
"called on a root object."
doDrain(system)
@@ -153,7 +153,7 @@ def changeToAtomic(system):
resume(system)
def changeToTiming(system):
- if not isinstance(system, objects.Root) and not isinstance(system, System):
+ if not isinstance(system, objects.Root) and not isinstance(system, objects.System):
raise TypeError, "Object is not a root or system object. Checkpoint must be "
"called on a root object."
doDrain(system)
@@ -162,6 +162,7 @@ def changeToTiming(system):
resume(system)
def switchCpus(cpuList):
+ print "switching cpus"
if not isinstance(cpuList, list):
raise RuntimeError, "Must pass a list to this function"
for i in cpuList:
@@ -189,9 +190,9 @@ def switchCpus(cpuList):
cc_main.cleanupCountedDrain(drain_event)
# Now all of the CPUs are ready to be switched out
for old_cpu in old_cpus:
+ print "switching"
old_cpu._ccObject.switchOut()
index = 0
- print "Switching CPUs"
for new_cpu in new_cpus:
new_cpu.takeOverFrom(old_cpus[index])
new_cpu._ccObject.resume()
diff --git a/src/sim/main.cc b/src/sim/main.cc
index 874d0ac85..8bb0d7aaa 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -66,6 +66,7 @@
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
#include "sim/sim_object.hh"
+#include "sim/system.hh"
#include "sim/stat_control.hh"
#include "sim/stats.hh"
#include "sim/root.hh"
@@ -440,6 +441,17 @@ convertToBaseCPUPtr(SimObject *obj)
return ptr;
}
+System *
+convertToSystemPtr(SimObject *obj)
+{
+ System *ptr = dynamic_cast<System *>(obj);
+
+ if (ptr == NULL)
+ warn("Casting to System pointer failed");
+ return ptr;
+}
+
+
/**
* Do C++ simulator exit processing. Exported to SWIG to be invoked
* when simulator terminates via Python's atexit mechanism.
diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh
index 38f2bdd23..32807b69d 100644
--- a/src/sim/sim_object.hh
+++ b/src/sim/sim_object.hh
@@ -64,6 +64,13 @@ class SimObject : public Serializable, protected StartupCallback
Draining,
Drained
};
+
+ enum MemoryMode {
+ Invalid=0,
+ Atomic,
+ Timing
+ };
+
private:
State state;
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 3ab1d81f2..827fe5c78 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -62,22 +62,16 @@ class RemoteGDB;
class System : public SimObject
{
public:
- enum MemoryMode {
- Invalid=0,
- Atomic,
- Timing
- };
static const char *MemoryModeStrings[3];
-
- MemoryMode getMemoryMode() { assert(memoryMode); return memoryMode; }
+ SimObject::MemoryMode getMemoryMode() { assert(memoryMode); return memoryMode; }
/** Change the memory mode of the system. This should only be called by the
* python!!
* @param mode Mode to change to (atomic/timing)
*/
- void setMemoryMode(MemoryMode mode);
+ void setMemoryMode(SimObject::MemoryMode mode);
PhysicalMemory *physmem;
PCEventQueue pcEventQueue;
@@ -126,7 +120,7 @@ class System : public SimObject
protected:
- MemoryMode memoryMode;
+ SimObject::MemoryMode memoryMode;
#if FULL_SYSTEM
/**
@@ -173,7 +167,7 @@ class System : public SimObject
{
std::string name;
PhysicalMemory *physmem;
- MemoryMode mem_mode;
+ SimObject::MemoryMode mem_mode;
#if FULL_SYSTEM
Tick boot_cpu_frequency;
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-01 10:06:48 +0000