diff options
Diffstat (limited to 'src')
138 files changed, 2534 insertions, 1197 deletions
diff --git a/src/SConscript b/src/SConscript index 9d7248213..74d9bf9a6 100644 --- a/src/SConscript +++ b/src/SConscript @@ -48,6 +48,7 @@ Import('env') base_sources = Split(''' base/annotate.cc + base/bigint.cc base/circlebuf.cc base/cprintf.cc base/fast_alloc.cc diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 8d13511ac..ec5090eb8 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -62,7 +62,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId) AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault; - tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect()); + tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); tc->setNextPC(tc->readPC() + sizeof(MachInst)); delete reset; @@ -76,12 +76,12 @@ void AlphaISA::initIPRs(ThreadContext *tc, int cpuId) { for (int i = 0; i < NumInternalProcRegs; ++i) { - tc->setMiscReg(i, 0); + tc->setMiscRegNoEffect(i, 0); } - tc->setMiscReg(IPR_PAL_BASE, PalBase); - tc->setMiscReg(IPR_MCSR, 0x6); - tc->setMiscReg(IPR_PALtemp16, cpuId); + tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase); + tc->setMiscRegNoEffect(IPR_MCSR, 0x6); + tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); } @@ -94,13 +94,13 @@ AlphaISA::processInterrupts(CPU *cpu) int ipl = 0; int summary = 0; - if (cpu->readMiscReg(IPR_ASTRR)) + if (cpu->readMiscRegNoEffect(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (cpu->readMiscReg(IPR_SIRR)) { + if (cpu->readMiscRegNoEffect(IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { + if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of the 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -121,12 +121,12 @@ AlphaISA::processInterrupts(CPU *cpu) } } - if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) { - cpu->setMiscReg(IPR_ISR, summary); - cpu->setMiscReg(IPR_INTID, ipl); + if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) { + cpu->setMiscRegNoEffect(IPR_ISR, summary); + cpu->setMiscRegNoEffect(IPR_INTID, ipl); cpu->trap(new InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - cpu->readMiscReg(IPR_IPLR), ipl, summary); + cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary); } } @@ -148,7 +148,7 @@ SimpleThread::hwrei() if (!(readPC() & 0x3)) return new UnimplementedOpcodeFault; - setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); + setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR)); if (!misspeculating()) { if (kernelStats) @@ -554,7 +554,7 @@ void AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) { for (int i = 0; i < NumInternalProcRegs; ++i) { - dest->setMiscReg(i, src->readMiscReg(i)); + dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); } } diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index 5efcf92e4..149729351 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -59,12 +59,6 @@ FaultName ArithmeticFault::_name = "arith"; FaultVect ArithmeticFault::_vect = 0x0501; FaultStat ArithmeticFault::_count; -#if !FULL_SYSTEM -FaultName PageTableFault::_name = "page_table_fault"; -FaultVect PageTableFault::_vect = 0x0000; -FaultStat PageTableFault::_count; -#endif - FaultName InterruptFault::_name = "interrupt"; FaultVect InterruptFault::_vect = 0x0101; FaultStat InterruptFault::_count; @@ -126,15 +120,15 @@ void AlphaFault::invoke(ThreadContext * tc) // exception restart address if (setRestartAddress() || !(tc->readPC() & 0x3)) - tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC()); + tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC()); if (skipFaultingInstruction()) { // traps... skip faulting instruction. - tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, - tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); + tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, + tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4); } - tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect()); + tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect()); tc->setNextPC(tc->readPC() + sizeof(MachInst)); } @@ -154,17 +148,17 @@ void DtbFault::invoke(ThreadContext * tc) if (!tc->misspeculating() && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { // set VA register with faulting address - tc->setMiscReg(AlphaISA::IPR_VA, vaddr); + tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr); // set MM_STAT register flags - tc->setMiscReg(AlphaISA::IPR_MM_STAT, + tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT, (((EV5::Opcode(tc->getInst()) & 0x3f) << 11) | ((EV5::Ra(tc->getInst()) & 0x1f) << 6) | (flags & 0x3f))); // set VA_FORM register with faulting formatted address - tc->setMiscReg(AlphaISA::IPR_VA_FORM, - tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); + tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM, + tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); } AlphaFault::invoke(tc); @@ -173,41 +167,15 @@ void DtbFault::invoke(ThreadContext * tc) void ItbFault::invoke(ThreadContext * tc) { if (!tc->misspeculating()) { - tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); - tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, - tc->readMiscReg(AlphaISA::IPR_IVPTBR) | + tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc); + tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM, + tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) | (AlphaISA::VAddr(pc).vpn() << 3)); } AlphaFault::invoke(tc); } -#else //!FULL_SYSTEM - -void PageTableFault::invoke(ThreadContext *tc) -{ - Process *p = tc->getProcessPtr(); - - // address is higher than the stack region or in the current stack region - if (vaddr > p->stack_base || vaddr > p->stack_min) - FaultBase::invoke(tc); - - // We've accessed the next page - if (vaddr > p->stack_min - PageBytes) { - DPRINTF(Stack, - "Increasing stack %#x:%#x to %#x:%#x because of access to %#x", - p->stack_min, p->stack_base, p->stack_min - PageBytes, - p->stack_base, vaddr); - p->stack_min -= PageBytes; - if (p->stack_base - p->stack_min > 8*1024*1024) - fatal("Over max stack size for one thread\n"); - p->pTable->allocate(p->stack_min, PageBytes); - } else { - warn("Page fault on address %#x\n", vaddr); - FaultBase::invoke(tc); - } -} - #endif } // namespace AlphaISA diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh index e2c3441e9..6342122c2 100644 --- a/src/arch/alpha/faults.hh +++ b/src/arch/alpha/faults.hh @@ -85,29 +85,6 @@ class AlignmentFault : public AlphaFault bool isAlignmentFault() {return true;} }; -#if !FULL_SYSTEM -class PageTableFault : public AlphaFault -{ - private: - Addr vaddr; - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - public: - PageTableFault(Addr va) - : vaddr(va) {} - FaultName name() {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} - void invoke(ThreadContext * tc); -}; - -static inline Fault genPageTableFault(Addr va) -{ - return new PageTableFault(va); -} -#endif - static inline Fault genMachineCheckFault() { return new MachineCheckFault; diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc index 0f6806319..f0f1eab7a 100644 --- a/src/arch/alpha/idle_event.cc +++ b/src/arch/alpha/idle_event.cc @@ -40,6 +40,6 @@ IdleStartEvent::process(ThreadContext *tc) { if (tc->getKernelStats()) tc->getKernelStats()->setIdleProcess( - tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc); + tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23), tc); remove(); } diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh index 0500714ad..6453edf97 100644 --- a/src/arch/alpha/interrupts.hh +++ b/src/arch/alpha/interrupts.hh @@ -112,13 +112,13 @@ namespace AlphaISA int ipl = 0; int summary = 0; - if (tc->readMiscReg(IPR_ASTRR)) + if (tc->readMiscRegNoEffect(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (tc->readMiscReg(IPR_SIRR)) { + if (tc->readMiscRegNoEffect(IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { + if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -138,12 +138,12 @@ namespace AlphaISA } } - if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) { + if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) { newIpl = ipl; newSummary = summary; newInfoSet = true; DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - tc->readMiscReg(IPR_IPLR), ipl, summary); + tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary); return new InterruptFault; } else { @@ -154,8 +154,8 @@ namespace AlphaISA void updateIntrInfo(ThreadContext *tc) { assert(newInfoSet); - tc->setMiscReg(IPR_ISR, newSummary); - tc->setMiscReg(IPR_INTID, newIpl); + tc->setMiscRegNoEffect(IPR_ISR, newSummary); + tc->setMiscRegNoEffect(IPR_INTID, newIpl); newInfoSet = false; } diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 49c25c3c2..b62372f66 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -638,7 +638,7 @@ decode OPCODE default Unknown::unknown() { /* Rb is a fake dependency so here is a fun way to get * the parser to understand that. */ - Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0); + Ra = xc->readMiscReg(AlphaISA::IPR_CC) + (Rb & 0); #else Ra = curTick; @@ -690,7 +690,7 @@ decode OPCODE default Unknown::unknown() { 0x00: CallPal::call_pal({{ if (!palValid || (palPriv - && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) { + && xc->readMiscReg(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) { // invalid pal function code, or attempt to do privileged // PAL call in non-kernel mode fault = new UnimplementedOpcodeFault; @@ -701,8 +701,8 @@ decode OPCODE default Unknown::unknown() { bool dopal = xc->simPalCheck(palFunc); if (dopal) { - xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); - NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset; + xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, NPC); + NPC = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + palOffset; } } }}, IsNonSpeculative); @@ -760,7 +760,7 @@ decode OPCODE default Unknown::unknown() { miscRegIndex >= NumInternalProcRegs) fault = new UnimplementedOpcodeFault; else - Ra = xc->readMiscRegWithEffect(miscRegIndex); + Ra = xc->readMiscReg(miscRegIndex); }}, IsIprAccess); } } @@ -775,7 +775,7 @@ decode OPCODE default Unknown::unknown() { miscRegIndex >= NumInternalProcRegs) fault = new UnimplementedOpcodeFault; else - xc->setMiscRegWithEffect(miscRegIndex, Ra); + xc->setMiscReg(miscRegIndex, Ra); if (traceData) { traceData->setData(Ra); } }}, IsIprAccess); } diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa index c845ea442..a350aa05f 100644 --- a/src/arch/alpha/isa/fp.isa +++ b/src/arch/alpha/isa/fp.isa @@ -46,7 +46,7 @@ output exec {{ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) { Fault fault = NoFault; // dummy... this ipr access should not fault - if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) { + if (!EV5::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) { fault = new FloatEnableFault; } return fault; @@ -229,7 +229,7 @@ def template FloatingPointExecute {{ %(code)s; } else { fesetround(getC99RoundingMode( - xc->readMiscReg(AlphaISA::MISCREG_FPCR))); + xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR))); %(code)s; fesetround(FE_TONEAREST); } diff --git a/src/arch/alpha/kernel_stats.cc b/src/arch/alpha/kernel_stats.cc index 6fc3cb72f..13dc95af7 100644 --- a/src/arch/alpha/kernel_stats.cc +++ b/src/arch/alpha/kernel_stats.cc @@ -150,7 +150,7 @@ Statistics::changeMode(cpu_mode newmode, ThreadContext *tc) void Statistics::mode(cpu_mode newmode, ThreadContext *tc) { - Addr pcbb = tc->readMiscReg(AlphaISA::IPR_PALtemp23); + Addr pcbb = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp23); if (newmode == kernel && pcbb == idleProcess) newmode = idle; diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh index 56b5ba5ed..df66b92bc 100644 --- a/src/arch/alpha/locked_mem.hh +++ b/src/arch/alpha/locked_mem.hh @@ -56,8 +56,8 @@ template <class XC> inline void handleLockedRead(XC *xc, Request *req) { - xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); - xc->setMiscReg(MISCREG_LOCKFLAG, true); + xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); + xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true); } @@ -71,13 +71,13 @@ handleLockedWrite(XC *xc, Request *req) req->setExtraData(2); } else { // standard store conditional - bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); - Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); + bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG); + Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR); if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { // Lock flag not set or addr mismatch in CPU; // don't even bother sending to memory system req->setExtraData(0); - xc->setMiscReg(MISCREG_LOCKFLAG, false); + xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false); // the rest of this code is not architectural; // it's just a debugging aid to help detect // livelock by warning on long sequences of failed diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc index 67f6c98e4..1af97adcf 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/miscregfile.cc @@ -61,7 +61,7 @@ namespace AlphaISA } MiscReg - MiscRegFile::readReg(int misc_reg) + MiscRegFile::readRegNoEffect(int misc_reg) { switch(misc_reg) { case MISCREG_FPCR: @@ -87,7 +87,7 @@ namespace AlphaISA } MiscReg - MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc) + MiscRegFile::readReg(int misc_reg, ThreadContext *tc) { switch(misc_reg) { case MISCREG_FPCR: @@ -112,7 +112,7 @@ namespace AlphaISA } void - MiscRegFile::setReg(int misc_reg, const MiscReg &val) + MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val) { switch(misc_reg) { case MISCREG_FPCR: @@ -143,7 +143,7 @@ namespace AlphaISA } void - MiscRegFile::setRegWithEffect(int misc_reg, const MiscReg &val, + MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc) { switch(misc_reg) { diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh index 31b3e59b3..aea702849 100644 --- a/src/arch/alpha/miscregfile.hh +++ b/src/arch/alpha/miscregfile.hh @@ -75,18 +75,18 @@ namespace AlphaISA #endif } - MiscReg readReg(int misc_reg); + MiscReg readRegNoEffect(int misc_reg); - MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc); + MiscReg readReg(int misc_reg, ThreadContext *tc); //These functions should be removed once the simplescalar cpu model //has been replaced. int getInstAsid(); int getDataAsid(); - void setReg(int misc_reg, const MiscReg &val); + void setRegNoEffect(int misc_reg, const MiscReg &val); - void setRegWithEffect(int misc_reg, const MiscReg &val, + void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc); void clear() diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc index 92e1b07df..3b42ca9bc 100644 --- a/src/arch/alpha/regfile.cc +++ b/src/arch/alpha/regfile.cc @@ -85,14 +85,14 @@ namespace AlphaISA void copyMiscRegs(ThreadContext *src, ThreadContext *dest) { - dest->setMiscReg(AlphaISA::MISCREG_FPCR, - src->readMiscReg(AlphaISA::MISCREG_FPCR)); - dest->setMiscReg(AlphaISA::MISCREG_UNIQ, - src->readMiscReg(AlphaISA::MISCREG_UNIQ)); - dest->setMiscReg(AlphaISA::MISCREG_LOCKFLAG, - src->readMiscReg(AlphaISA::MISCREG_LOCKFLAG)); - dest->setMiscReg(AlphaISA::MISCREG_LOCKADDR, - src->readMiscReg(AlphaISA::MISCREG_LOCKADDR)); + dest->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR, + src->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)); + dest->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ, + src->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ)); + dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, + src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG)); + dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR, + src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR)); #if FULL_SYSTEM copyIprs(src, dest); diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 54372da36..b93707181 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -106,25 +106,25 @@ namespace AlphaISA miscRegFile.clear(); } - MiscReg readMiscReg(int miscReg) + MiscReg readMiscRegNoEffect(int miscReg) { - return miscRegFile.readReg(miscReg); + return miscRegFile.readRegNoEffect(miscReg); } - MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc) + MiscReg readMiscReg(int miscReg, ThreadContext *tc) { - return miscRegFile.readRegWithEffect(miscReg, tc); + return miscRegFile.readReg(miscReg, tc); } - void setMiscReg(int miscReg, const MiscReg &val) + void setMiscRegNoEffect(int miscReg, const MiscReg &val) { - miscRegFile.setReg(miscReg, val); + miscRegFile.setRegNoEffect(miscReg, val); } - void setMiscRegWithEffect(int miscReg, const MiscReg &val, + void setMiscReg(int miscReg, const MiscReg &val, ThreadContext * tc) { - miscRegFile.setRegWithEffect(miscReg, val, tc); + miscRegFile.setReg(miscReg, val, tc); } FloatReg readFloatReg(int floatReg) diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index 4637bd7a6..a68e5218e 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -187,7 +187,7 @@ RemoteGDB::acc(Addr va, size_t len) if (AlphaISA::PcPAL(va) || va < 0x10000) return true; - Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20); + Addr ptbr = context->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20); TheISA::PageTableEntry pte = TheISA::kernel_pte_lookup(context->getPhysPort(), ptbr, va); if (!pte.valid()) { DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va); diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc index c4612e156..c16498e72 100644 --- a/src/arch/alpha/stacktrace.cc +++ b/src/arch/alpha/stacktrace.cc @@ -146,7 +146,7 @@ namespace AlphaISA { tc = _tc; - bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + bool usermode = (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; Addr pc = tc->readNextPC(); bool kernel = tc->getSystemPtr()->kernelStart <= pc && @@ -219,22 +219,22 @@ namespace AlphaISA bool StackTrace::isEntry(Addr addr) { - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp12)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp7)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp11)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp21)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp9)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp2)) return true; return false; diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 1e0155138..3ab65e664 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -312,14 +312,14 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 #if ALPHA_TLASER - if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && + if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && VAddrSpaceEV5(req->getVaddr()) == 2) #else if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) #endif { // only valid in kernel mode - if (ICM_CM(tc->readMiscReg(IPR_ICM)) != + if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != mode_kernel) { acv++; return new ItbAcvFault(req->getVaddr()); @@ -337,7 +337,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const } else { // not a physical address: need to look up pte - int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN)); + int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), asn); @@ -352,7 +352,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) const // check permissions for this access if (!(pte->xre & - (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) { + (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { // instruction access fault acv++; return new ItbAcvFault(req->getVaddr()); @@ -453,7 +453,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const Addr pc = tc->readPC(); mode_type mode = - (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)); + (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); /** @@ -469,7 +469,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const if (PcPAL(pc)) { mode = (req->getFlags() & ALTMODE) ? (mode_type)ALT_MODE_AM( - tc->readMiscReg(IPR_ALT_MODE)) + tc->readMiscRegNoEffect(IPR_ALT_MODE)) : mode_kernel; } @@ -487,7 +487,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const // Check for "superpage" mapping #if ALPHA_TLASER - if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && + if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && VAddrSpaceEV5(req->getVaddr()) == 2) #else if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) @@ -495,7 +495,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const { // only valid in kernel mode - if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) != + if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != mode_kernel) { if (write) { write_acv++; } else { read_acv++; } uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | @@ -519,7 +519,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const else read_accesses++; - int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN)); + int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); // not a physical address: need to look up pte PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index 9a06cc2a4..c8a50e8a2 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -45,7 +45,7 @@ namespace AlphaISA static inline bool inUserMode(ThreadContext *tc) { - return (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; } static inline ExtMachInst diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc index 1a3147bcc..6ffbea181 100644 --- a/src/arch/alpha/vtophys.cc +++ b/src/arch/alpha/vtophys.cc @@ -88,7 +88,7 @@ Addr AlphaISA::vtophys(ThreadContext *tc, Addr addr) { AlphaISA::VAddr vaddr = addr; - Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20); + Addr ptbr = tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp20); Addr paddr = 0; //@todo Andrew couldn't remember why he commented some of this code //so I put it back in. Perhaps something to do with gdb debugging? diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 9b63c8842..21860a2e1 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1368,7 +1368,7 @@ class ControlRegOperand(Operand): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read control register as FP') - base = 'xc->readMiscRegOperandWithEffect(this, %s)' % self.src_reg_idx + base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx if self.size == self.dflt_size: return '%s = %s;\n' % (self.base_name, base) else: @@ -1378,7 +1378,7 @@ class ControlRegOperand(Operand): def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to write control register as FP') - wb = 'xc->setMiscRegOperandWithEffect(this, %s, %s);\n' % \ + wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ (self.dest_reg_idx, self.base_name) wb += 'if (traceData) { traceData->setData(%s); }' % \ self.base_name diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 2a8ab1df5..c9e6aa75b 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -58,12 +58,6 @@ FaultName ArithmeticFault::_name = "arith"; FaultVect ArithmeticFault::_vect = 0x0501; FaultStat ArithmeticFault::_count; -#if !FULL_SYSTEM -FaultName PageTableFault::_name = "page_table_fault"; -FaultVect PageTableFault::_vect = 0x0000; -FaultStat PageTableFault::_count; -#endif - FaultName InterruptFault::_name = "interrupt"; FaultVect InterruptFault::_vect = 0x0101; FaultStat InterruptFault::_count; @@ -112,25 +106,5 @@ FaultName IntegerOverflowFault::_name = "intover"; FaultVect IntegerOverflowFault::_vect = 0x0501; FaultStat IntegerOverflowFault::_count; -void PageTableFault::invoke(ThreadContext *tc) -{ - Process *p = tc->getProcessPtr(); - - // address is higher than the stack region or in the current stack region - if (vaddr > p->stack_base || vaddr > p->stack_min) - FaultBase::invoke(tc); - - // We've accessed the next page - if (vaddr > p->stack_min - PageBytes) { - p->stack_min -= PageBytes; - if (p->stack_base - p->stack_min > 8*1024*1024) - fatal("Over max stack size for one thread\n"); - p->pTable->allocate(p->stack_min, PageBytes); - warn("Increasing stack size by one page."); - } else { - FaultBase::invoke(tc); - } -} - } // namespace MipsISA diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh index 9d2c5df32..86c742413 100644 --- a/src/arch/mips/faults.hh +++ b/src/arch/mips/faults.hh @@ -80,30 +80,6 @@ class AlignmentFault : public MipsFault bool isAlignmentFault() {return true;} }; -#if !FULL_SYSTEM -class PageTableFault : public MipsFault -{ - private: - Addr vaddr; - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - public: - PageTableFault(Addr va) - : vaddr(va) {} - FaultName name() {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} - void invoke(ThreadContext * tc); -}; - -static inline Fault genPageTableFault(Addr va) -{ - return new PageTableFault(va); -} -#endif - - static inline Fault genMachineCheckFault() { return new MachineCheckFault; diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 3a8688797..b5d1df4fc 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -289,8 +289,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode RS_MSB { 0x0: decode RS { format CP0Control { - 0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }}); - 0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }}); + 0x0: mfc0({{ Rt = xc->readMiscRegNoEffect(RD << 5 | SEL); }}); + 0x4: mtc0({{ xc->setMiscRegNoEffect(RD << 5 | SEL, Rt); }}); } format MipsMT { diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 368925e00..53ee09512 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -215,22 +215,22 @@ namespace MipsISA void copyMiscRegs(ThreadContext *tc); - MiscReg readReg(int misc_reg) + MiscReg readRegNoEffect(int misc_reg) { return miscRegFile[misc_reg]; } - MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc) + MiscReg readReg(int misc_reg, ThreadContext *tc) { return miscRegFile[misc_reg]; } - void setReg(int misc_reg, const MiscReg &val) + void setRegNoEffect(int misc_reg, const MiscReg &val) { miscRegFile[misc_reg] = val; } - void setRegWithEffect(int misc_reg, const MiscReg &val, + void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc) { miscRegFile[misc_reg] = val; diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index 7b57b31f5..387fbd5c8 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -57,25 +57,25 @@ namespace MipsISA bzero(&miscRegFile, sizeof(miscRegFile)); } - MiscReg readMiscReg(int miscReg) + MiscReg readMiscRegNoEffect(int miscReg) { - return miscRegFile.readReg(miscReg); + return miscRegFile.readRegNoEffect(miscReg); } - MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc) + MiscReg readMiscReg(int miscReg, ThreadContext *tc) { - return miscRegFile.readRegWithEffect(miscReg, tc); + return miscRegFile.readReg(miscReg, tc); } - void setMiscReg(int miscReg, const MiscReg &val) + void setMiscRegNoEffect(int miscReg, const MiscReg &val) { - miscRegFile.setReg(miscReg, val); + miscRegFile.setRegNoEffect(miscReg, val); } - void setMiscRegWithEffect(int miscReg, const MiscReg &val, + void setMiscReg(int miscReg, const MiscReg &val, ThreadContext * tc) { - miscRegFile.setRegWithEffect(miscReg, val, tc); + miscRegFile.setReg(miscReg, val, tc); } FloatRegVal readFloatReg(int floatReg) diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index b1a6ae919..88c086090 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -267,12 +267,6 @@ template<> SparcFaultBase::FaultVals SparcFault<TrapInstruction>::vals = {"trap_instruction", 0x100, 1602, {P, P, H}}; -#if !FULL_SYSTEM -template<> SparcFaultBase::FaultVals - SparcFault<PageTableFault>::vals = - {"page_table_fault", 0x0000, 0, {SH, SH, SH}}; -#endif - /** * This causes the thread context to enter RED state. This causes the side * effects which go with entering RED state because of a trap. @@ -282,17 +276,17 @@ void enterREDState(ThreadContext *tc) { //@todo Disable the mmu? //@todo Disable watchpoints? - MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); + MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); //HPSTATE.red = 1 HPSTATE |= (1 << 5); //HPSTATE.hpriv = 1 HPSTATE |= (1 << 2); - tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE); + tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); //PSTATE.priv is set to 1 here. The manual says it should be 0, but //Legion sets it to 1. - MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); + MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE); PSTATE |= (1 << 2); - tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE); + tc->setMiscReg(MISCREG_PSTATE, PSTATE); } /** @@ -302,17 +296,17 @@ void enterREDState(ThreadContext *tc) void doREDFault(ThreadContext *tc, TrapType tt) { - MiscReg TL = tc->readMiscReg(MISCREG_TL); - MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE); - MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); - MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); - //MiscReg CCR = tc->readMiscReg(MISCREG_CCR); + MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL); + MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE); + MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE); + MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); + //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR); MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); - MiscReg ASI = tc->readMiscReg(MISCREG_ASI); - MiscReg CWP = tc->readMiscReg(MISCREG_CWP); - //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE); - MiscReg CANSAVE = tc->readMiscReg(NumIntArchRegs + 3); - MiscReg GL = tc->readMiscReg(MISCREG_GL); + MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); + MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); + //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE); + MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3); + MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); MiscReg PC = tc->readPC(); MiscReg NPC = tc->readNextPC(); @@ -335,25 +329,25 @@ void doREDFault(ThreadContext *tc, TrapType tt) replaceBits(TSTATE, 4, 0, CWP); //Write back TSTATE - tc->setMiscReg(MISCREG_TSTATE, TSTATE); + tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); //set TPC to PC - tc->setMiscReg(MISCREG_TPC, PC); + tc->setMiscRegNoEffect(MISCREG_TPC, PC); //set TNPC to NPC - tc->setMiscReg(MISCREG_TNPC, NPC); + tc->setMiscRegNoEffect(MISCREG_TNPC, NPC); //set HTSTATE.hpstate to hpstate - tc->setMiscReg(MISCREG_HTSTATE, HPSTATE); + tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE); //TT = trap type; - tc->setMiscReg(MISCREG_TT, tt); + tc->setMiscRegNoEffect(MISCREG_TT, tt); //Update GL - tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL)); + tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL)); PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit PSTATE |= (1 << 4); //set PSTATE.pef to 1 - tc->setMiscReg(MISCREG_PSTATE, PSTATE); + tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE); //set HPSTATE.red to 1 HPSTATE |= (1 << 5); @@ -363,7 +357,7 @@ void doREDFault(ThreadContext *tc, TrapType tt) HPSTATE &= ~(1 << 10); //set HPSTATE.tlz to 0 HPSTATE &= ~(1 << 0); - tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); + tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE); bool changedCWP = true; if(tt == 0x24) @@ -378,7 +372,7 @@ void doREDFault(ThreadContext *tc, TrapType tt) if(changedCWP) { CWP = (CWP + NWindows) % NWindows; - tc->setMiscRegWithEffect(MISCREG_CWP, CWP); + tc->setMiscReg(MISCREG_CWP, CWP); } } @@ -389,17 +383,17 @@ void doREDFault(ThreadContext *tc, TrapType tt) void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) { - MiscReg TL = tc->readMiscReg(MISCREG_TL); - MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE); - MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); - MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); - //MiscReg CCR = tc->readMiscReg(MISCREG_CCR); + MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL); + MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE); + MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE); + MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); + //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR); MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); - MiscReg ASI = tc->readMiscReg(MISCREG_ASI); - MiscReg CWP = tc->readMiscReg(MISCREG_CWP); - //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE); + MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); + MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); + //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE); MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3); - MiscReg GL = tc->readMiscReg(MISCREG_GL); + MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); MiscReg PC = tc->readPC(); MiscReg NPC = tc->readNextPC(); @@ -410,7 +404,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) //Increment the trap level TL++; - tc->setMiscReg(MISCREG_TL, TL); + tc->setMiscRegNoEffect(MISCREG_TL, TL); //Save off state @@ -426,24 +420,24 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) replaceBits(TSTATE, 4, 0, CWP); //Write back TSTATE - tc->setMiscReg(MISCREG_TSTATE, TSTATE); + tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); //set TPC to PC - tc->setMiscReg(MISCREG_TPC, PC); + tc->setMiscRegNoEffect(MISCREG_TPC, PC); //set TNPC to NPC - tc->setMiscReg(MISCREG_TNPC, NPC); + tc->setMiscRegNoEffect(MISCREG_TNPC, NPC); //set HTSTATE.hpstate to hpstate - tc->setMiscReg(MISCREG_HTSTATE, HPSTATE); + tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE); //TT = trap type; - tc->setMiscReg(MISCREG_TT, tt); + tc->setMiscRegNoEffect(MISCREG_TT, tt); //Update the global register level if (!gotoHpriv) - tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL)); + tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxPGL)); else - tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL)); + tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL)); //PSTATE.mm is unchanged PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present @@ -460,12 +454,12 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1 HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0 //HPSTATE.tlz is unchanged - tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); + tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE); } else { // we are going to priv PSTATE |= (1 << 2); //PSTATE.priv = 1 replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle } - tc->setMiscReg(MISCREG_PSTATE, PSTATE); + tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE); bool changedCWP = true; @@ -481,7 +475,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv) if (changedCWP) { CWP = (CWP + NWindows) % NWindows; - tc->setMiscRegWithEffect(MISCREG_CWP, CWP); + tc->setMiscReg(MISCREG_CWP, CWP); } } @@ -495,14 +489,14 @@ void getREDVector(MiscReg TT, Addr & PC, Addr & NPC) void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT) { - Addr HTBA = tc->readMiscReg(MISCREG_HTBA); + Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA); PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14)); NPC = PC + sizeof(MachInst); } void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL) { - Addr TBA = tc->readMiscReg(MISCREG_TBA); + Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA); PC = (TBA & ~mask(15)) | (TL > 1 ? (1 << 14) : 0) | ((TT << 5) & mask(14)); @@ -519,10 +513,10 @@ void SparcFaultBase::invoke(ThreadContext * tc) //We can refer to this to see what the trap level -was-, but something //in the middle could change it in the regfile out from under us. - MiscReg tl = tc->readMiscReg(MISCREG_TL); - MiscReg tt = tc->readMiscReg(MISCREG_TT); - MiscReg pstate = tc->readMiscReg(MISCREG_PSTATE); - MiscReg hpstate = tc->readMiscReg(MISCREG_HPSTATE); + MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL); + MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT); + MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); + MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); Addr PC, NPC; @@ -571,15 +565,15 @@ void PowerOnReset::invoke(ThreadContext * tc) //on reset Trap which sets the processor into the following state. //Bits that aren't set aren't defined on startup. - tc->setMiscReg(MISCREG_TL, MaxTL); - tc->setMiscReg(MISCREG_TT, trapType()); - tc->setMiscRegWithEffect(MISCREG_GL, MaxGL); + tc->setMiscRegNoEffect(MISCREG_TL, MaxTL); + tc->setMiscRegNoEffect(MISCREG_TT, trapType()); + tc->setMiscReg(MISCREG_GL, MaxGL); //Turn on pef and priv, set everything else to 0 - tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2)); + tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2)); //Turn on red and hpriv, set everything else to 0 - MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); + MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); //HPSTATE.red = 1 HPSTATE |= (1 << 5); //HPSTATE.hpriv = 1 @@ -588,10 +582,10 @@ void PowerOnReset::invoke(ThreadContext * tc) HPSTATE &= ~(1 << 10); //HPSTATE.tlz = 0 HPSTATE &= ~(1 << 0); - tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); + tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE); //The tick register is unreadable by nonprivileged software - tc->setMiscReg(MISCREG_TICK, 1ULL << 63); + tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63); //Enter RED state. We do this last so that the actual state preserved in //the trap stack is the state from before this fault. @@ -609,7 +603,7 @@ void PowerOnReset::invoke(ThreadContext * tc) // Clear all the soft interrupt bits softint = 0; // disable timer compare interrupts, reset tick_cmpr - tc->setMiscReg(MISCREG_ + tc->setMiscRegNoEffect(MISCREG_ tick_cmprFields.int_dis = 1; tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing stickFields.npt = 1; //The TICK register is unreadable by by !priv @@ -680,28 +674,6 @@ void TrapInstruction::invoke(ThreadContext *tc) tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst)); } -void PageTableFault::invoke(ThreadContext *tc) -{ - Process *p = tc->getProcessPtr(); - - // We've accessed the next page of the stack, so extend the stack - // to cover it. - if(vaddr < p->stack_min && vaddr >= p->stack_min - PageBytes) - { - p->stack_min -= PageBytes; - if(p->stack_base - p->stack_min > 8*1024*1024) - fatal("Over max stack size for one thread\n"); - p->pTable->allocate(p->stack_min, PageBytes); - warn("Increasing stack size by one page."); - } - // Otherwise, we have an unexpected page fault. Report that fact, - // and what address was accessed to cause the fault. - else - { - panic("Page table fault when accessing virtual address %#x\n", vaddr); - } -} - #endif } // namespace SparcISA diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 0ba897e67..10ef89279 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -256,22 +256,6 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction> #endif }; -#if !FULL_SYSTEM -class PageTableFault : public SparcFault<PageTableFault> -{ - private: - Addr vaddr; - public: - PageTableFault(Addr va) : vaddr(va) {} - void invoke(ThreadContext * tc); -}; - -static inline Fault genPageTableFault(Addr va) -{ - return new PageTableFault(va); -} -#endif - static inline Fault genMachineCheckFault() { return new InternalProcessorError; diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index 3234002c5..4ad3385fb 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -102,8 +102,8 @@ class Interrupts Fault getInterrupt(ThreadContext * tc) { - int hpstate = tc->readMiscReg(MISCREG_HPSTATE); - int pstate = tc->readMiscReg(MISCREG_PSTATE); + int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); + int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); bool ie = pstate & PSTATE::ie; // THESE ARE IN ORDER OF PRIORITY diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index 693cc6876..bba63f407 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -492,8 +492,8 @@ output exec {{ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) { Fault fault = NoFault; // dummy... this ipr access should not fault - if (xc->readMiscRegWithEffect(MISCREG_PSTATE) & PSTATE::pef && - xc->readMiscRegWithEffect(MISCREG_FPRS) & 0x4) + if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef && + xc->readMiscReg(MISCREG_FPRS) & 0x4) return NoFault; else return new FpDisabled; diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 849eed1cc..20bc4ae5d 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -140,7 +140,7 @@ void MiscRegFile::clear() #endif } -MiscReg MiscRegFile::readReg(int miscReg) +MiscReg MiscRegFile::readRegNoEffect(int miscReg) { switch (miscReg) { case MISCREG_TLB_DATA: @@ -331,7 +331,7 @@ MiscReg MiscRegFile::readReg(int miscReg) } } -MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) +MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) { switch (miscReg) { // tick and stick are aliased to each other in niagra @@ -374,7 +374,7 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) case MISCREG_QUEUE_NRES_ERROR_TAIL: #if FULL_SYSTEM case MISCREG_HPSTATE: - return readFSRegWithEffect(miscReg, tc); + return readFSReg(miscReg, tc); #else case MISCREG_HPSTATE: //HPSTATE is special because because sometimes in privilege checks for instructions @@ -386,10 +386,10 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) #endif } - return readReg(miscReg); + return readRegNoEffect(miscReg); } -void MiscRegFile::setReg(int miscReg, const MiscReg &val) +void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val) { switch (miscReg) { // case MISCREG_Y: @@ -621,7 +621,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) } } -void MiscRegFile::setRegWithEffect(int miscReg, +void MiscRegFile::setReg(int miscReg, const MiscReg &val, ThreadContext * tc) { MiscReg new_val = val; @@ -682,7 +682,7 @@ void MiscRegFile::setRegWithEffect(int miscReg, case MISCREG_QUEUE_NRES_ERROR_TAIL: #if FULL_SYSTEM case MISCREG_HPSTATE: - setFSRegWithEffect(miscReg, val, tc); + setFSReg(miscReg, val, tc); return; #else case MISCREG_HPSTATE: @@ -692,7 +692,7 @@ void MiscRegFile::setRegWithEffect(int miscReg, panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val); #endif } - setReg(miscReg, new_val); + setRegNoEffect(miscReg, new_val); } void MiscRegFile::serialize(std::ostream & os) diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index ac0e930c5..6063c21c8 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -257,9 +257,8 @@ namespace SparcISA // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu #if FULL_SYSTEM - void setFSRegWithEffect(int miscReg, const MiscReg &val, - ThreadContext *tc); - MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc); + void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); + MiscReg readFSReg(int miscReg, ThreadContext * tc); // Update interrupt state on softint or pil change void checkSoftInt(ThreadContext *tc); @@ -291,13 +290,13 @@ namespace SparcISA clear(); } - MiscReg readReg(int miscReg); + MiscReg readRegNoEffect(int miscReg); - MiscReg readRegWithEffect(int miscReg, ThreadContext *tc); + MiscReg readReg(int miscReg, ThreadContext *tc); - void setReg(int miscReg, const MiscReg &val); + void setRegNoEffect(int miscReg, const MiscReg &val); - void setRegWithEffect(int miscReg, + void setReg(int miscReg, const MiscReg &val, ThreadContext * tc); int getInstAsid() diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index c22aa6781..e4774ab54 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -88,38 +88,38 @@ Sparc32LiveProcess::startup() //From the SPARC ABI //The process runs in user mode - threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02); + threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02); //Setup default FP state - threadContexts[0]->setMiscReg(MISCREG_FSR, 0); + threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0); - threadContexts[0]->setMiscReg(MISCREG_TICK, 0); + threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0); // /* * Register window management registers */ //No windows contain info from other programs - //threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0); //There are no windows to pop - //threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0); //All windows are available to save into - //threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2); //All windows are "clean" - //threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows); //Start with register window 0 - threadContexts[0]->setMiscReg(MISCREG_CWP, 0); + threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0); //Always use spill and fill traps 0 - //threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0); threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0); //Set the trap level to 0 - threadContexts[0]->setMiscReg(MISCREG_TL, 0); + threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0); //Set the ASI register to something fixed - threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY); + threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); } void @@ -130,38 +130,38 @@ Sparc64LiveProcess::startup() //From the SPARC ABI //The process runs in user mode - threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02); + threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02); //Setup default FP state - threadContexts[0]->setMiscReg(MISCREG_FSR, 0); + threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0); - threadContexts[0]->setMiscReg(MISCREG_TICK, 0); + threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0); // /* * Register window management registers */ //No windows contain info from other programs - //threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0); //There are no windows to pop - //threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0); //All windows are available to save into - //threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2); //All windows are "clean" - //threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows); //Start with register window 0 - threadContexts[0]->setMiscReg(MISCREG_CWP, 0); + threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0); //Always use spill and fill traps 0 - //threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0); + //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0); threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0); //Set the trap level to 0 - threadContexts[0]->setMiscReg(MISCREG_TL, 0); + threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0); //Set the ASI register to something fixed - threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY); + threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); } M5_32_auxv_t::M5_32_auxv_t(int32_t type, int32_t val) diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 944b1f401..667b1f002 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -75,25 +75,25 @@ void RegFile::clear() miscRegFile.clear(); } -MiscReg RegFile::readMiscReg(int miscReg) +MiscReg RegFile::readMiscRegNoEffect(int miscReg) { - return miscRegFile.readReg(miscReg); + return miscRegFile.readRegNoEffect(miscReg); } -MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc) +MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc) { - return miscRegFile.readRegWithEffect(miscReg, tc); + return miscRegFile.readReg(miscReg, tc); } -void RegFile::setMiscReg(int miscReg, const MiscReg &val) +void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val) { - miscRegFile.setReg(miscReg, val); + miscRegFile.setRegNoEffect(miscReg, val); } -void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val, +void RegFile::setMiscReg(int miscReg, const MiscReg &val, ThreadContext * tc) { - miscRegFile.setRegWithEffect(miscReg, val, tc); + miscRegFile.setReg(miscReg, val, tc); } FloatReg RegFile::readFloatReg(int floatReg, int width) @@ -153,8 +153,8 @@ void RegFile::setIntReg(int intReg, const IntReg &val) int SparcISA::flattenIntIndex(ThreadContext * tc, int reg) { - int gl = tc->readMiscReg(MISCREG_GL); - int cwp = tc->readMiscReg(MISCREG_CWP); + int gl = tc->readMiscRegNoEffect(MISCREG_GL); + int cwp = tc->readMiscRegNoEffect(MISCREG_CWP); //DPRINTF(Sparc, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp); int newReg; //The total number of global registers @@ -257,146 +257,146 @@ void RegFile::changeContext(RegContextParam param, RegContextVal val) void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) { - uint8_t tl = src->readMiscReg(MISCREG_TL); + uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); // Read all the trap level dependent registers and save them off for(int i = 1; i <= MaxTL; i++) { - src->setMiscReg(MISCREG_TL, i); - dest->setMiscReg(MISCREG_TL, i); + src->setMiscRegNoEffect(MISCREG_TL, i); + dest->setMiscRegNoEffect(MISCREG_TL, i); - dest->setMiscReg(MISCREG_TT, src->readMiscReg(MISCREG_TT)); - dest->setMiscReg(MISCREG_TPC, src->readMiscReg(MISCREG_TPC)); - dest->setMiscReg(MISCREG_TNPC, src->readMiscReg(MISCREG_TNPC)); - dest->setMiscReg(MISCREG_TSTATE, src->readMiscReg(MISCREG_TSTATE)); + dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); + dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); + dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); + dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); } // Save off the traplevel - dest->setMiscReg(MISCREG_TL, tl); - src->setMiscReg(MISCREG_TL, tl); + dest->setMiscRegNoEffect(MISCREG_TL, tl); + src->setMiscRegNoEffect(MISCREG_TL, tl); // ASRs -// dest->setMiscReg(MISCREG_Y, src->readMiscReg(MISCREG_Y)); -// dest->setMiscReg(MISCREG_CCR, src->readMiscReg(MISCREG_CCR)); - dest->setMiscReg(MISCREG_ASI, src->readMiscReg(MISCREG_ASI)); - dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK)); - dest->setMiscReg(MISCREG_FPRS, src->readMiscReg(MISCREG_FPRS)); - dest->setMiscReg(MISCREG_SOFTINT, src->readMiscReg(MISCREG_SOFTINT)); - dest->setMiscReg(MISCREG_TICK_CMPR, src->readMiscReg(MISCREG_TICK_CMPR)); - dest->setMiscReg(MISCREG_STICK, src->readMiscReg(MISCREG_STICK)); - dest->setMiscReg(MISCREG_STICK_CMPR, src->readMiscReg(MISCREG_STICK_CMPR)); +// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); +// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); + dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); + dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); + dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); + dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); + dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); + dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); + dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); // Priv Registers - dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK)); - dest->setMiscReg(MISCREG_TBA, src->readMiscReg(MISCREG_TBA)); - dest->setMiscReg(MISCREG_PSTATE, src->readMiscReg(MISCREG_PSTATE)); - dest->setMiscReg(MISCREG_PIL, src->readMiscReg(MISCREG_PIL)); - dest->setMiscReg(MISCREG_CWP, src->readMiscReg(MISCREG_CWP)); -// dest->setMiscReg(MISCREG_CANSAVE, src->readMiscReg(MISCREG_CANSAVE)); -// dest->setMiscReg(MISCREG_CANRESTORE, src->readMiscReg(MISCREG_CANRESTORE)); -// dest->setMiscReg(MISCREG_OTHERWIN, src->readMiscReg(MISCREG_OTHERWIN)); -// dest->setMiscReg(MISCREG_CLEANWIN, src->readMiscReg(MISCREG_CLEANWIN)); -// dest->setMiscReg(MISCREG_WSTATE, src->readMiscReg(MISCREG_WSTATE)); - dest->setMiscReg(MISCREG_GL, src->readMiscReg(MISCREG_GL)); + dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); + dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); + dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); + dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); + dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); +// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); +// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); +// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); +// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); +// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); + dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); // Hyperprivilged registers - dest->setMiscReg(MISCREG_HPSTATE, src->readMiscReg(MISCREG_HPSTATE)); - dest->setMiscReg(MISCREG_HINTP, src->readMiscReg(MISCREG_HINTP)); - dest->setMiscReg(MISCREG_HTBA, src->readMiscReg(MISCREG_HTBA)); - dest->setMiscReg(MISCREG_STRAND_STS_REG, - src->readMiscReg(MISCREG_STRAND_STS_REG)); - dest->setMiscReg(MISCREG_HSTICK_CMPR, - src->readMiscReg(MISCREG_HSTICK_CMPR)); + dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); + dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); + dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); + dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, + src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); + dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, + src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); // FSR - dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR)); + dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); //Strand Status Register - dest->setMiscReg(MISCREG_STRAND_STS_REG, - src->readMiscReg(MISCREG_STRAND_STS_REG)); + dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, + src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); // MMU Registers - dest->setMiscReg(MISCREG_MMU_P_CONTEXT, - src->readMiscReg(MISCREG_MMU_P_CONTEXT)); - dest->setMiscReg(MISCREG_MMU_S_CONTEXT, - src->readMiscReg(MISCREG_MMU_S_CONTEXT)); - dest->setMiscReg(MISCREG_MMU_PART_ID, - src->readMiscReg(MISCREG_MMU_PART_ID)); - dest->setMiscReg(MISCREG_MMU_LSU_CTRL, - src->readMiscReg(MISCREG_MMU_LSU_CTRL)); - - dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0, - src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0)); - dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1, - src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1)); - dest->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG, - src->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG)); - dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0, - src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0)); - dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1, - src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1)); - dest->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG, - src->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); - dest->setMiscReg(MISCREG_MMU_ITLB_SFSR, - src->readMiscReg(MISCREG_MMU_ITLB_SFSR)); - dest->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, - src->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS)); - - dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0, - src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0)); - dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1, - src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1)); - dest->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG, - src->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG)); - dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0, - src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0)); - dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1, - src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1)); - dest->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG, - src->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); - dest->setMiscReg(MISCREG_MMU_DTLB_SFSR, - src->readMiscReg(MISCREG_MMU_DTLB_SFSR)); - dest->setMiscReg(MISCREG_MMU_DTLB_SFAR, - src->readMiscReg(MISCREG_MMU_DTLB_SFAR)); - dest->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, - src->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS)); + dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, + src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); + dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, + src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); + dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, + src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); + dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, + src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); + + dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, + src->readMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); + dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, + src->readMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); + dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_C0_CONFIG, + src->readMiscRegNoEffect(MISCREG_MMU_ITLB_C0_CONFIG)); + dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, + src->readMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); + dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, + src->readMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); + dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_CX_CONFIG, + src->readMiscRegNoEffect(MISCREG_MMU_ITLB_CX_CONFIG)); + dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_SFSR, + src->readMiscRegNoEffect(MISCREG_MMU_ITLB_SFSR)); + dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_TAG_ACCESS, + src->readMiscRegNoEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); + + dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, + src->readMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); + dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, + src->readMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); + dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_C0_CONFIG, + src->readMiscRegNoEffect(MISCREG_MMU_DTLB_C0_CONFIG)); + dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, + src->readMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); + dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, + src->readMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); + dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_CX_CONFIG, + src->readMiscRegNoEffect(MISCREG_MMU_DTLB_CX_CONFIG)); + dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_SFSR, + src->readMiscRegNoEffect(MISCREG_MMU_DTLB_SFSR)); + dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_SFAR, + src->readMiscRegNoEffect(MISCREG_MMU_DTLB_SFAR)); + dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_TAG_ACCESS, + src->readMiscRegNoEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); // Scratchpad Registers - dest->setMiscReg(MISCREG_SCRATCHPAD_R0, - src->readMiscReg(MISCREG_SCRATCHPAD_R0)); - dest->setMiscReg(MISCREG_SCRATCHPAD_R1, - src->readMiscReg(MISCREG_SCRATCHPAD_R1)); - dest->setMiscReg(MISCREG_SCRATCHPAD_R2, - src->readMiscReg(MISCREG_SCRATCHPAD_R2)); - dest->setMiscReg(MISCREG_SCRATCHPAD_R3, - src->readMiscReg(MISCREG_SCRATCHPAD_R3)); - dest->setMiscReg(MISCREG_SCRATCHPAD_R4, - src->readMiscReg(MISCREG_SCRATCHPAD_R4)); - dest->setMiscReg(MISCREG_SCRATCHPAD_R5, - src->readMiscReg(MISCREG_SCRATCHPAD_R5)); - dest->setMiscReg(MISCREG_SCRATCHPAD_R6, - src->readMiscReg(MISCREG_SCRATCHPAD_R6)); - dest->setMiscReg(MISCREG_SCRATCHPAD_R7, - src->readMiscReg(MISCREG_SCRATCHPAD_R7)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); + dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, + src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); // Queue Registers - dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD, - src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD)); - dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL, - src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL)); - dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD, - src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD)); - dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL, - src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL)); - dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD, - src->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD)); - dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL, - src->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL)); - dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD, - src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD)); - dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL, - src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, + src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); + dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, + src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); } void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest) diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 9e0b3beb3..f3e253f7e 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -73,13 +73,13 @@ namespace SparcISA int FlattenIntIndex(int reg); - MiscReg readMiscReg(int miscReg); + MiscReg readMiscRegNoEffect(int miscReg); - MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc); + MiscReg readMiscReg(int miscReg, ThreadContext *tc); - void setMiscReg(int miscReg, const MiscReg &val); + void setMiscRegNoEffect(int miscReg, const MiscReg &val); - void setMiscRegWithEffect(int miscReg, const MiscReg &val, + void setMiscReg(int miscReg, const MiscReg &val, ThreadContext * tc); int instAsid() diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc index e2ea7a84d..85b0c03a3 100644 --- a/src/arch/sparc/remote_gdb.cc +++ b/src/arch/sparc/remote_gdb.cc @@ -167,7 +167,7 @@ RemoteGDB::getregs() { memset(gdbregs.regs, 0, gdbregs.size); - if (context->readMiscRegWithEffect(MISCREG_PSTATE) & + if (context->readMiscReg(MISCREG_PSTATE) & PSTATE::am) { uint32_t *regs; regs = (uint32_t*)gdbregs.regs; @@ -177,8 +177,8 @@ RemoteGDB::getregs() regs[x] = htobe((uint32_t)context->readIntReg(x - RegG0)); regs[Reg32Y] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 1)); - regs[Reg32Psr] = htobe((uint32_t)context->readMiscRegWithEffect(MISCREG_PSTATE)); - regs[Reg32Fsr] = htobe((uint32_t)context->readMiscRegWithEffect(MISCREG_FSR)); + regs[Reg32Psr] = htobe((uint32_t)context->readMiscReg(MISCREG_PSTATE)); + regs[Reg32Fsr] = htobe((uint32_t)context->readMiscReg(MISCREG_FSR)); regs[Reg32Csr] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 2)); } else { gdbregs.regs[RegPc] = htobe(context->readPC()); @@ -186,13 +186,13 @@ RemoteGDB::getregs() for(int x = RegG0; x <= RegI0 + 7; x++) gdbregs.regs[x] = htobe(context->readIntReg(x - RegG0)); - gdbregs.regs[RegFsr] = htobe(context->readMiscRegWithEffect(MISCREG_FSR)); - gdbregs.regs[RegFprs] = htobe(context->readMiscRegWithEffect(MISCREG_FPRS)); + gdbregs.regs[RegFsr] = htobe(context->readMiscReg(MISCREG_FSR)); + gdbregs.regs[RegFprs] = htobe(context->readMiscReg(MISCREG_FPRS)); gdbregs.regs[RegY] = htobe(context->readIntReg(NumIntArchRegs + 1)); gdbregs.regs[RegState] = htobe( - context->readMiscRegWithEffect(MISCREG_CWP) | - context->readMiscRegWithEffect(MISCREG_PSTATE) << 8 | - context->readMiscRegWithEffect(MISCREG_ASI) << 24 | + context->readMiscReg(MISCREG_CWP) | + context->readMiscReg(MISCREG_PSTATE) << 8 | + context->readMiscReg(MISCREG_ASI) << 24 | context->readIntReg(NumIntArchRegs + 2) << 32); } diff --git a/src/arch/sparc/stacktrace.cc b/src/arch/sparc/stacktrace.cc index 2eb697bf2..2d7991267 100644 --- a/src/arch/sparc/stacktrace.cc +++ b/src/arch/sparc/stacktrace.cc @@ -146,7 +146,7 @@ namespace SparcISA #if 0 tc = _tc; - bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + bool usermode = (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; Addr pc = tc->readNextPC(); bool kernel = tc->getSystemPtr()->kernelStart <= pc && @@ -221,22 +221,22 @@ namespace SparcISA StackTrace::isEntry(Addr addr) { #if 0 - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp12)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp7)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp11)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp21)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp9)) return true; - if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2)) + if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp2)) return true; #endif return false; diff --git a/src/arch/sparc/syscallreturn.hh b/src/arch/sparc/syscallreturn.hh index d92b12790..cf13fc3e8 100644 --- a/src/arch/sparc/syscallreturn.hh +++ b/src/arch/sparc/syscallreturn.hh @@ -49,13 +49,13 @@ namespace SparcISA // no error, clear XCC.C tc->setIntReg(NumIntArchRegs + 2, tc->readIntReg(NumIntArchRegs + 2) & 0xEE); - //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) & 0xEE); + //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE); tc->setIntReg(ReturnValueReg, return_value.value()); } else { // got an error, set XCC.C tc->setIntReg(NumIntArchRegs + 2, tc->readIntReg(NumIntArchRegs + 2) | 0x11); - //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) | 0x11); + //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11); tc->setIntReg(ReturnValueReg, -return_value.value()); } } diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 41d55158e..c39969769 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -396,7 +396,7 @@ TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, bool se, FaultTypes ft, int asi) { uint64_t sfsr; - sfsr = tc->readMiscReg(reg); + sfsr = tc->readMiscRegNoEffect(reg); if (sfsr & 0x1) sfsr = 0x3; @@ -410,7 +410,7 @@ TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, sfsr |= 1 << 6; sfsr |= ft << 7; sfsr |= asi << 16; - tc->setMiscRegWithEffect(reg, sfsr); + tc->setMiscReg(reg, sfsr); } void @@ -419,7 +419,7 @@ TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", va, context, mbits(va, 63,13) | mbits(context,12,0)); - tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); + tc->setMiscReg(reg, mbits(va, 63,13) | mbits(context,12,0)); } void @@ -444,7 +444,7 @@ DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", a, (int)write, ct, ft, asi); TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); - tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); + tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); } void @@ -458,7 +458,7 @@ DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) Fault ITB::translate(RequestPtr &req, ThreadContext *tc) { - uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); + uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); Addr vaddr = req->getVaddr(); TlbEntry *e; @@ -572,7 +572,7 @@ Fault DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) { /* @todo this could really use some profiling and fixing to make it faster! */ - uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); + uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); Addr vaddr = req->getVaddr(); Addr size = req->getSize(); ASI asi; @@ -864,90 +864,90 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) switch (asi) { case ASI_LSU_CONTROL_REG: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); + pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); break; case ASI_MMU: switch (va) { case 0x8: - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); + pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT)); break; case 0x10: - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); + pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT)); break; default: goto doMmuReadError; } break; case ASI_QUEUE: - pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + + pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + (va >> 4) - 0x3c)); break; case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); + pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0)); break; case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); + pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1)); break; case ASI_DMMU_CTXT_ZERO_CONFIG: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); + pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG)); break; case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); + pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0)); break; case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); + pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1)); break; case ASI_IMMU_CTXT_ZERO_CONFIG: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); + pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG)); break; case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); + pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0)); break; case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); + pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1)); break; case ASI_DMMU_CTXT_NONZERO_CONFIG: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); + pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); break; case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); + pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0)); break; case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); + pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1)); break; case ASI_IMMU_CTXT_NONZERO_CONFIG: assert(va == 0); - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); + pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); break; case ASI_SPARC_ERROR_STATUS_REG: pkt->set((uint64_t)0); break; case ASI_HYP_SCRATCHPAD: case ASI_SCRATCHPAD: - pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); + pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); break; case ASI_IMMU: switch (va) { case 0x0: - temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); + temp = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS); pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); break; case 0x18: - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); + pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_SFSR)); break; case 0x30: - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); + pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS)); break; default: goto doMmuReadError; @@ -956,20 +956,20 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) case ASI_DMMU: switch (va) { case 0x0: - temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); + temp = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS); pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); break; case 0x18: - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); + pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFSR)); break; case 0x20: - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); + pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFAR)); break; case 0x30: - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); + pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS)); break; case 0x80: - pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); + pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); break; default: goto doMmuReadError; @@ -977,35 +977,35 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) break; case ASI_DMMU_TSB_PS0_PTR_REG: pkt->set(MakeTsbPtr(Ps0, - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG))); + tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS), + tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0), + tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), + tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0), + tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG))); break; case ASI_DMMU_TSB_PS1_PTR_REG: pkt->set(MakeTsbPtr(Ps1, - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG))); + tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS), + tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1), + tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), + tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1), + tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG))); break; case ASI_IMMU_TSB_PS0_PTR_REG: pkt->set(MakeTsbPtr(Ps0, - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG))); + tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS), + tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0), + tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), + tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0), + tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG))); break; case ASI_IMMU_TSB_PS1_PTR_REG: pkt->set(MakeTsbPtr(Ps1, - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG))); + tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS), + tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1), + tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), + tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1), + tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG))); break; case ASI_SWVR_INTR_RECEIVE: pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); @@ -1048,15 +1048,15 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) switch (asi) { case ASI_LSU_CONTROL_REG: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); + tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); break; case ASI_MMU: switch (va) { case 0x8: - tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); + tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data); break; case 0x10: - tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); + tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data); break; default: goto doMmuWriteError; @@ -1064,56 +1064,56 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) break; case ASI_QUEUE: assert(mbits(data,13,6) == data); - tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + + tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + (va >> 4) - 0x3c, data); break; case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); + tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0, data); break; case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); + tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1, data); break; case ASI_DMMU_CTXT_ZERO_CONFIG: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); + tc->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG, data); break; case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); + tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0, data); break; case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); + tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1, data); break; case ASI_IMMU_CTXT_ZERO_CONFIG: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); + tc->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG, data); break; case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); + tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0, data); break; case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); + tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1, data); break; case ASI_DMMU_CTXT_NONZERO_CONFIG: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); + tc->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG, data); break; case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); + tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0, data); break; case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); + tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1, data); break; case ASI_IMMU_CTXT_NONZERO_CONFIG: assert(va == 0); - tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); + tc->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG, data); break; case ASI_SPARC_ERROR_EN_REG: case ASI_SPARC_ERROR_STATUS_REG: @@ -1121,16 +1121,16 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) break; case ASI_HYP_SCRATCHPAD: case ASI_SCRATCHPAD: - tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); + tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); break; case ASI_IMMU: switch (va) { case 0x18: - tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); + tc->setMiscReg(MISCREG_MMU_ITLB_SFSR, data); break; case 0x30: sext<59>(bits(data, 59,0)); - tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); + tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, data); break; default: goto doMmuWriteError; @@ -1140,10 +1140,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) entry_insert = bits(va, 8,3); case ASI_ITLB_DATA_IN_REG: assert(entry_insert != -1 || mbits(va,10,9) == va); - ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); + ta_insert = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS); va_insert = mbits(ta_insert, 63,13); ct_insert = mbits(ta_insert, 12,0); - part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); + part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); real_insert = bits(va, 9,9); pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : PageTableEntry::sun4u); @@ -1154,10 +1154,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) entry_insert = bits(va, 8,3); case ASI_DTLB_DATA_IN_REG: assert(entry_insert != -1 || mbits(va,10,9) == va); - ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); + ta_insert = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS); va_insert = mbits(ta_insert, 63,13); ct_insert = mbits(ta_insert, 12,0); - part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); + part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); real_insert = bits(va, 9,9); pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : PageTableEntry::sun4u); @@ -1166,10 +1166,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) case ASI_IMMU_DEMAP: ignore = false; ctx_id = -1; - part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); + part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); switch (bits(va,5,4)) { case 0: - ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); + ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); break; case 1: ignore = true; @@ -1201,14 +1201,14 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) case ASI_DMMU: switch (va) { case 0x18: - tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); + tc->setMiscReg(MISCREG_MMU_DTLB_SFSR, data); break; case 0x30: sext<59>(bits(data, 59,0)); - tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); + tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, data); break; case 0x80: - tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); + tc->setMiscReg(MISCREG_MMU_PART_ID, data); break; default: goto doMmuWriteError; @@ -1217,13 +1217,13 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) case ASI_DMMU_DEMAP: ignore = false; ctx_id = -1; - part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); + part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); switch (bits(va,5,4)) { case 0: - ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); + ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); break; case 1: - ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); + ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT); break; case 3: ctx_id = 0; @@ -1274,25 +1274,25 @@ DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) { uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); ptrs[0] = MakeTsbPtr(Ps0, tag_access, - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); + tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0), + tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), + tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0), + tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); ptrs[1] = MakeTsbPtr(Ps1, tag_access, - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1), - tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); + tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1), + tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), + tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1), + tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); ptrs[2] = MakeTsbPtr(Ps0, tag_access, - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); + tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0), + tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), + tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0), + tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); ptrs[3] = MakeTsbPtr(Ps1, tag_access, - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1), - tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); + tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1), + tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), + tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1), + tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); } diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 5b13cd041..6c8a987fe 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -59,25 +59,24 @@ MiscRegFile::checkSoftInt(ThreadContext *tc) void -MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, - ThreadContext *tc) +MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) { int64_t time; switch (miscReg) { /* Full system only ASRs */ case MISCREG_SOFTINT: - setReg(miscReg, val);; + setRegNoEffect(miscReg, val);; checkSoftInt(tc); break; case MISCREG_SOFTINT_CLR: - return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc); + return setReg(MISCREG_SOFTINT, ~val & softint, tc); case MISCREG_SOFTINT_SET: - return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc); + return setReg(MISCREG_SOFTINT, val | softint, tc); case MISCREG_TICK_CMPR: if (tickCompare == NULL) tickCompare = new TickCompareEvent(this, tc); - setReg(miscReg, val); + setRegNoEffect(miscReg, val); if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) tickCompare->deschedule(); time = (tick_cmpr & mask(63)) - (tick & mask(63)); @@ -92,7 +91,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_STICK_CMPR: if (sTickCompare == NULL) sTickCompare = new STickCompareEvent(this, tc); - setReg(miscReg, val); + setRegNoEffect(miscReg, val); if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) sTickCompare->deschedule(); time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - @@ -106,10 +105,10 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, break; case MISCREG_PSTATE: - setReg(miscReg, val); + setRegNoEffect(miscReg, val); case MISCREG_PIL: - setReg(miscReg, val); + setRegNoEffect(miscReg, val); checkSoftInt(tc); break; @@ -117,7 +116,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, panic("Shouldn't be writing HVER\n"); case MISCREG_HINTP: - setReg(miscReg, val); + setRegNoEffect(miscReg, val); if (hintp) tc->getCpuPtr()->post_interrupt(IT_HINTP,0); else @@ -126,12 +125,12 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_HTBA: // clear lower 7 bits on writes. - setReg(miscReg, val & ULL(~0x7FFF)); + setRegNoEffect(miscReg, val & ULL(~0x7FFF)); break; case MISCREG_QUEUE_CPU_MONDO_HEAD: case MISCREG_QUEUE_CPU_MONDO_TAIL: - setReg(miscReg, val); + setRegNoEffect(miscReg, val); if (cpu_mondo_head != cpu_mondo_tail) tc->getCpuPtr()->post_interrupt(IT_CPU_MONDO,0); else @@ -139,7 +138,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, break; case MISCREG_QUEUE_DEV_MONDO_HEAD: case MISCREG_QUEUE_DEV_MONDO_TAIL: - setReg(miscReg, val); + setRegNoEffect(miscReg, val); if (dev_mondo_head != dev_mondo_tail) tc->getCpuPtr()->post_interrupt(IT_DEV_MONDO,0); else @@ -147,7 +146,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, break; case MISCREG_QUEUE_RES_ERROR_HEAD: case MISCREG_QUEUE_RES_ERROR_TAIL: - setReg(miscReg, val); + setRegNoEffect(miscReg, val); if (res_error_head != res_error_tail) tc->getCpuPtr()->post_interrupt(IT_RES_ERROR,0); else @@ -155,14 +154,14 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, break; case MISCREG_QUEUE_NRES_ERROR_HEAD: case MISCREG_QUEUE_NRES_ERROR_TAIL: - setReg(miscReg, val); + setRegNoEffect(miscReg, val); // This one doesn't have an interrupt to report to the guest OS break; case MISCREG_HSTICK_CMPR: if (hSTickCompare == NULL) hSTickCompare = new HSTickCompareEvent(this, tc); - setReg(miscReg, val); + setRegNoEffect(miscReg, val); if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) hSTickCompare->deschedule(); time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - @@ -177,7 +176,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_HPSTATE: // T1000 spec says impl. dependent val must always be 1 - setReg(miscReg, val | HPSTATE::id); + setRegNoEffect(miscReg, val | HPSTATE::id); #if FULL_SYSTEM if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0); @@ -187,7 +186,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, break; case MISCREG_HTSTATE: case MISCREG_STRAND_STS_REG: - setReg(miscReg, val); + setRegNoEffect(miscReg, val); break; default: @@ -196,7 +195,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, } MiscReg -MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) +MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) { switch (miscReg) { /* Privileged registers. */ @@ -217,10 +216,10 @@ MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) case MISCREG_HTSTATE: case MISCREG_STRAND_STS_REG: case MISCREG_HSTICK_CMPR: - return readReg(miscReg) ; + return readRegNoEffect(miscReg) ; case MISCREG_HTBA: - return readReg(miscReg) & ULL(~0x7FFF); + return readRegNoEffect(miscReg) & ULL(~0x7FFF); case MISCREG_HVER: return NWindows | MaxTL << 8 | MaxGL << 16; @@ -259,8 +258,8 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) if (ticks == 0) { DPRINTF(Timer, "STick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); - if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { - setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); + if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { + setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); } } else sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); @@ -280,8 +279,8 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) if (ticks == 0) { DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); - if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { - setRegWithEffect(MISCREG_HINTP, 1, tc); + if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { + setReg(MISCREG_HINTP, 1, tc); } // Need to do something to cause interrupt to happen here !!! @todo } else diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 3c8bdcd01..64b91695e 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -44,8 +44,8 @@ namespace SparcISA static inline bool inUserMode(ThreadContext *tc) { - return !(tc->readMiscReg(MISCREG_PSTATE & (1 << 2)) || - tc->readMiscReg(MISCREG_HPSTATE & (1 << 2))); + return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) || + tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2))); } inline ExtMachInst @@ -56,7 +56,7 @@ namespace SparcISA //slightly redundant, but it removes the need to put a condition //into all the execute functions if(inst & (1 << 13)) - emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI)) + emi |= (static_cast<ExtMachInst>(xc->readMiscRegNoEffect(MISCREG_ASI)) << (sizeof(MachInst) * 8)); else emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5)) diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc index cb545185a..9a93950d2 100644 --- a/src/arch/sparc/vtophys.cc +++ b/src/arch/sparc/vtophys.cc @@ -66,7 +66,7 @@ namespace SparcISA // 4. We are not priv, use ctxN0* tsbs to find the page // For all accesses we check the tlbs first since it's possible that // long standing pages (e.g. locked kernel mappings) won't be in the tsb - uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); + uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); bool hpriv = bits(tlbdata,0,0); //bool priv = bits(tlbdata,2,2); diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 36ead852d..fff29ba89 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -111,6 +111,10 @@ full_system_sources = Split(''' # Syscall emulation (non-full-system) sources syscall_emulation_sources = Split(''' + linux/linux.cc + linux/process.cc + linux/syscalls.cc + process.cc ''') sources = base_sources diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh new file mode 100644 index 000000000..3fe25bd5f --- /dev/null +++ b/src/arch/x86/intregs.hh @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_INTREGS_HH__ +#define __ARCH_X86_INTREGS_HH__ + +namespace X86ISA +{ + enum IntRegIndex + { + INTREG_RAX, + INTREG_RCX, + INTREG_RDX, + INTREG_RBX, + INTREG_RSP, + INTREG_RBP, + INTREG_RSI, + INTREG_RDI, + INTREG_R8W, + INTREG_R9W, + INTREG_R10W, + INTREG_R11W, + INTREG_R12W, + INTREG_R13W, + INTREG_R14W, + INTREG_R15W + }; +}; + +#endif // __ARCH_X86_INTERRUPTS_HH__ diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index d5da8b420..5a625f741 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -58,6 +58,7 @@ #ifndef __ARCH_X86_ISATRAITS_HH__ #define __ARCH_X86_ISATRAITS_HH__ +#include "arch/x86/intregs.hh" #include "arch/x86/types.hh" #include "arch/x86/x86_traits.hh" @@ -93,21 +94,21 @@ namespace X86ISA // semantically meaningful register indices //There is no such register in X86 const int ZeroReg = 0; - const int StackPointerReg = 4; //RSP + const int StackPointerReg = INTREG_RSP; //X86 doesn't seem to have a link register const int ReturnAddressReg = 0; - const int ReturnValueReg = 0; //RAX - const int FramePointerReg = 5; //RBP - const int ArgumentReg0 = 7; //RDI - const int ArgumentReg1 = 6; //RSI - const int ArgumentReg2 = 2; //RDX - const int ArgumentReg3 = 1; //RCX - const int ArgumentReg4 = 8; //R8W - const int ArgumentReg5 = 9; //R9W + const int ReturnValueReg = INTREG_RAX; + const int FramePointerReg = INTREG_RBP; + const int ArgumentReg0 = INTREG_RDI; + const int ArgumentReg1 = INTREG_RSI; + const int ArgumentReg2 = INTREG_RDX; + const int ArgumentReg3 = INTREG_RCX; + const int ArgumentReg4 = INTREG_R8W; + const int ArgumentReg5 = INTREG_R9W; // Some OS syscalls use a second register (rdx) to return a second // value - const int SyscallPseudoReturnReg = 2; //RDX + const int SyscallPseudoReturnReg = INTREG_RDX; //XXX These numbers are bogus const int MaxInstSrcRegs = 10; diff --git a/src/arch/x86/linux/linux.cc b/src/arch/x86/linux/linux.cc new file mode 100644 index 000000000..59754d7b3 --- /dev/null +++ b/src/arch/x86/linux/linux.cc @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/linux/linux.hh" +#include <fcntl.h> + +// open(2) flags translation table +OpenFlagTransTable X86Linux::openFlagTable[] = { +#ifdef _MSC_VER + { TGT_O_RDONLY, _O_RDONLY }, + { TGT_O_WRONLY, _O_WRONLY }, + { TGT_O_RDWR, _O_RDWR }, + { TGT_O_APPEND, _O_APPEND }, + { TGT_O_CREAT, _O_CREAT }, + { TGT_O_TRUNC, _O_TRUNC }, + { TGT_O_EXCL, _O_EXCL }, +#ifdef _O_NONBLOCK + { TGT_O_NONBLOCK, _O_NONBLOCK }, +#endif +#ifdef _O_NOCTTY + { TGT_O_NOCTTY, _O_NOCTTY }, +#endif +#ifdef _O_SYNC + { TGT_O_SYNC, _O_SYNC }, +#endif +#else /* !_MSC_VER */ + { TGT_O_RDONLY, O_RDONLY }, + { TGT_O_WRONLY, O_WRONLY }, + { TGT_O_RDWR, O_RDWR }, + { TGT_O_APPEND, O_APPEND }, + { TGT_O_CREAT, O_CREAT }, + { TGT_O_TRUNC, O_TRUNC }, + { TGT_O_EXCL, O_EXCL }, + { TGT_O_NONBLOCK, O_NONBLOCK }, + { TGT_O_NOCTTY, O_NOCTTY }, +#ifdef O_SYNC + { TGT_O_SYNC, O_SYNC }, +#endif +#endif /* _MSC_VER */ +}; + +const int X86Linux::NUM_OPEN_FLAGS = + (sizeof(X86Linux::openFlagTable)/sizeof(X86Linux::openFlagTable[0])); + diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh new file mode 100644 index 000000000..a276d4c0c --- /dev/null +++ b/src/arch/x86/linux/linux.hh @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_LINUX_LINUX_HH__ +#define __ARCH_X86_LINUX_LINUX_HH__ + +#include "kern/linux/linux.hh" + +class X86Linux : public Linux +{ + public: + + typedef struct { + uint32_t st_dev; + char __pad1[4]; + uint64_t st_ino; + uint32_t st_mode; + uint16_t st_nlink; + uint32_t st_uid; + uint32_t st_gid; + uint32_t st_rdev; + char __pad2[4]; + int64_t st_size; + int64_t st_atimeX; + int64_t st_mtimeX; + int64_t st_ctimeX; + int64_t st_blksize; + int64_t st_blocks; + uint64_t __unused4[2]; + } tgt_stat; + + static OpenFlagTransTable openFlagTable[]; + + static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY + static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY + static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR + static const int TGT_O_NONBLOCK = 0x00004000; //!< O_NONBLOCK + static const int TGT_O_APPEND = 0x00000008; //!< O_APPEND + static const int TGT_O_CREAT = 0x00000200; //!< O_CREAT + static const int TGT_O_TRUNC = 0x00000400; //!< O_TRUNC + static const int TGT_O_EXCL = 0x00000800; //!< O_EXCL + static const int TGT_O_NOCTTY = 0x00008000; //!< O_NOCTTY + static const int TGT_O_SYNC = 0x00002000; //!< O_SYNC +// static const int TGT_O_DRD = 0x00010000; //!< O_DRD +// static const int TGT_O_DIRECTIO = 0x00020000; //!< O_DIRECTIO +// static const int TGT_O_CACHE = 0x00002000; //!< O_CACHE +// static const int TGT_O_DSYNC = 0x00008000; //!< O_DSYNC +// static const int TGT_O_RSYNC = 0x00040000; //!< O_RSYNC + + static const int NUM_OPEN_FLAGS; + + static const unsigned TGT_MAP_ANONYMOUS = 0x20; +}; + +#endif diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc new file mode 100644 index 000000000..9ef591a1c --- /dev/null +++ b/src/arch/x86/linux/process.cc @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/isa_traits.hh" +#include "arch/x86/linux/process.hh" +#include "arch/x86/regfile.hh" + +#include "base/trace.hh" +#include "cpu/thread_context.hh" +#include "kern/linux/linux.hh" + +#include "sim/process.hh" +#include "sim/syscall_emul.hh" + +using namespace std; +using namespace X86ISA; + +SyscallDesc* +X86LinuxProcess::getDesc(int callnum) +{ + if (callnum < 0 || callnum > Num_Syscall_Descs) + return NULL; + return &syscallDescs[callnum]; +} + +X86LinuxProcess::X86LinuxProcess(const std::string &name, + ObjectFile *objFile, + System * system, + int stdin_fd, + int stdout_fd, + int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp, + const std::string &cwd, + uint64_t _uid, uint64_t _euid, + uint64_t _gid, uint64_t _egid, + uint64_t _pid, uint64_t _ppid) + : X86LiveProcess(name, objFile, system, + stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd, + _uid, _euid, _gid, _egid, _pid, _ppid), + Num_Syscall_Descs(273) +{} + +void X86LinuxProcess::handleTrap(int trapNum, ThreadContext *tc) +{ + switch(trapNum) + { + //This implementation is from SPARC + case 0x10: //Linux 32 bit syscall trap + tc->syscall(tc->readIntReg(1)); + break; + default: + X86LiveProcess::handleTrap(trapNum, tc); + } +} diff --git a/src/arch/x86/linux/process.hh b/src/arch/x86/linux/process.hh new file mode 100644 index 000000000..7e7236f0d --- /dev/null +++ b/src/arch/x86/linux/process.hh @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __X86_LINUX_PROCESS_HH__ +#define __X86_LINUX_PROCESS_HH__ + +#include "sim/process.hh" +#include "arch/x86/linux/linux.hh" +#include "arch/x86/syscallreturn.hh" +#include "arch/x86/process.hh" + +namespace X86ISA { + +/// A process with emulated x86/Linux syscalls. +class X86LinuxProcess : public X86LiveProcess +{ + public: + /// Constructor. + X86LinuxProcess(const std::string &name, + ObjectFile *objFile, + System * system, + int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp, + const std::string &cwd, + uint64_t _uid, uint64_t _euid, + uint64_t _gid, uint64_t _egid, + uint64_t _pid, uint64_t _ppid); + + /// Array of syscall descriptors, indexed by call number. + static SyscallDesc syscallDescs[]; + + SyscallDesc* getDesc(int callnum); + + const int Num_Syscall_Descs; + + void handleTrap(int trapNum, ThreadContext *tc); +}; + +} // namespace X86ISA +#endif // __X86_LINUX_PROCESS_HH__ diff --git a/src/arch/x86/linux/syscalls.cc b/src/arch/x86/linux/syscalls.cc new file mode 100644 index 000000000..809784635 --- /dev/null +++ b/src/arch/x86/linux/syscalls.cc @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/linux/process.hh" +#include "kern/linux/linux.hh" +#include "sim/syscall_emul.hh" + +using namespace X86ISA; + +/// Target uname() handler. +static SyscallReturn +unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process, + ThreadContext *tc) +{ + TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0)); + + strcpy(name->sysname, "Linux"); + strcpy(name->nodename, "m5.eecs.umich.edu"); + strcpy(name->release, "2.6.12"); + strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); + strcpy(name->machine, "x86_64"); + + name.copyOut(tc->getMemPort()); + + return 0; +} + +SyscallDesc X86LinuxProcess::syscallDescs[] = { + /* 0 */ SyscallDesc("read", unimplementedFunc), + /* 1 */ SyscallDesc("write", unimplementedFunc), + /* 2 */ SyscallDesc("open", unimplementedFunc), + /* 3 */ SyscallDesc("close", unimplementedFunc), + /* 4 */ SyscallDesc("stat", unimplementedFunc), + /* 5 */ SyscallDesc("fstat", unimplementedFunc), + /* 6 */ SyscallDesc("lstat", unimplementedFunc), + /* 7 */ SyscallDesc("poll", unimplementedFunc), + /* 8 */ SyscallDesc("lseek", unimplementedFunc), + /* 9 */ SyscallDesc("mmap", unimplementedFunc), + /* 10 */ SyscallDesc("mprotect", unimplementedFunc), + /* 11 */ SyscallDesc("munmap", unimplementedFunc), + /* 12 */ SyscallDesc("brk", unimplementedFunc), + /* 13 */ SyscallDesc("rt_sigaction", unimplementedFunc), + /* 14 */ SyscallDesc("rt_sigprocmask", unimplementedFunc), + /* 15 */ SyscallDesc("rt_sigreturn", unimplementedFunc), + /* 16 */ SyscallDesc("ioctl", unimplementedFunc), + /* 17 */ SyscallDesc("pread64", unimplementedFunc), + /* 18 */ SyscallDesc("pwrite64", unimplementedFunc), + /* 19 */ SyscallDesc("readv", unimplementedFunc), + /* 20 */ SyscallDesc("writev", unimplementedFunc), + /* 21 */ SyscallDesc("access", unimplementedFunc), + /* 22 */ SyscallDesc("pipe", unimplementedFunc), + /* 23 */ SyscallDesc("select", unimplementedFunc), + /* 24 */ SyscallDesc("sched_yield", unimplementedFunc), + /* 25 */ SyscallDesc("mremap", unimplementedFunc), + /* 26 */ SyscallDesc("msync", unimplementedFunc), + /* 27 */ SyscallDesc("mincore", unimplementedFunc), + /* 28 */ SyscallDesc("madvise", unimplementedFunc), + /* 29 */ SyscallDesc("shmget", unimplementedFunc), + /* 30 */ SyscallDesc("shmat", unimplementedFunc), + /* 31 */ SyscallDesc("shmctl", unimplementedFunc), + /* 32 */ SyscallDesc("dup", unimplementedFunc), + /* 33 */ SyscallDesc("dup2", unimplementedFunc), + /* 34 */ SyscallDesc("pause", unimplementedFunc), + /* 35 */ SyscallDesc("nanosleep", unimplementedFunc), + /* 36 */ SyscallDesc("getitimer", unimplementedFunc), + /* 37 */ SyscallDesc("alarm", unimplementedFunc), + /* 38 */ SyscallDesc("setitimer", unimplementedFunc), + /* 39 */ SyscallDesc("getpid", unimplementedFunc), + /* 40 */ SyscallDesc("sendfile", unimplementedFunc), + /* 41 */ SyscallDesc("socket", unimplementedFunc), + /* 42 */ SyscallDesc("connect", unimplementedFunc), + /* 43 */ SyscallDesc("accept", unimplementedFunc), + /* 44 */ SyscallDesc("sendto", unimplementedFunc), + /* 45 */ SyscallDesc("recvfrom", unimplementedFunc), + /* 46 */ SyscallDesc("sendmsg", unimplementedFunc), + /* 47 */ SyscallDesc("recvmsg", unimplementedFunc), + /* 48 */ SyscallDesc("shutdown", unimplementedFunc), + /* 49 */ SyscallDesc("bind", unimplementedFunc), + /* 50 */ SyscallDesc("listen", unimplementedFunc), + /* 51 */ SyscallDesc("getsockname", unimplementedFunc), + /* 52 */ SyscallDesc("getpeername", unimplementedFunc), + /* 53 */ SyscallDesc("socketpair", unimplementedFunc), + /* 54 */ SyscallDesc("setsockopt", unimplementedFunc), + /* 55 */ SyscallDesc("getsockopt", unimplementedFunc), + /* 56 */ SyscallDesc("clone", unimplementedFunc), + /* 57 */ SyscallDesc("fork", unimplementedFunc), + /* 58 */ SyscallDesc("vfork", unimplementedFunc), + /* 59 */ SyscallDesc("execve", unimplementedFunc), + /* 60 */ SyscallDesc("exit", unimplementedFunc), + /* 61 */ SyscallDesc("wait4", unimplementedFunc), + /* 62 */ SyscallDesc("kill", unimplementedFunc), + /* 63 */ SyscallDesc("uname", unameFunc), + /* 64 */ SyscallDesc("semget", unimplementedFunc), + /* 65 */ SyscallDesc("semop", unimplementedFunc), + /* 66 */ SyscallDesc("semctl", unimplementedFunc), + /* 67 */ SyscallDesc("shmdt", unimplementedFunc), + /* 68 */ SyscallDesc("msgget", unimplementedFunc), + /* 69 */ SyscallDesc("msgsnd", unimplementedFunc), + /* 70 */ SyscallDesc("msgrcv", unimplementedFunc), + /* 71 */ SyscallDesc("msgctl", unimplementedFunc), + /* 72 */ SyscallDesc("fcntl", unimplementedFunc), + /* 73 */ SyscallDesc("flock", unimplementedFunc), + /* 74 */ SyscallDesc("fsync", unimplementedFunc), + /* 75 */ SyscallDesc("fdatasync", unimplementedFunc), + /* 76 */ SyscallDesc("truncate", unimplementedFunc), + /* 77 */ SyscallDesc("ftruncate", unimplementedFunc), + /* 78 */ SyscallDesc("getdents", unimplementedFunc), + /* 79 */ SyscallDesc("getcwd", unimplementedFunc), + /* 80 */ SyscallDesc("chdir", unimplementedFunc), + /* 81 */ SyscallDesc("fchdir", unimplementedFunc), + /* 82 */ SyscallDesc("rename", unimplementedFunc), + /* 83 */ SyscallDesc("mkdir", unimplementedFunc), + /* 84 */ SyscallDesc("rmdir", unimplementedFunc), + /* 85 */ SyscallDesc("creat", unimplementedFunc), + /* 86 */ SyscallDesc("link", unimplementedFunc), + /* 87 */ SyscallDesc("unlink", unimplementedFunc), + /* 88 */ SyscallDesc("symlink", unimplementedFunc), + /* 89 */ SyscallDesc("readlink", unimplementedFunc), + /* 90 */ SyscallDesc("chmod", unimplementedFunc), + /* 91 */ SyscallDesc("fchmod", unimplementedFunc), + /* 92 */ SyscallDesc("chown", unimplementedFunc), + /* 93 */ SyscallDesc("fchown", unimplementedFunc), + /* 94 */ SyscallDesc("lchown", unimplementedFunc), + /* 95 */ SyscallDesc("umask", unimplementedFunc), + /* 96 */ SyscallDesc("gettimeofday", unimplementedFunc), + /* 97 */ SyscallDesc("getrlimit", unimplementedFunc), + /* 98 */ SyscallDesc("getrusage", unimplementedFunc), + /* 99 */ SyscallDesc("sysinfo", unimplementedFunc), + /* 100 */ SyscallDesc("times", unimplementedFunc), + /* 101 */ SyscallDesc("ptrace", unimplementedFunc), + /* 102 */ SyscallDesc("getuid", unimplementedFunc), + /* 103 */ SyscallDesc("syslog", unimplementedFunc), + /* 104 */ SyscallDesc("getgid", unimplementedFunc), + /* 105 */ SyscallDesc("setuid", unimplementedFunc), + /* 106 */ SyscallDesc("setgid", unimplementedFunc), + /* 107 */ SyscallDesc("geteuid", unimplementedFunc), + /* 108 */ SyscallDesc("getegid", unimplementedFunc), + /* 109 */ SyscallDesc("setpgid", unimplementedFunc), + /* 110 */ SyscallDesc("getppid", unimplementedFunc), + /* 111 */ SyscallDesc("getpgrp", unimplementedFunc), + /* 112 */ SyscallDesc("setsid", unimplementedFunc), + /* 113 */ SyscallDesc("setreuid", unimplementedFunc), + /* 114 */ SyscallDesc("setregid", unimplementedFunc), + /* 115 */ SyscallDesc("getgroups", unimplementedFunc), + /* 116 */ SyscallDesc("setgroups", unimplementedFunc), + /* 117 */ SyscallDesc("setresuid", unimplementedFunc), + /* 118 */ SyscallDesc("getresuid", unimplementedFunc), + /* 119 */ SyscallDesc("setresgid", unimplementedFunc), + /* 120 */ SyscallDesc("getresgid", unimplementedFunc), + /* 121 */ SyscallDesc("getpgid", unimplementedFunc), + /* 122 */ SyscallDesc("setfsuid", unimplementedFunc), + /* 123 */ SyscallDesc("setfsgid", unimplementedFunc), + /* 124 */ SyscallDesc("getsid", unimplementedFunc), + /* 125 */ SyscallDesc("capget", unimplementedFunc), + /* 126 */ SyscallDesc("capset", unimplementedFunc), + /* 127 */ SyscallDesc("rt_sigpending", unimplementedFunc), + /* 128 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc), + /* 129 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc), + /* 130 */ SyscallDesc("rt_sigsuspend", unimplementedFunc), + /* 131 */ SyscallDesc("sigaltstack", unimplementedFunc), + /* 132 */ SyscallDesc("utime", unimplementedFunc), + /* 133 */ SyscallDesc("mknod", unimplementedFunc), + /* 134 */ SyscallDesc("uselib", unimplementedFunc), + /* 135 */ SyscallDesc("personality", unimplementedFunc), + /* 136 */ SyscallDesc("ustat", unimplementedFunc), + /* 137 */ SyscallDesc("statfs", unimplementedFunc), + /* 138 */ SyscallDesc("fstatfs", unimplementedFunc), + /* 139 */ SyscallDesc("sysfs", unimplementedFunc), + /* 140 */ SyscallDesc("getpriority", unimplementedFunc), + /* 141 */ SyscallDesc("setpriority", unimplementedFunc), + /* 142 */ SyscallDesc("sched_setparam", unimplementedFunc), + /* 143 */ SyscallDesc("sched_getparam", unimplementedFunc), + /* 144 */ SyscallDesc("sched_setscheduler", unimplementedFunc), + /* 145 */ SyscallDesc("sched_getscheduler", unimplementedFunc), + /* 146 */ SyscallDesc("sched_get_priority_max", unimplementedFunc), + /* 147 */ SyscallDesc("sched_get_priority_min", unimplementedFunc), + /* 148 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc), + /* 149 */ SyscallDesc("mlock", unimplementedFunc), + /* 150 */ SyscallDesc("munlock", unimplementedFunc), + /* 151 */ SyscallDesc("mlockall", unimplementedFunc), + /* 152 */ SyscallDesc("munlockall", unimplementedFunc), + /* 153 */ SyscallDesc("vhangup", unimplementedFunc), + /* 154 */ SyscallDesc("modify_ldt", unimplementedFunc), + /* 155 */ SyscallDesc("pivot_root", unimplementedFunc), + /* 156 */ SyscallDesc("_sysctl", unimplementedFunc), + /* 157 */ SyscallDesc("prctl", unimplementedFunc), + /* 158 */ SyscallDesc("arch_prctl", unimplementedFunc), + /* 159 */ SyscallDesc("adjtimex", unimplementedFunc), + /* 160 */ SyscallDesc("setrlimit", unimplementedFunc), + /* 161 */ SyscallDesc("chroot", unimplementedFunc), + /* 162 */ SyscallDesc("sync", unimplementedFunc), + /* 163 */ SyscallDesc("acct", unimplementedFunc), + /* 164 */ SyscallDesc("settimeofday", unimplementedFunc), + /* 165 */ SyscallDesc("mount", unimplementedFunc), + /* 166 */ SyscallDesc("umount2", unimplementedFunc), + /* 167 */ SyscallDesc("swapon", unimplementedFunc), + /* 168 */ SyscallDesc("swapoff", unimplementedFunc), + /* 169 */ SyscallDesc("reboot", unimplementedFunc), + /* 170 */ SyscallDesc("sethostname", unimplementedFunc), + /* 171 */ SyscallDesc("setdomainname", unimplementedFunc), + /* 172 */ SyscallDesc("iopl", unimplementedFunc), + /* 173 */ SyscallDesc("ioperm", unimplementedFunc), + /* 174 */ SyscallDesc("create_module", unimplementedFunc), + /* 175 */ SyscallDesc("init_module", unimplementedFunc), + /* 176 */ SyscallDesc("delete_module", unimplementedFunc), + /* 177 */ SyscallDesc("get_kernel_syms", unimplementedFunc), + /* 178 */ SyscallDesc("query_module", unimplementedFunc), + /* 179 */ SyscallDesc("quotactl", unimplementedFunc), + /* 180 */ SyscallDesc("nfsservctl", unimplementedFunc), + /* 181 */ SyscallDesc("getpmsg", unimplementedFunc), + /* 182 */ SyscallDesc("putpmsg", unimplementedFunc), + /* 183 */ SyscallDesc("afs_syscall", unimplementedFunc), + /* 184 */ SyscallDesc("tuxcall", unimplementedFunc), + /* 185 */ SyscallDesc("security", unimplementedFunc), + /* 186 */ SyscallDesc("gettid", unimplementedFunc), + /* 187 */ SyscallDesc("readahead", unimplementedFunc), + /* 188 */ SyscallDesc("setxattr", unimplementedFunc), + /* 189 */ SyscallDesc("lsetxattr", unimplementedFunc), + /* 190 */ SyscallDesc("fsetxattr", unimplementedFunc), + /* 191 */ SyscallDesc("getxattr", unimplementedFunc), + /* 192 */ SyscallDesc("lgetxattr", unimplementedFunc), + /* 193 */ SyscallDesc("fgetxattr", unimplementedFunc), + /* 194 */ SyscallDesc("listxattr", unimplementedFunc), + /* 195 */ SyscallDesc("llistxattr", unimplementedFunc), + /* 196 */ SyscallDesc("flistxattr", unimplementedFunc), + /* 197 */ SyscallDesc("removexattr", unimplementedFunc), + /* 198 */ SyscallDesc("lremovexattr", unimplementedFunc), + /* 199 */ SyscallDesc("fremovexattr", unimplementedFunc), + /* 200 */ SyscallDesc("tkill", unimplementedFunc), + /* 201 */ SyscallDesc("time", unimplementedFunc), + /* 202 */ SyscallDesc("futex", unimplementedFunc), + /* 203 */ SyscallDesc("sched_setaffinity", unimplementedFunc), + /* 204 */ SyscallDesc("sched_getaffinity", unimplementedFunc), + /* 205 */ SyscallDesc("set_thread_area", unimplementedFunc), + /* 206 */ SyscallDesc("io_setup", unimplementedFunc), + /* 207 */ SyscallDesc("io_destroy", unimplementedFunc), + /* 208 */ SyscallDesc("io_getevents", unimplementedFunc), + /* 209 */ SyscallDesc("io_submit", unimplementedFunc), + /* 210 */ SyscallDesc("io_cancel", unimplementedFunc), + /* 211 */ SyscallDesc("get_thread_area", unimplementedFunc), + /* 212 */ SyscallDesc("lookup_dcookie", unimplementedFunc), + /* 213 */ SyscallDesc("epoll_create", unimplementedFunc), + /* 214 */ SyscallDesc("epoll_ctl_old", unimplementedFunc), + /* 215 */ SyscallDesc("epoll_wait_old", unimplementedFunc), + /* 216 */ SyscallDesc("remap_file_pages", unimplementedFunc), + /* 217 */ SyscallDesc("getdents64", unimplementedFunc), + /* 218 */ SyscallDesc("set_tid_address", unimplementedFunc), + /* 219 */ SyscallDesc("restart_syscall", unimplementedFunc), + /* 220 */ SyscallDesc("semtimedop", unimplementedFunc), + /* 221 */ SyscallDesc("fadvise64", unimplementedFunc), + /* 222 */ SyscallDesc("timer_create", unimplementedFunc), + /* 223 */ SyscallDesc("timer_settime", unimplementedFunc), + /* 224 */ SyscallDesc("timer_gettime", unimplementedFunc), + /* 225 */ SyscallDesc("timer_getoverrun", unimplementedFunc), + /* 226 */ SyscallDesc("timer_delete", unimplementedFunc), + /* 227 */ SyscallDesc("clock_settime", unimplementedFunc), + /* 228 */ SyscallDesc("clock_gettime", unimplementedFunc), + /* 229 */ SyscallDesc("clock_getres", unimplementedFunc), + /* 230 */ SyscallDesc("clock_nanosleep", unimplementedFunc), + /* 231 */ SyscallDesc("exit_group", unimplementedFunc), + /* 232 */ SyscallDesc("epoll_wait", unimplementedFunc), + /* 233 */ SyscallDesc("epoll_ctl", unimplementedFunc), + /* 234 */ SyscallDesc("tgkill", unimplementedFunc), + /* 235 */ SyscallDesc("utimes", unimplementedFunc), + /* 236 */ SyscallDesc("vserver", unimplementedFunc), + /* 237 */ SyscallDesc("mbind", unimplementedFunc), + /* 238 */ SyscallDesc("set_mempolicy", unimplementedFunc), + /* 239 */ SyscallDesc("get_mempolicy", unimplementedFunc), + /* 240 */ SyscallDesc("mq_open", unimplementedFunc), + /* 241 */ SyscallDesc("mq_unlink", unimplementedFunc), + /* 242 */ SyscallDesc("mq_timedsend", unimplementedFunc), + /* 243 */ SyscallDesc("mq_timedreceive", unimplementedFunc), + /* 244 */ SyscallDesc("mq_notify", unimplementedFunc), + /* 245 */ SyscallDesc("mq_getsetattr", unimplementedFunc), + /* 246 */ SyscallDesc("kexec_load", unimplementedFunc), + /* 247 */ SyscallDesc("waitid", unimplementedFunc), + /* 248 */ SyscallDesc("add_key", unimplementedFunc), + /* 249 */ SyscallDesc("request_key", unimplementedFunc), + /* 250 */ SyscallDesc("keyctl", unimplementedFunc), + /* 251 */ SyscallDesc("ioprio_set", unimplementedFunc), + /* 252 */ SyscallDesc("ioprio_get", unimplementedFunc), + /* 253 */ SyscallDesc("inotify_init", unimplementedFunc), + /* 254 */ SyscallDesc("inotify_add_watch", unimplementedFunc), + /* 255 */ SyscallDesc("inotify_rm_watch", unimplementedFunc), + /* 256 */ SyscallDesc("migrate_pages", unimplementedFunc), + /* 257 */ SyscallDesc("openat", unimplementedFunc), + /* 258 */ SyscallDesc("mkdirat", unimplementedFunc), + /* 259 */ SyscallDesc("mknodat", unimplementedFunc), + /* 260 */ SyscallDesc("fchownat", unimplementedFunc), + /* 261 */ SyscallDesc("futimesat", unimplementedFunc), + /* 262 */ SyscallDesc("newfstatat", unimplementedFunc), + /* 263 */ SyscallDesc("unlinkat", unimplementedFunc), + /* 264 */ SyscallDesc("renameat", unimplementedFunc), + /* 265 */ SyscallDesc("linkat", unimplementedFunc), + /* 266 */ SyscallDesc("symlinkat", unimplementedFunc), + /* 267 */ SyscallDesc("readlinkat", unimplementedFunc), + /* 268 */ SyscallDesc("fchmodat", unimplementedFunc), + /* 269 */ SyscallDesc("faccessat", unimplementedFunc), + /* 270 */ SyscallDesc("pselect6", unimplementedFunc), + /* 271 */ SyscallDesc("ppoll", unimplementedFunc), + /* 272 */ SyscallDesc("unshare", unimplementedFunc) +}; diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc index bfd3ded5d..14ba3c7cc 100644 --- a/src/arch/x86/miscregfile.cc +++ b/src/arch/x86/miscregfile.cc @@ -100,25 +100,25 @@ string X86ISA::getMiscRegName(RegIndex index) void MiscRegFile::clear() { - panic("No misc registers in x86 yet!\n"); + //When there are actually misc regs implemented, this will clear them } -MiscReg MiscRegFile::readReg(int miscReg) +MiscReg MiscRegFile::readRegNoEffect(int miscReg) { panic("No misc registers in x86 yet!\n"); } -MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) +MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc) { panic("No misc registers in x86 yet!\n"); } -void MiscRegFile::setReg(int miscReg, const MiscReg &val) +void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val) { panic("No misc registers in x86 yet!\n"); } -void MiscRegFile::setRegWithEffect(int miscReg, +void MiscRegFile::setReg(int miscReg, const MiscReg &val, ThreadContext * tc) { panic("No misc registers in x86 yet!\n"); diff --git a/src/arch/x86/miscregfile.hh b/src/arch/x86/miscregfile.hh index be04cd528..10acb97a4 100644 --- a/src/arch/x86/miscregfile.hh +++ b/src/arch/x86/miscregfile.hh @@ -113,13 +113,13 @@ namespace X86ISA clear(); } - MiscReg readReg(int miscReg); + MiscReg readRegNoEffect(int miscReg); - MiscReg readRegWithEffect(int miscReg, ThreadContext *tc); + MiscReg readReg(int miscReg, ThreadContext *tc); - void setReg(int miscReg, const MiscReg &val); + void setRegNoEffect(int miscReg, const MiscReg &val); - void setRegWithEffect(int miscReg, + void setReg(int miscReg, const MiscReg &val, ThreadContext *tc); void serialize(std::ostream & os); diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc new file mode 100644 index 000000000..e6d1e4921 --- /dev/null +++ b/src/arch/x86/process.cc @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2003-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + * Ali Saidi + */ + +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/isa_traits.hh" +#include "arch/x86/process.hh" +#include "arch/x86/types.hh" +#include "base/loader/object_file.hh" +#include "base/loader/elf_object.hh" +#include "base/misc.hh" +#include "cpu/thread_context.hh" +#include "mem/page_table.hh" +#include "mem/translating_port.hh" +#include "sim/system.hh" + +using namespace std; +using namespace X86ISA; + +M5_64_auxv_t::M5_64_auxv_t(int64_t type, int64_t val) +{ + a_type = TheISA::htog(type); + a_val = TheISA::htog(val); +} + +X86LiveProcess::X86LiveProcess(const std::string &nm, ObjectFile *objFile, + System *_system, int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, std::vector<std::string> &envp, + const std::string &cwd, + uint64_t _uid, uint64_t _euid, uint64_t _gid, uint64_t _egid, + uint64_t _pid, uint64_t _ppid) + : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd, + argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid) +{ + brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); + brk_point = roundUp(brk_point, VMPageSize); + + // Set pointer for next thread stack. Reserve 8M for main stack. + next_thread_stack_base = stack_base - (8 * 1024 * 1024); + + // Set up stack. On SPARC Linux, stack goes from the top of memory + // downward, less the hole for the kernel address space. + stack_base = (Addr)0x80000000000ULL; + + // Set up region for mmaps. Tru64 seems to start just above 0 and + // grow up from there. + mmap_start = mmap_end = 0xfffff80000000000ULL; +} + +void X86LiveProcess::handleTrap(int trapNum, ThreadContext *tc) +{ + switch(trapNum) + { + default: + panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); + } +} + +void +X86LiveProcess::startup() +{ + argsInit(sizeof(IntReg), VMPageSize); + + //The AMD64 abi says that only rsp and rdx are defined at process + //startup. rsp will be set by argsInit, and I don't understand what + //rdx should be set to. The other floating point and integer registers + //will be zeroed by the register file constructors, but control registers + //should be initialized here. Since none of those are implemented, there + //isn't anything here. +} + +void +X86LiveProcess::argsInit(int intSize, int pageSize) +{ + typedef M5_64_auxv_t auxv_t; + Process::startup(); + + string filename; + if(argv.size() < 1) + filename = ""; + else + filename = argv[0]; + + Addr alignmentMask = ~(intSize - 1); + + // load object file into target memory + objFile->loadSections(initVirtMem); + + //These are the auxilliary vector types + enum auxTypes + { + X86_AT_NULL = 0, + X86_AT_IGNORE = 1, + X86_AT_EXECFD = 2, + X86_AT_PHDR = 3, + X86_AT_PHENT = 4, + X86_AT_PHNUM = 5, + X86_AT_PAGESZ = 6, + X86_AT_BASE = 7, + X86_AT_FLAGS = 8, + X86_AT_ENTRY = 9, + X86_AT_NOTELF = 10, + X86_AT_UID = 11, + X86_AT_EUID = 12, + X86_AT_GID = 13, + X86_AT_EGID = 14 + }; + + //Setup the auxilliary vectors. These will already have endian conversion. + //Auxilliary vectors are loaded only for elf formatted executables. + ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); + if(elfObject) + { + /* + //Bits which describe the system hardware capabilities + auxv.push_back(auxv_t(SPARC_AT_HWCAP, hwcap)); + //The system page size + auxv.push_back(auxv_t(SPARC_AT_PAGESZ, SparcISA::VMPageSize)); + //Defined to be 100 in the kernel source. + //Frequency at which times() increments + auxv.push_back(auxv_t(SPARC_AT_CLKTCK, 100)); + // For statically linked executables, this is the virtual address of the + // program header tables if they appear in the executable image + auxv.push_back(auxv_t(SPARC_AT_PHDR, elfObject->programHeaderTable())); + // This is the size of a program header entry from the elf file. + auxv.push_back(auxv_t(SPARC_AT_PHENT, elfObject->programHeaderSize())); + // This is the number of program headers from the original elf file. + auxv.push_back(auxv_t(SPARC_AT_PHNUM, elfObject->programHeaderCount())); + //This is the address of the elf "interpreter", It should be set + //to 0 for regular executables. It should be something else + //(not sure what) for dynamic libraries. + auxv.push_back(auxv_t(SPARC_AT_BASE, 0)); + //This is hardwired to 0 in the elf loading code in the kernel + auxv.push_back(auxv_t(SPARC_AT_FLAGS, 0)); + //The entry point to the program + auxv.push_back(auxv_t(SPARC_AT_ENTRY, objFile->entryPoint())); + //Different user and group IDs + auxv.push_back(auxv_t(SPARC_AT_UID, uid())); + auxv.push_back(auxv_t(SPARC_AT_EUID, euid())); + auxv.push_back(auxv_t(SPARC_AT_GID, gid())); + auxv.push_back(auxv_t(SPARC_AT_EGID, egid())); + //Whether to enable "secure mode" in the executable + auxv.push_back(auxv_t(SPARC_AT_SECURE, 0));*/ + } + + //Figure out how big the initial stack needs to be + + // The unaccounted for 0 at the top of the stack + int mysterious_size = intSize; + + //This is the name of the file which is present on the initial stack + //It's purpose is to let the user space linker examine the original file. + int file_name_size = filename.size() + 1; + + int env_data_size = 0; + for (int i = 0; i < envp.size(); ++i) { + env_data_size += envp[i].size() + 1; + } + int arg_data_size = 0; + for (int i = 0; i < argv.size(); ++i) { + arg_data_size += argv[i].size() + 1; + } + + //The info_block needs to be padded so it's size is a multiple of the + //alignment mask. Also, it appears that there needs to be at least some + //padding, so if the size is already a multiple, we need to increase it + //anyway. + int info_block_size = + (file_name_size + + env_data_size + + arg_data_size + + intSize) & alignmentMask; + + int info_block_padding = + info_block_size - + file_name_size - + env_data_size - + arg_data_size; + + //Each auxilliary vector is two 8 byte words + int aux_array_size = intSize * 2 * (auxv.size() + 1); + + int envp_array_size = intSize * (envp.size() + 1); + int argv_array_size = intSize * (argv.size() + 1); + + int argc_size = intSize; + int window_save_size = intSize * 16; + + int space_needed = + mysterious_size + + info_block_size + + aux_array_size + + envp_array_size + + argv_array_size + + argc_size + + window_save_size; + + stack_min = stack_base - space_needed; + stack_min &= alignmentMask; + stack_size = stack_base - stack_min; + + // map memory + pTable->allocate(roundDown(stack_min, pageSize), + roundUp(stack_size, pageSize)); + + // map out initial stack contents + Addr mysterious_base = stack_base - mysterious_size; + Addr file_name_base = mysterious_base - file_name_size; + Addr env_data_base = file_name_base - env_data_size; + Addr arg_data_base = env_data_base - arg_data_size; + Addr auxv_array_base = arg_data_base - aux_array_size - info_block_padding; + Addr envp_array_base = auxv_array_base - envp_array_size; + Addr argv_array_base = envp_array_base - argv_array_size; + Addr argc_base = argv_array_base - argc_size; +#ifndef NDEBUG + // only used in DPRINTF + Addr window_save_base = argc_base - window_save_size; +#endif + + DPRINTF(X86, "The addresses of items on the initial stack:\n"); + DPRINTF(X86, "0x%x - file name\n", file_name_base); + DPRINTF(X86, "0x%x - env data\n", env_data_base); + DPRINTF(X86, "0x%x - arg data\n", arg_data_base); + DPRINTF(X86, "0x%x - auxv array\n", auxv_array_base); + DPRINTF(X86, "0x%x - envp array\n", envp_array_base); + DPRINTF(X86, "0x%x - argv array\n", argv_array_base); + DPRINTF(X86, "0x%x - argc \n", argc_base); + DPRINTF(X86, "0x%x - window save\n", window_save_base); + DPRINTF(X86, "0x%x - stack min\n", stack_min); + + // write contents to stack + + // figure out argc + uint64_t argc = argv.size(); + uint64_t guestArgc = TheISA::htog(argc); + + //Write out the mysterious 0 + uint64_t mysterious_zero = 0; + initVirtMem->writeBlob(mysterious_base, + (uint8_t*)&mysterious_zero, mysterious_size); + + //Write the file name + initVirtMem->writeString(file_name_base, filename.c_str()); + + //Copy the aux stuff + for(int x = 0; x < auxv.size(); x++) + { + initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, + (uint8_t*)&(auxv[x].a_type), intSize); + initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, + (uint8_t*)&(auxv[x].a_val), intSize); + } + //Write out the terminating zeroed auxilliary vector + const uint64_t zero = 0; + initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(), + (uint8_t*)&zero, 2 * intSize); + + copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); + copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); + + initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); + + //Set up the thread context to start running the process + threadContexts[0]->setIntReg(ArgumentReg0, argc); + threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + threadContexts[0]->setIntReg(StackPointerReg, stack_min); + + Addr prog_entry = objFile->entryPoint(); + threadContexts[0]->setPC(prog_entry); + threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); + + //Align the "stack_min" to a page boundary. + stack_min = roundDown(stack_min, pageSize); + +// num_processes++; +} diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh index 92bb86c29..a2fa258c8 100644 --- a/src/arch/x86/process.hh +++ b/src/arch/x86/process.hh @@ -58,10 +58,51 @@ #ifndef __ARCH_X86_PROCESS_HH__ #define __ARCH_X86_PROCESS_HH__ -#error X86 is not yet supported! +#include <string> +#include <vector> +#include "sim/process.hh" namespace X86ISA { -}; + struct M5_64_auxv_t + { + int64_t a_type; + union { + int64_t a_val; + int64_t a_ptr; + int64_t a_fcn; + }; + + M5_64_auxv_t() + {} + + M5_64_auxv_t(int64_t type, int64_t val); + }; + + class X86LiveProcess : public LiveProcess + { + protected: + std::vector<M5_64_auxv_t> auxv; + + X86LiveProcess(const std::string &nm, ObjectFile *objFile, + System *_system, + int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp, + const std::string &cwd, + uint64_t _uid, uint64_t _euid, + uint64_t _gid, uint64_t _egid, + uint64_t _pid, uint64_t _ppid); + + void startup(); + + public: + + //Handles traps which request services from the operating system + virtual void handleTrap(int trapNum, ThreadContext *tc); + + void argsInit(int intSize, int pageSize); + }; +} #endif // __ARCH_X86_PROCESS_HH__ diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc index 506913a35..568eb1d94 100644 --- a/src/arch/x86/regfile.cc +++ b/src/arch/x86/regfile.cc @@ -130,25 +130,25 @@ void RegFile::clear() miscRegFile.clear(); } -MiscReg RegFile::readMiscReg(int miscReg) +MiscReg RegFile::readMiscRegNoEffect(int miscReg) { - return miscRegFile.readReg(miscReg); + return miscRegFile.readRegNoEffect(miscReg); } -MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc) +MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc) { - return miscRegFile.readRegWithEffect(miscReg, tc); + return miscRegFile.readReg(miscReg, tc); } -void RegFile::setMiscReg(int miscReg, const MiscReg &val) +void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val) { - miscRegFile.setReg(miscReg, val); + miscRegFile.setRegNoEffect(miscReg, val); } -void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val, +void RegFile::setMiscReg(int miscReg, const MiscReg &val, ThreadContext * tc) { - miscRegFile.setRegWithEffect(miscReg, val, tc); + miscRegFile.setReg(miscReg, val, tc); } FloatReg RegFile::readFloatReg(int floatReg, int width) diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh index 41ebcd8de..d4425b04c 100644 --- a/src/arch/x86/regfile.hh +++ b/src/arch/x86/regfile.hh @@ -98,13 +98,13 @@ namespace X86ISA int FlattenIntIndex(int reg); - MiscReg readMiscReg(int miscReg); + MiscReg readMiscRegNoEffect(int miscReg); - MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc); + MiscReg readMiscReg(int miscReg, ThreadContext *tc); - void setMiscReg(int miscReg, const MiscReg &val); + void setMiscRegNoEffect(int miscReg, const MiscReg &val); - void setMiscRegWithEffect(int miscReg, const MiscReg &val, + void setMiscReg(int miscReg, const MiscReg &val, ThreadContext * tc); int instAsid() diff --git a/src/base/annotate.cc b/src/base/annotate.cc index ba2fb1788..de7eeed51 100644 --- a/src/base/annotate.cc +++ b/src/base/annotate.cc @@ -32,7 +32,7 @@ #include "base/callback.hh" #include "base/output.hh" #include "base/trace.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" diff --git a/src/base/bigint.cc b/src/base/bigint.cc new file mode 100644 index 000000000..ce9942c9c --- /dev/null +++ b/src/base/bigint.cc @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "base/bigint.hh" + +#include <iostream> + +using namespace std; + +ostream & operator << (ostream & os, const Twin64_t & t) +{ + os << t.a << ", " << t.b; + return os; +} + +ostream & operator << (ostream & os, const Twin32_t & t) +{ + os << t.a << ", " << t.b; + return os; +} diff --git a/src/base/bigint.hh b/src/base/bigint.hh index d533e662a..ed48c67fe 100644 --- a/src/base/bigint.hh +++ b/src/base/bigint.hh @@ -28,12 +28,21 @@ * Authors: Ali Saidi */ +#include <iostream> + #ifndef __BASE_BIGINT_HH__ #define __BASE_BIGINT_HH__ // Create a couple of large int types for atomic reads struct m5_twin64_t { uint64_t a; uint64_t b; + m5_twin64_t() + {} + m5_twin64_t(const uint64_t x) + { + a = x; + b = x; + } inline m5_twin64_t& operator=(const uint64_t x) { a = x; @@ -45,6 +54,13 @@ struct m5_twin64_t { struct m5_twin32_t { uint32_t a; uint32_t b; + m5_twin32_t() + {} + m5_twin32_t(const uint32_t x) + { + a = x; + b = x; + } inline m5_twin32_t& operator=(const uint32_t x) { a = x; @@ -59,6 +75,9 @@ struct m5_twin32_t { typedef m5_twin64_t Twin64_t; typedef m5_twin32_t Twin32_t; +// Output operator overloads +std::ostream & operator << (std::ostream & os, const Twin64_t & t); +std::ostream & operator << (std::ostream & os, const Twin32_t & t); #endif // __BASE_BIGINT_HH__ diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index b56dc5aa6..8f157da28 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -89,6 +89,12 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) } else if (ehdr.e_machine == EM_MIPS && ehdr.e_ident[EI_CLASS] == ELFCLASS32) { arch = ObjectFile::Mips; + } else if (ehdr.e_machine == EM_X86_64 && + ehdr.e_ident[EI_CLASS] == ELFCLASS64) { + //In the future, we might want to differentiate between 32 bit + //and 64 bit x86 processes in case there are differences in their + //initial stack frame. + arch = ObjectFile::X86; } else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) { arch = ObjectFile::Alpha; } else { diff --git a/src/base/misc.cc b/src/base/misc.cc index 29b6d2d88..afb48ca80 100644 --- a/src/base/misc.cc +++ b/src/base/misc.cc @@ -38,7 +38,7 @@ #include "base/trace.hh" #include "base/varargs.hh" #include "sim/host.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/base/pollevent.cc b/src/base/pollevent.cc index 32724b74d..331b5eac6 100644 --- a/src/base/pollevent.cc +++ b/src/base/pollevent.cc @@ -42,7 +42,7 @@ #include "sim/host.hh" #include "base/misc.hh" #include "base/pollevent.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include "sim/serialize.hh" using namespace std; diff --git a/src/base/pollevent.hh b/src/base/pollevent.hh index 5b84650cb..ecaeb94ce 100644 --- a/src/base/pollevent.hh +++ b/src/base/pollevent.hh @@ -33,7 +33,7 @@ #include <vector> #include <poll.h> -#include "sim/root.hh" +#include "sim/core.hh" class Checkpoint; class PollQueue; diff --git a/src/base/trace.hh b/src/base/trace.hh index 8e380d8e1..c1b506187 100644 --- a/src/base/trace.hh +++ b/src/base/trace.hh @@ -39,7 +39,7 @@ #include "base/match.hh" #include "base/traceflags.hh" #include "sim/host.hh" -#include "sim/root.hh" +#include "sim/core.hh" namespace Trace { diff --git a/src/base/traceflags.py b/src/base/traceflags.py index ba6aa6af8..cb17d98d3 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -168,6 +168,7 @@ baseFlags = [ 'VtoPhys', 'WriteBarrier', 'Writeback', + 'X86', ] # diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 3e08193ee..7b3628986 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -298,27 +298,27 @@ class CheckerCPU : public BaseCPU thread->setNextPC(val); } - MiscReg readMiscReg(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) { - return thread->readMiscReg(misc_reg); + return thread->readMiscRegNoEffect(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg) + MiscReg readMiscReg(int misc_reg) { - return thread->readMiscRegWithEffect(misc_reg); + return thread->readMiscReg(misc_reg); } - void setMiscReg(int misc_reg, const MiscReg &val) + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) { result.integer = val; miscRegIdxs.push(misc_reg); - return thread->setMiscReg(misc_reg, val); + return thread->setMiscRegNoEffect(misc_reg, val); } - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { miscRegIdxs.push(misc_reg); - return thread->setMiscRegWithEffect(misc_reg, val); + return thread->setMiscReg(misc_reg, val); } void recordPCChange(uint64_t val) { changedPC = true; newPC = val; } diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 56e13dd1e..f3f8a0bb3 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -386,13 +386,13 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst) int misc_reg_idx = miscRegIdxs.front(); miscRegIdxs.pop(); - if (inst->tcBase()->readMiscReg(misc_reg_idx) != - thread->readMiscReg(misc_reg_idx)) { + if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) != + thread->readMiscRegNoEffect(misc_reg_idx)) { warn("%lli: Misc reg idx %i (side effect) does not match! " "Inst: %#x, checker: %#x", curTick, misc_reg_idx, - inst->tcBase()->readMiscReg(misc_reg_idx), - thread->readMiscReg(misc_reg_idx)); + inst->tcBase()->readMiscRegNoEffect(misc_reg_idx), + thread->readMiscRegNoEffect(misc_reg_idx)); handleError(inst); } } @@ -432,7 +432,7 @@ Checker<DynInstPtr>::copyResult(DynInstPtr &inst) } else if (idx < TheISA::Fpcr_DepTag) { thread->setFloatRegBits(idx, inst->readIntResult()); } else { - thread->setMiscReg(idx, inst->readIntResult()); + thread->setMiscRegNoEffect(idx, inst->readIntResult()); } } diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index cf36d8392..3b4d21e13 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -248,11 +248,17 @@ class CheckerThreadContext : public ThreadContext checkerCPU->recordNextPCChange(val); } + MiscReg readMiscRegNoEffect(int misc_reg) + { return actualTC->readMiscRegNoEffect(misc_reg); } + MiscReg readMiscReg(int misc_reg) { return actualTC->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg) - { return actualTC->readMiscRegWithEffect(misc_reg); } + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) + { + checkerTC->setMiscRegNoEffect(misc_reg, val); + actualTC->setMiscRegNoEffect(misc_reg, val); + } void setMiscReg(int misc_reg, const MiscReg &val) { @@ -260,12 +266,6 @@ class CheckerThreadContext : public ThreadContext actualTC->setMiscReg(misc_reg, val); } - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) - { - checkerTC->setMiscRegWithEffect(misc_reg, val); - actualTC->setMiscRegWithEffect(misc_reg, val); - } - unsigned readStCondFailures() { return actualTC->readStCondFailures(); } diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index edccd747f..2b9fe4bcf 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -100,18 +100,18 @@ class ExecContext { void setNextNPC(uint64_t val); /** Reads a miscellaneous register. */ - MiscReg readMiscReg(int misc_reg); + MiscReg readMiscRegNoEffect(int misc_reg); /** Reads a miscellaneous register, handling any architectural * side effects due to reading that register. */ - MiscReg readMiscRegWithEffect(int misc_reg); + MiscReg readMiscReg(int misc_reg); /** Sets a miscellaneous register. */ - void setMiscReg(int misc_reg, const MiscReg &val); + void setMiscRegNoEffect(int misc_reg, const MiscReg &val); /** Sets a miscellaneous register, handling any architectural * side effects due to writing that register. */ - void setMiscRegWithEffect(int misc_reg, const MiscReg &val); + void setMiscReg(int misc_reg, const MiscReg &val); /** Records the effective address of the instruction. Only valid * for memory ops. */ diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index c4d3ae505..54d8c68fa 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -171,14 +171,14 @@ Trace::InstRecord::dump() outs << "PC = " << thread->readNextPC(); outs << " NPC = " << thread->readNextNPC(); newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2); - //newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); + //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_CCR); if(newVal != ccr) { outs << " CCR = " << newVal; ccr = newVal; } newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1); - //newVal = thread->readMiscReg(SparcISA::MISCREG_Y); + //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_Y); if(newVal != y) { outs << " Y = " << newVal; @@ -387,30 +387,30 @@ Trace::InstRecord::dump() diffFpRegs = true; } } - uint64_t oldTl = thread->readMiscReg(MISCREG_TL); + uint64_t oldTl = thread->readMiscRegNoEffect(MISCREG_TL); if (oldTl != shared_data->tl) diffTl = true; for (int i = 1; i <= MaxTL; i++) { - thread->setMiscReg(MISCREG_TL, i); - if (thread->readMiscReg(MISCREG_TPC) != + thread->setMiscRegNoEffect(MISCREG_TL, i); + if (thread->readMiscRegNoEffect(MISCREG_TPC) != shared_data->tpc[i-1]) diffTpc = true; - if (thread->readMiscReg(MISCREG_TNPC) != + if (thread->readMiscRegNoEffect(MISCREG_TNPC) != shared_data->tnpc[i-1]) diffTnpc = true; - if (thread->readMiscReg(MISCREG_TSTATE) != + if (thread->readMiscRegNoEffect(MISCREG_TSTATE) != shared_data->tstate[i-1]) diffTstate = true; - if (thread->readMiscReg(MISCREG_TT) != + if (thread->readMiscRegNoEffect(MISCREG_TT) != shared_data->tt[i-1]) diffTt = true; - if (thread->readMiscReg(MISCREG_HTSTATE) != + if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) != shared_data->htstate[i-1]) diffHtstate = true; } - thread->setMiscReg(MISCREG_TL, oldTl); + thread->setMiscRegNoEffect(MISCREG_TL, oldTl); - if(shared_data->tba != thread->readMiscReg(MISCREG_TBA)) + if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA)) diffTba = true; //When the hpstate register is read by an instruction, //legion has bit 11 set. When it's in storage, it doesn't. @@ -418,50 +418,50 @@ Trace::InstRecord::dump() //of the registers like that, the bit is always set to 1 and //we just don't compare it. It's not supposed to matter //anyway. - if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE)) + if((shared_data->hpstate | (1 << 11)) != thread->readMiscRegNoEffect(MISCREG_HPSTATE)) diffHpstate = true; - if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA)) + if(shared_data->htba != thread->readMiscRegNoEffect(MISCREG_HTBA)) diffHtba = true; - if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE)) + if(shared_data->pstate != thread->readMiscRegNoEffect(MISCREG_PSTATE)) diffPstate = true; - //if(shared_data->y != thread->readMiscReg(MISCREG_Y)) + //if(shared_data->y != thread->readMiscRegNoEffect(MISCREG_Y)) if(shared_data->y != thread->readIntReg(NumIntArchRegs + 1)) diffY = true; - if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) { + if(shared_data->fsr != thread->readMiscRegNoEffect(MISCREG_FSR)) { diffFsr = true; if (mbits(shared_data->fsr, 63,10) == - mbits(thread->readMiscReg(MISCREG_FSR), 63,10)) { - thread->setMiscReg(MISCREG_FSR, shared_data->fsr); + mbits(thread->readMiscRegNoEffect(MISCREG_FSR), 63,10)) { + thread->setMiscRegNoEffect(MISCREG_FSR, shared_data->fsr); diffFsr = false; } } - //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR)) + //if(shared_data->ccr != thread->readMiscRegNoEffect(MISCREG_CCR)) if(shared_data->ccr != thread->readIntReg(NumIntArchRegs + 2)) diffCcr = true; - if(shared_data->gl != thread->readMiscReg(MISCREG_GL)) + if(shared_data->gl != thread->readMiscRegNoEffect(MISCREG_GL)) diffGl = true; - if(shared_data->asi != thread->readMiscReg(MISCREG_ASI)) + if(shared_data->asi != thread->readMiscRegNoEffect(MISCREG_ASI)) diffAsi = true; - if(shared_data->pil != thread->readMiscReg(MISCREG_PIL)) + if(shared_data->pil != thread->readMiscRegNoEffect(MISCREG_PIL)) diffPil = true; - if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP)) + if(shared_data->cwp != thread->readMiscRegNoEffect(MISCREG_CWP)) diffCwp = true; - //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE)) + //if(shared_data->cansave != thread->readMiscRegNoEffect(MISCREG_CANSAVE)) if(shared_data->cansave != thread->readIntReg(NumIntArchRegs + 3)) diffCansave = true; //if(shared_data->canrestore != - // thread->readMiscReg(MISCREG_CANRESTORE)) + // thread->readMiscRegNoEffect(MISCREG_CANRESTORE)) if(shared_data->canrestore != thread->readIntReg(NumIntArchRegs + 4)) diffCanrestore = true; - //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN)) + //if(shared_data->otherwin != thread->readMiscRegNoEffect(MISCREG_OTHERWIN)) if(shared_data->otherwin != thread->readIntReg(NumIntArchRegs + 6)) diffOtherwin = true; - //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) + //if(shared_data->cleanwin != thread->readMiscRegNoEffect(MISCREG_CLEANWIN)) if(shared_data->cleanwin != thread->readIntReg(NumIntArchRegs + 5)) diffCleanwin = true; @@ -569,78 +569,78 @@ Trace::InstRecord::dump() printSectionHeader(outs, "General State"); printColumnLabels(outs); printRegPair(outs, "HPstate", - thread->readMiscReg(MISCREG_HPSTATE), + thread->readMiscRegNoEffect(MISCREG_HPSTATE), shared_data->hpstate | (1 << 11)); printRegPair(outs, "Htba", - thread->readMiscReg(MISCREG_HTBA), + thread->readMiscRegNoEffect(MISCREG_HTBA), shared_data->htba); printRegPair(outs, "Pstate", - thread->readMiscReg(MISCREG_PSTATE), + thread->readMiscRegNoEffect(MISCREG_PSTATE), shared_data->pstate); printRegPair(outs, "Y", - //thread->readMiscReg(MISCREG_Y), + //thread->readMiscRegNoEffect(MISCREG_Y), thread->readIntReg(NumIntArchRegs + 1), shared_data->y); printRegPair(outs, "FSR", - thread->readMiscReg(MISCREG_FSR), + thread->readMiscRegNoEffect(MISCREG_FSR), shared_data->fsr); printRegPair(outs, "Ccr", - //thread->readMiscReg(MISCREG_CCR), + //thread->readMiscRegNoEffect(MISCREG_CCR), thread->readIntReg(NumIntArchRegs + 2), shared_data->ccr); printRegPair(outs, "Tl", - thread->readMiscReg(MISCREG_TL), + thread->readMiscRegNoEffect(MISCREG_TL), shared_data->tl); printRegPair(outs, "Gl", - thread->readMiscReg(MISCREG_GL), + thread->readMiscRegNoEffect(MISCREG_GL), shared_data->gl); printRegPair(outs, "Asi", - thread->readMiscReg(MISCREG_ASI), + thread->readMiscRegNoEffect(MISCREG_ASI), shared_data->asi); printRegPair(outs, "Pil", - thread->readMiscReg(MISCREG_PIL), + thread->readMiscRegNoEffect(MISCREG_PIL), shared_data->pil); printRegPair(outs, "Cwp", - thread->readMiscReg(MISCREG_CWP), + thread->readMiscRegNoEffect(MISCREG_CWP), shared_data->cwp); printRegPair(outs, "Cansave", - //thread->readMiscReg(MISCREG_CANSAVE), + //thread->readMiscRegNoEffect(MISCREG_CANSAVE), thread->readIntReg(NumIntArchRegs + 3), shared_data->cansave); printRegPair(outs, "Canrestore", - //thread->readMiscReg(MISCREG_CANRESTORE), + //thread->readMiscRegNoEffect(MISCREG_CANRESTORE), thread->readIntReg(NumIntArchRegs + 4), shared_data->canrestore); printRegPair(outs, "Otherwin", - //thread->readMiscReg(MISCREG_OTHERWIN), + //thread->readMiscRegNoEffect(MISCREG_OTHERWIN), thread->readIntReg(NumIntArchRegs + 6), shared_data->otherwin); printRegPair(outs, "Cleanwin", - //thread->readMiscReg(MISCREG_CLEANWIN), + //thread->readMiscRegNoEffect(MISCREG_CLEANWIN), thread->readIntReg(NumIntArchRegs + 5), shared_data->cleanwin); outs << endl; for (int i = 1; i <= MaxTL; i++) { printLevelHeader(outs, i); printColumnLabels(outs); - thread->setMiscReg(MISCREG_TL, i); + thread->setMiscRegNoEffect(MISCREG_TL, i); printRegPair(outs, "Tpc", - thread->readMiscReg(MISCREG_TPC), + thread->readMiscRegNoEffect(MISCREG_TPC), shared_data->tpc[i-1]); printRegPair(outs, "Tnpc", - thread->readMiscReg(MISCREG_TNPC), + thread->readMiscRegNoEffect(MISCREG_TNPC), shared_data->tnpc[i-1]); printRegPair(outs, "Tstate", - thread->readMiscReg(MISCREG_TSTATE), + thread->readMiscRegNoEffect(MISCREG_TSTATE), shared_data->tstate[i-1]); printRegPair(outs, "Tt", - thread->readMiscReg(MISCREG_TT), + thread->readMiscRegNoEffect(MISCREG_TT), shared_data->tt[i-1]); printRegPair(outs, "Htstate", - thread->readMiscReg(MISCREG_HTSTATE), + thread->readMiscRegNoEffect(MISCREG_HTSTATE), shared_data->htstate[i-1]); } - thread->setMiscReg(MISCREG_TL, oldTl); + thread->setMiscRegNoEffect(MISCREG_TL, oldTl); outs << endl; printSectionHeader(outs, "General Purpose Registers"); diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh index 0f642c08e..8c0fa22cb 100644 --- a/src/cpu/exetrace.hh +++ b/src/cpu/exetrace.hh @@ -116,6 +116,8 @@ class InstRecord void setAddr(Addr a) { addr = a; addr_valid = true; } + void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; } + void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; } void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 4a2086296..676893098 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -106,21 +106,21 @@ class AlphaO3CPU : public FullO3CPU<Impl> #endif /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); + TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); + TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - void setMiscReg(int misc_reg, const TheISA::MiscReg &val, + void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val, + void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 41f149963..b91972704 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -154,32 +154,32 @@ AlphaO3CPU<Impl>::regStats() template <class Impl> TheISA::MiscReg -AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) +AlphaO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) { - return this->regFile.readMiscReg(misc_reg, tid); + return this->regFile.readMiscRegNoEffect(misc_reg, tid); } template <class Impl> TheISA::MiscReg -AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid) +AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) { - return this->regFile.readMiscRegWithEffect(misc_reg, tid); + return this->regFile.readMiscReg(misc_reg, tid); } template <class Impl> void -AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val, +AlphaO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid) { - this->regFile.setMiscReg(misc_reg, val, tid); + this->regFile.setMiscRegNoEffect(misc_reg, val, tid); } template <class Impl> void -AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, +AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid) { - this->regFile.setMiscRegWithEffect(misc_reg, val, tid); + this->regFile.setMiscReg(misc_reg, val, tid); } template <class Impl> @@ -209,7 +209,7 @@ Fault AlphaO3CPU<Impl>::hwrei(unsigned tid) { // Need to clear the lock flag upon returning from an interrupt. - this->setMiscReg(AlphaISA::MISCREG_LOCKFLAG, false, tid); + this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); this->thread[tid]->kernelStats->hwrei(); diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 603a1b52d..20759d849 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -95,39 +95,39 @@ class AlphaDynInst : public BaseDynInst<Impl> public: /** Reads a miscellaneous register. */ - MiscReg readMiscReg(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) { - return this->cpu->readMiscReg(misc_reg, this->threadNumber); + return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber); } /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg) + MiscReg readMiscReg(int misc_reg) { - return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber); + return this->cpu->readMiscReg(misc_reg, this->threadNumber); } /** Sets a misc. register. */ - void setMiscReg(int misc_reg, const MiscReg &val) + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) { this->instResult.integer = val; - return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); + return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber); } /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { - return this->cpu->setMiscRegWithEffect(misc_reg, val, + return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); } /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) + TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) { - return this->cpu->readMiscReg( + return this->cpu->readMiscRegNoEffect( si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, this->threadNumber); } @@ -135,18 +135,18 @@ class AlphaDynInst : public BaseDynInst<Impl> /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx) + TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) { - return this->cpu->readMiscRegWithEffect( + return this->cpu->readMiscReg( si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, this->threadNumber); } /** Sets a misc. register. */ - void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val) + void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val) { this->instResult.integer = val; - return this->cpu->setMiscReg( + return this->cpu->setMiscRegNoEffect( si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, val, this->threadNumber); } @@ -154,10 +154,10 @@ class AlphaDynInst : public BaseDynInst<Impl> /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - void setMiscRegOperandWithEffect(const StaticInst *si, int idx, + void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) { - return this->cpu->setMiscRegWithEffect( + return this->cpu->setMiscReg( si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, val, this->threadNumber); } diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index 50cdec408..fdce1ade5 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -118,7 +118,7 @@ AlphaDynInst<Impl>::hwrei() return new AlphaISA::UnimplementedOpcodeFault; // Set the next PC based on the value of the EXC_ADDR IPR. - this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR, + this->setNextPC(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, this->threadNumber)); // Tell CPU to clear any state it needs to if a hwrei is taken. diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 66c75a12d..785165636 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -45,7 +45,7 @@ #include "cpu/o3/isa_specific.hh" #include "cpu/o3/cpu.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include "sim/stat_control.hh" #if USE_CHECKER diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index e6a779823..ac0149d18 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -40,7 +40,7 @@ #include "mem/request.hh" #include "sim/byteswap.hh" #include "sim/host.hh" -#include "sim/root.hh" +#include "sim/core.hh" #if FULL_SYSTEM #include "arch/tlb.hh" diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 98b8fa900..d5781d89d 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -32,7 +32,7 @@ #include <limits> #include <vector> -#include "sim/root.hh" +#include "sim/core.hh" #include "cpu/o3/fu_pool.hh" #include "cpu/o3/inst_queue.hh" diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh index 7e6268cdf..0361c1814 100755 --- a/src/cpu/o3/mips/cpu.hh +++ b/src/cpu/o3/mips/cpu.hh @@ -87,20 +87,20 @@ class MipsO3CPU : public FullO3CPU<Impl> } /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); + TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); + TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); + void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - void setMiscRegWithEffect(int misc_reg, + void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index e7dbd3aba..317fd748e 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -135,31 +135,31 @@ MipsO3CPU<Impl>::regStats() template <class Impl> MiscReg -MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) +MipsO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) { - return this->regFile.readMiscReg(misc_reg, tid); + return this->regFile.readMiscRegNoEffect(misc_reg, tid); } template <class Impl> MiscReg -MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid) +MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) { - return this->regFile.readMiscRegWithEffect(misc_reg, tid); + return this->regFile.readMiscReg(misc_reg, tid); } template <class Impl> void -MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) +MipsO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid) { - this->regFile.setMiscReg(misc_reg, val, tid); + this->regFile.setMiscRegNoEffect(misc_reg, val, tid); } template <class Impl> void -MipsO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val, +MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) { - this->regFile.setMiscRegWithEffect(misc_reg, val, tid); + this->regFile.setMiscReg(misc_reg, val, tid); } template <class Impl> diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh index f53530908..366b4bb23 100755 --- a/src/cpu/o3/mips/dyn_inst.hh +++ b/src/cpu/o3/mips/dyn_inst.hh @@ -93,32 +93,32 @@ class MipsDynInst : public BaseDynInst<Impl> public: /** Reads a miscellaneous register. */ - MiscReg readMiscReg(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) { - return this->cpu->readMiscReg(misc_reg, this->threadNumber); + return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber); } /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg) + MiscReg readMiscReg(int misc_reg) { - return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber); + return this->cpu->readMiscReg(misc_reg, this->threadNumber); } /** Sets a misc. register. */ - void setMiscReg(int misc_reg, const MiscReg &val) + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) { this->instResult.integer = val; - this->cpu->setMiscReg(misc_reg, val, this->threadNumber); + this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber); } /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { - return this->cpu->setMiscRegWithEffect(misc_reg, val, + return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); } diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 598af123e..c4f8f3a9f 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -225,26 +225,26 @@ class PhysRegFile floatRegFile[reg_idx].q = val; } - MiscReg readMiscReg(int misc_reg, unsigned thread_id) + MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id) { - return miscRegs[thread_id].readReg(misc_reg); + return miscRegs[thread_id].readRegNoEffect(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id) + MiscReg readMiscReg(int misc_reg, unsigned thread_id) { - return miscRegs[thread_id].readRegWithEffect(misc_reg, + return miscRegs[thread_id].readReg(misc_reg, cpu->tcBase(thread_id)); } - void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) + void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned thread_id) { - miscRegs[thread_id].setReg(misc_reg, val); + miscRegs[thread_id].setRegNoEffect(misc_reg, val); } - void setMiscRegWithEffect(int misc_reg, const MiscReg &val, + void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) { - miscRegs[thread_id].setRegWithEffect(misc_reg, val, + miscRegs[thread_id].setReg(misc_reg, val, cpu->tcBase(thread_id)); } diff --git a/src/cpu/o3/sparc/cpu.hh b/src/cpu/o3/sparc/cpu.hh index 08ebd2710..7b932e429 100644 --- a/src/cpu/o3/sparc/cpu.hh +++ b/src/cpu/o3/sparc/cpu.hh @@ -106,20 +106,20 @@ class SparcO3CPU : public FullO3CPU<Impl> #endif /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); + TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); + TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); + void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val, + void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index c039a8fec..a425a8a56 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -153,32 +153,32 @@ SparcO3CPU<Impl>::regStats() template <class Impl> TheISA::MiscReg -SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) +SparcO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) { - return this->regFile.readMiscReg(misc_reg, tid); + return this->regFile.readMiscRegNoEffect(misc_reg, tid); } template <class Impl> TheISA::MiscReg -SparcO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid) +SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) { - return this->regFile.readMiscRegWithEffect(misc_reg, tid); + return this->regFile.readMiscReg(misc_reg, tid); } template <class Impl> void -SparcO3CPU<Impl>::setMiscReg(int misc_reg, +SparcO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, const SparcISA::MiscReg &val, unsigned tid) { - this->regFile.setMiscReg(misc_reg, val, tid); + this->regFile.setMiscRegNoEffect(misc_reg, val, tid); } template <class Impl> void -SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, +SparcO3CPU<Impl>::setMiscReg(int misc_reg, const SparcISA::MiscReg &val, unsigned tid) { - this->regFile.setMiscRegWithEffect(misc_reg, val, tid); + this->regFile.setMiscReg(misc_reg, val, tid); } template <class Impl> diff --git a/src/cpu/o3/sparc/dyn_inst.hh b/src/cpu/o3/sparc/dyn_inst.hh index 4314488b5..72242b161 100644 --- a/src/cpu/o3/sparc/dyn_inst.hh +++ b/src/cpu/o3/sparc/dyn_inst.hh @@ -77,39 +77,39 @@ class SparcDynInst : public BaseDynInst<Impl> public: /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscReg(int misc_reg) + TheISA::MiscReg readMiscRegNoEffect(int misc_reg) { - return this->cpu->readMiscReg(misc_reg, this->threadNumber); + return this->cpu->readMiscRegNoEffect(misc_reg, this->threadNumber); } /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegWithEffect(int misc_reg) + TheISA::MiscReg readMiscReg(int misc_reg) { - return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber); + return this->cpu->readMiscReg(misc_reg, this->threadNumber); } /** Sets a misc. register. */ - void setMiscReg(int misc_reg, const TheISA::MiscReg &val) + void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val) { this->instResult.integer = val; - return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); + return this->cpu->setMiscRegNoEffect(misc_reg, val, this->threadNumber); } /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val) + void setMiscReg(int misc_reg, const TheISA::MiscReg &val) { - return this->cpu->setMiscRegWithEffect(misc_reg, val, + return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); } /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) + TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) { - return this->cpu->readMiscReg( + return this->cpu->readMiscRegNoEffect( si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, this->threadNumber); } @@ -117,19 +117,19 @@ class SparcDynInst : public BaseDynInst<Impl> /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx) + TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx) { - return this->cpu->readMiscRegWithEffect( + return this->cpu->readMiscReg( si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag, this->threadNumber); } /** Sets a misc. register. */ - void setMiscRegOperand(const StaticInst * si, + void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const TheISA::MiscReg &val) { this->instResult.integer = val; - return this->cpu->setMiscReg( + return this->cpu->setMiscRegNoEffect( si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, val, this->threadNumber); } @@ -137,10 +137,10 @@ class SparcDynInst : public BaseDynInst<Impl> /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - void setMiscRegOperandWithEffect( + void setMiscRegOperand( const StaticInst *si, int idx, const TheISA::MiscReg &val) { - return this->cpu->setMiscRegWithEffect( + return this->cpu->setMiscReg( si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag, val, this->threadNumber); } diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 4987d6eb4..93638673b 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -206,20 +206,20 @@ class O3ThreadContext : public ThreadContext virtual void setNextPC(uint64_t val); /** Reads a miscellaneous register. */ - virtual MiscReg readMiscReg(int misc_reg) - { return cpu->readMiscReg(misc_reg, thread->readTid()); } + virtual MiscReg readMiscRegNoEffect(int misc_reg) + { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ - virtual MiscReg readMiscRegWithEffect(int misc_reg) - { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); } + virtual MiscReg readMiscReg(int misc_reg) + { return cpu->readMiscReg(misc_reg, thread->readTid()); } /** Sets a misc. register. */ - virtual void setMiscReg(int misc_reg, const MiscReg &val); + virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); /** Sets a misc. register, including any side-effects the * write might have as defined by the architecture. */ - virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val); + virtual void setMiscReg(int misc_reg, const MiscReg &val); /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index af98fa1f5..d2acc6232 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -442,9 +442,9 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val) template <class Impl> void -O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) +O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { - cpu->setMiscReg(misc_reg, val, thread->readTid()); + cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { @@ -454,10 +454,10 @@ O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) template <class Impl> void -O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg, +O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) { - cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid()); + cpu->setMiscReg(misc_reg, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index baea7a546..2432df55e 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -235,14 +235,14 @@ class OzoneCPU : public BaseCPU public: // ISA stuff: + MiscReg readMiscRegNoEffect(int misc_reg); + MiscReg readMiscReg(int misc_reg); - MiscReg readMiscRegWithEffect(int misc_reg); + void setMiscRegNoEffect(int misc_reg, const MiscReg &val); void setMiscReg(int misc_reg, const MiscReg &val); - void setMiscRegWithEffect(int misc_reg, const MiscReg &val); - unsigned readStCondFailures() { return thread->storeCondFailures; } diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index a854de8de..4a76ae110 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -1089,24 +1089,24 @@ OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val) template <class Impl> TheISA::MiscReg -OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg) +OzoneCPU<Impl>::OzoneTC::readMiscRegNoEffect(int misc_reg) { - return thread->miscRegFile.readReg(misc_reg); + return thread->miscRegFile.readRegNoEffect(misc_reg); } template <class Impl> TheISA::MiscReg -OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg) +OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg) { - return thread->miscRegFile.readRegWithEffect(misc_reg, this); + return thread->miscRegFile.readReg(misc_reg, this); } template <class Impl> void -OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val) +OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode - thread->miscRegFile.setReg(misc_reg, val); + thread->miscRegFile.setRegNoEffect(misc_reg, val); if (!thread->inSyscall) { cpu->squashFromTC(); @@ -1115,10 +1115,10 @@ OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val) template <class Impl> void -OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val) +OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode - thread->miscRegFile.setRegWithEffect(misc_reg, val, this); + thread->miscRegFile.setReg(misc_reg, val, this); if (!thread->inSyscall) { cpu->squashFromTC(); diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index 88f96b14b..e138cbe13 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -231,14 +231,14 @@ class OzoneDynInst : public BaseDynInst<Impl> public: // ISA stuff + MiscReg readMiscRegNoEffect(int misc_reg); + MiscReg readMiscReg(int misc_reg); - MiscReg readMiscRegWithEffect(int misc_reg); + void setMiscRegNoEffect(int misc_reg, const MiscReg &val); void setMiscReg(int misc_reg, const MiscReg &val); - void setMiscRegWithEffect(int misc_reg, const MiscReg &val); - #if FULL_SYSTEM Fault hwrei(); void trap(Fault fault); diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 05a66d77a..8519917f5 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -219,31 +219,31 @@ OzoneDynInst<Impl>::clearMemDependents() template <class Impl> TheISA::MiscReg -OzoneDynInst<Impl>::readMiscReg(int misc_reg) +OzoneDynInst<Impl>::readMiscRegNoEffect(int misc_reg) { - return this->thread->readMiscReg(misc_reg); + return this->thread->readMiscRegNoEffect(misc_reg); } template <class Impl> TheISA::MiscReg -OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg) +OzoneDynInst<Impl>::readMiscReg(int misc_reg) { - return this->thread->readMiscRegWithEffect(misc_reg); + return this->thread->readMiscReg(misc_reg); } template <class Impl> void -OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val) +OzoneDynInst<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { this->setIntResult(val); - this->thread->setMiscReg(misc_reg, val); + this->thread->setMiscRegNoEffect(misc_reg, val); } template <class Impl> void -OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val) +OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val) { - this->thread->setMiscRegWithEffect(misc_reg, val); + this->thread->setMiscReg(misc_reg, val); } #if FULL_SYSTEM @@ -255,7 +255,7 @@ OzoneDynInst<Impl>::hwrei() if (!(this->readPC() & 0x3)) return new AlphaISA::UnimplementedOpcodeFault; - this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR)); + this->setNextPC(this->thread->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR)); this->cpu->hwrei(); diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh index 84f935a72..8d7ebb60e 100644 --- a/src/cpu/ozone/inorder_back_end_impl.hh +++ b/src/cpu/ozone/inorder_back_end_impl.hh @@ -89,13 +89,13 @@ InorderBackEnd<Impl>::checkInterrupts() int summary = 0; - if (thread->readMiscReg(IPR_ASTRR)) + if (thread->readMiscRegNoEffect(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (thread->readMiscReg(IPR_SIRR)) { + if (thread->readMiscRegNoEffect(IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { + if (thread->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of the 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -116,14 +116,14 @@ InorderBackEnd<Impl>::checkInterrupts() } } - if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) { + if (ipl && ipl > thread->readMiscRegNoEffect(IPR_IPLR)) { thread->inSyscall = true; - thread->setMiscReg(IPR_ISR, summary); - thread->setMiscReg(IPR_INTID, ipl); + thread->setMiscRegNoEffect(IPR_ISR, summary); + thread->setMiscRegNoEffect(IPR_INTID, ipl); Fault(new InterruptFault)->invoke(xc); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - thread->readMiscReg(IPR_IPLR), ipl, summary); + thread->readMiscRegNoEffect(IPR_IPLR), ipl, summary); // May need to go 1 inst prior squashPending = true; diff --git a/src/cpu/ozone/inst_queue_impl.hh b/src/cpu/ozone/inst_queue_impl.hh index 84f2b2a19..ea9d03c0d 100644 --- a/src/cpu/ozone/inst_queue_impl.hh +++ b/src/cpu/ozone/inst_queue_impl.hh @@ -38,7 +38,7 @@ #include <vector> -#include "sim/root.hh" +#include "sim/core.hh" #include "cpu/ozone/inst_queue.hh" #if 0 diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index a181c93f4..c0a9cad24 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -1193,7 +1193,7 @@ LWBackEnd<Impl>::commitInst(int inst_num) #if FULL_SYSTEM if (thread->profile) { // bool usermode = -// (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; +// (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; // thread->profilePC = usermode ? 1 : inst->readPC(); thread->profilePC = inst->readPC(); ProfileNode *node = thread->profile->consume(thread->getTC(), diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index a71795851..53776e7d9 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -115,24 +115,24 @@ struct OzoneThreadState : public ThreadState { ThreadContext *getTC() { return tc; } - MiscReg readMiscReg(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) { - return miscRegFile.readReg(misc_reg); + return miscRegFile.readRegNoEffect(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg) + MiscReg readMiscReg(int misc_reg) { - return miscRegFile.readRegWithEffect(misc_reg, tc); + return miscRegFile.readReg(misc_reg, tc); } - void setMiscReg(int misc_reg, const MiscReg &val) + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) { - miscRegFile.setReg(misc_reg, val); + miscRegFile.setRegNoEffect(misc_reg, val); } - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { - miscRegFile.setRegWithEffect(misc_reg, val, tc); + miscRegFile.setReg(misc_reg, val, tc); } uint64_t readPC() diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc index fca357fe3..7ab8bfcb8 100644 --- a/src/cpu/pc_event.cc +++ b/src/cpu/pc_event.cc @@ -40,7 +40,7 @@ #include "cpu/thread_context.hh" #include "cpu/pc_event.hh" #include "sim/debug.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include "sim/system.hh" using namespace std; diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 01c8e8eb7..eae24014b 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -284,14 +284,19 @@ class BaseSimpleCPU : public BaseCPU void setNextPC(uint64_t val) { thread->setNextPC(val); } void setNextNPC(uint64_t val) { thread->setNextNPC(val); } + MiscReg readMiscRegNoEffect(int misc_reg) + { + return thread->readMiscRegNoEffect(misc_reg); + } + MiscReg readMiscReg(int misc_reg) { return thread->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg) + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) { - return thread->readMiscRegWithEffect(misc_reg); + return thread->setMiscRegNoEffect(misc_reg, val); } void setMiscReg(int misc_reg, const MiscReg &val) @@ -299,9 +304,10 @@ class BaseSimpleCPU : public BaseCPU return thread->setMiscReg(misc_reg, val); } - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) + MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx) { - return thread->setMiscRegWithEffect(misc_reg, val); + int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; + return thread->readMiscRegNoEffect(reg_idx); } MiscReg readMiscRegOperand(const StaticInst *si, int idx) @@ -310,23 +316,17 @@ class BaseSimpleCPU : public BaseCPU return thread->readMiscReg(reg_idx); } - MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->readMiscRegWithEffect(reg_idx); - } - - void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) + void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val) { int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->setMiscReg(reg_idx, val); + return thread->setMiscRegNoEffect(reg_idx, val); } - void setMiscRegOperandWithEffect( + void setMiscRegOperand( const StaticInst *si, int idx, const MiscReg &val) { int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->setMiscRegWithEffect(reg_idx, val); + return thread->setMiscReg(reg_idx, val); } unsigned readStCondFailures() { diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index f2f79c070..824914ad0 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -350,24 +350,24 @@ class SimpleThread : public ThreadState regs.setNextNPC(val); } - MiscReg readMiscReg(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) { - return regs.readMiscReg(misc_reg); + return regs.readMiscRegNoEffect(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg) + MiscReg readMiscReg(int misc_reg) { - return regs.readMiscRegWithEffect(misc_reg, tc); + return regs.readMiscReg(misc_reg, tc); } - void setMiscReg(int misc_reg, const MiscReg &val) + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) { - return regs.setMiscReg(misc_reg, val); + return regs.setMiscRegNoEffect(misc_reg, val); } - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { - return regs.setMiscRegWithEffect(misc_reg, val, tc); + return regs.setMiscReg(misc_reg, val, tc); } unsigned readStCondFailures() { return storeCondFailures; } diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc index cb4a7cdf7..64fcc0580 100644 --- a/src/cpu/static_inst.cc +++ b/src/cpu/static_inst.cc @@ -31,7 +31,7 @@ #include <iostream> #include "cpu/static_inst.hh" -#include "sim/root.hh" +#include "sim/core.hh" StaticInstPtr StaticInst::nullStaticInstPtr; diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index a24dc49da..05c409c95 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -226,14 +226,14 @@ class ThreadContext virtual void setNextNPC(uint64_t val) = 0; + virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; + virtual MiscReg readMiscReg(int misc_reg) = 0; - virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0; + virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; - virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; - // Also not necessarily the best location for these two. Hopefully will go // away once we decide upon where st cond failures goes. virtual unsigned readStCondFailures() = 0; @@ -412,18 +412,18 @@ class ProxyThreadContext : public ThreadContext void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } + MiscReg readMiscRegNoEffect(int misc_reg) + { return actualTC->readMiscRegNoEffect(misc_reg); } + MiscReg readMiscReg(int misc_reg) { return actualTC->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg) - { return actualTC->readMiscRegWithEffect(misc_reg); } + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) + { return actualTC->setMiscRegNoEffect(misc_reg, val); } void setMiscReg(int misc_reg, const MiscReg &val) { return actualTC->setMiscReg(misc_reg, val); } - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) - { return actualTC->setMiscRegWithEffect(misc_reg, val); } - unsigned readStCondFailures() { return actualTC->readStCondFailures(); } diff --git a/src/dev/etherbus.cc b/src/dev/etherbus.cc index 348bb818a..cedb3cd4d 100644 --- a/src/dev/etherbus.cc +++ b/src/dev/etherbus.cc @@ -43,7 +43,7 @@ #include "dev/etherint.hh" #include "dev/etherpkt.hh" #include "sim/builder.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/dev/etherdump.cc b/src/dev/etherdump.cc index 0c986cc21..04463f3ee 100644 --- a/src/dev/etherdump.cc +++ b/src/dev/etherdump.cc @@ -41,7 +41,7 @@ #include "base/output.hh" #include "dev/etherdump.hh" #include "sim/builder.hh" -#include "sim/root.hh" +#include "sim/core.hh" using std::string; diff --git a/src/dev/etherlink.cc b/src/dev/etherlink.cc index cd3812270..5d30e1744 100644 --- a/src/dev/etherlink.cc +++ b/src/dev/etherlink.cc @@ -47,7 +47,7 @@ #include "sim/builder.hh" #include "sim/serialize.hh" #include "sim/system.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/dev/ide_disk.cc b/src/dev/ide_disk.cc index 5083c9c8d..9fa0cedde 100644 --- a/src/dev/ide_disk.cc +++ b/src/dev/ide_disk.cc @@ -48,7 +48,7 @@ #include "dev/alpha/tsunami_pchip.hh" #include "sim/builder.hh" #include "sim/sim_object.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include "arch/isa_traits.hh" using namespace std; diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc index 1c2465dd1..f906e69cf 100644 --- a/src/dev/pcidev.cc +++ b/src/dev/pcidev.cc @@ -51,7 +51,7 @@ #include "sim/builder.hh" #include "sim/byteswap.hh" #include "sim/param.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh index 82db34bf6..b94276035 100644 --- a/src/kern/tru64/tru64.hh +++ b/src/kern/tru64/tru64.hh @@ -56,7 +56,7 @@ class Tru64 {}; #include <unistd.h> #include "cpu/base.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include "sim/syscall_emul.hh" typedef struct stat global_stat; @@ -511,7 +511,7 @@ class Tru64 : public OperatingSystem tc->setFloatRegBits(i, htog(sc->sc_fpregs[i])); } - tc->setMiscReg(AlphaISA::MISCREG_FPCR, htog(sc->sc_fpcr)); + tc->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR, htog(sc->sc_fpcr)); return 0; } @@ -653,7 +653,7 @@ class Tru64 : public OperatingSystem ssp->nxm_sysevent = htog(0); if (i == 0) { - uint64_t uniq = tc->readMiscReg(AlphaISA::MISCREG_UNIQ); + uint64_t uniq = tc->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ); ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset)); ssp->nxm_u.nxm_active = htog(uniq | 1); } @@ -693,7 +693,7 @@ class Tru64 : public OperatingSystem tc->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0)); tc->setIntReg(27/*t12*/, gtoh(attrp->registers.pc)); tc->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp)); - tc->setMiscReg(AlphaISA::MISCREG_UNIQ, uniq_val); + tc->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ, uniq_val); tc->setPC(gtoh(attrp->registers.pc)); tc->setNextPC(gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst)); diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh index a4df1b03f..fa00a0f5a 100644 --- a/src/mem/cache/cache_blk.hh +++ b/src/mem/cache/cache_blk.hh @@ -37,7 +37,7 @@ #include <list> -#include "sim/root.hh" // for Tick +#include "sim/core.hh" // for Tick #include "arch/isa_traits.hh" // for Addr #include "mem/request.hh" diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc index 352d1ec6f..74dad658b 100644 --- a/src/mem/cache/miss/mshr.cc +++ b/src/mem/cache/miss/mshr.cc @@ -39,7 +39,7 @@ #include <vector> #include "mem/cache/miss/mshr.hh" -#include "sim/root.hh" // for curTick +#include "sim/core.hh" // for curTick #include "sim/host.hh" #include "base/misc.hh" #include "mem/cache/cache.hh" diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index 20e2ef0ac..9c802d0dc 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -42,7 +42,7 @@ #include "mem/cache/base_cache.hh" #include "mem/cache/tags/iic.hh" #include "base/intmath.hh" -#include "sim/root.hh" // for curTick +#include "sim/core.hh" // for curTick #include "base/trace.hh" // for DPRINTF diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc index 102bb3506..8e8779774 100644 --- a/src/mem/cache/tags/lru.cc +++ b/src/mem/cache/tags/lru.cc @@ -38,7 +38,7 @@ #include "mem/cache/base_cache.hh" #include "base/intmath.hh" #include "mem/cache/tags/lru.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/mem/cache/tags/split_lifo.cc b/src/mem/cache/tags/split_lifo.cc index 792ff8fa7..d71d1a3ef 100644 --- a/src/mem/cache/tags/split_lifo.cc +++ b/src/mem/cache/tags/split_lifo.cc @@ -38,7 +38,7 @@ #include "mem/cache/base_cache.hh" #include "base/intmath.hh" #include "mem/cache/tags/split_lifo.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include "base/trace.hh" using namespace std; diff --git a/src/mem/cache/tags/split_lru.cc b/src/mem/cache/tags/split_lru.cc index c37d72cb7..7227fb5c1 100644 --- a/src/mem/cache/tags/split_lru.cc +++ b/src/mem/cache/tags/split_lru.cc @@ -38,7 +38,7 @@ #include "mem/cache/base_cache.hh" #include "base/intmath.hh" #include "mem/cache/tags/split_lru.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 16410594a..dc23e9f6d 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -46,7 +46,7 @@ #include "base/misc.hh" #include "mem/request.hh" #include "sim/host.hh" -#include "sim/root.hh" +#include "sim/core.hh" struct Packet; diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh index 552b6dd27..d1edd00aa 100644 --- a/src/mem/packet_access.hh +++ b/src/mem/packet_access.hh @@ -41,31 +41,6 @@ // these functions and make the users do their own byte swapping since // the memory system does not in fact have an endianness. -template<> -inline Twin64_t -Packet::get() -{ - Twin64_t d; - assert(staticData || dynamicData); - assert(sizeof(Twin64_t) <= size); - d.a = TheISA::gtoh(*(uint64_t*)data); - d.b = TheISA::gtoh(*((uint64_t*)data + 1)); - return d; -} - -template<> -inline Twin32_t -Packet::get() -{ - Twin32_t d; - assert(staticData || dynamicData); - assert(sizeof(Twin32_t) <= size); - d.a = TheISA::gtoh(*(uint32_t*)data); - d.b = TheISA::gtoh(*((uint32_t*)data + 1)); - return d; -} - - /** return the value of what is pointed to in the packet. */ template <typename T> inline T diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index fe8094b88..96bc23793 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -157,7 +157,7 @@ PageTable::translate(RequestPtr &req) assert(pageAlign(req->getVaddr() + req->getSize() - 1) == pageAlign(req->getVaddr())); if (!translate(req->getVaddr(), paddr)) { - return genPageTableFault(req->getVaddr()); + return Fault(new PageTableFault(req->getVaddr())); } req->setPaddr(paddr); return page_check(req->getPaddr(), req->getSize()); diff --git a/src/mem/request.hh b/src/mem/request.hh index 43d8ff1d5..d2ebc91d3 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -40,7 +40,7 @@ #define __MEM_REQUEST_HH__ #include "sim/host.hh" -#include "sim/root.hh" +#include "sim/core.hh" #include <cassert> diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 1c4a79020..06dc92bc6 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -36,7 +36,7 @@ import internal # import a few SWIG-wrapped items (those that are likely to be used # directly by user scripts) completely into this module for # convenience -from internal.event import SimLoopExitEvent +import event # import the m5 compile options import defines @@ -80,7 +80,9 @@ env.update(os.environ) # The final hook to generate .ini files. Called from the user script # once the config is built. def instantiate(root): - params.ticks_per_sec = float(root.clock.frequency) + # we need to fix the global frequency + ticks.fixGlobalFrequency() + root.unproxy_all() # ugly temporary hack to get output to config.ini sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w') @@ -94,6 +96,7 @@ def instantiate(root): # Initialize the global statistics internal.stats.initSimStats() + # Create the C++ sim objects and connect ports root.createCCObject() root.connectPorts() @@ -136,11 +139,13 @@ def simulate(*args, **kwargs): # Export curTick to user script. def curTick(): - return internal.event.cvar.curTick + return internal.core.cvar.curTick + +# Python exit handlers happen in reverse order. We want to dump stats last. +atexit.register(internal.stats.dump) # register our C++ exit callback function with Python atexit.register(internal.core.doExitCleanup) -atexit.register(internal.stats.dump) # This loops until all objects have been fully drained. def doDrain(root): @@ -182,17 +187,17 @@ def restoreCheckpoint(root, dir): need_resume.append(root) def changeToAtomic(system): - if not isinstance(system, objects.Root) and not isinstance(system, objects.System): - raise TypeError, "Object is not a root or system object. Checkpoint must be " - "called on a root object." + if not isinstance(system, (objects.Root, objects.System)): + raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ + (type(system), objects.Root, objects.System) doDrain(system) print "Changing memory mode to atomic" system.changeTiming(internal.sim_object.SimObject.Atomic) def changeToTiming(system): - if not isinstance(system, objects.Root) and not isinstance(system, objects.System): - raise TypeError, "Object is not a root or system object. Checkpoint must be " - "called on a root object." + if not isinstance(system, (objects.Root, objects.System)): + raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ + (type(system), objects.Root, objects.System) doDrain(system) print "Changing memory mode to timing" system.changeTiming(internal.sim_object.SimObject.Timing) @@ -233,14 +238,6 @@ def switchCpus(cpuList): new_cpu._ccObject.resume() index += 1 -def dumpStats(): - print 'Dumping stats' - internal.stats.dump() - -def resetStats(): - print 'Resetting stats' - internal.stats.reset() - # Since we have so many mutual imports in this package, we should: # 1. Put all intra-package imports at the *bottom* of the file, unless # they're absolutely needed before that (for top-level statements diff --git a/src/python/m5/convert.py b/src/python/m5/convert.py index 580a579bc..bb9e3e1f1 100644 --- a/src/python/m5/convert.py +++ b/src/python/m5/convert.py @@ -148,7 +148,7 @@ def toLatency(value): raise ValueError, "cannot convert '%s' to latency" % value -def toClockPeriod(value): +def anyToLatency(value): """result is a clock period""" if not isinstance(value, str): @@ -170,6 +170,27 @@ def toClockPeriod(value): raise ValueError, "cannot convert '%s' to clock period" % value +def anyToFrequency(value): + """result is a clock period""" + + if not isinstance(value, str): + raise TypeError, "wrong type '%s' should be str" % type(value) + + try: + val = toFrequency(value) + return val + except ValueError: + pass + + try: + val = toLatency(value) + if val != 0: + val = 1 / val + return val + except ValueError: + pass + + raise ValueError, "cannot convert '%s' to clock period" % value def toNetworkBandwidth(value): if not isinstance(value, str): diff --git a/src/python/m5/event.py b/src/python/m5/event.py new file mode 100644 index 000000000..2d6497464 --- /dev/null +++ b/src/python/m5/event.py @@ -0,0 +1,42 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from internal.event import create +from internal.event import SimLoopExitEvent as SimExit + +class ProgressEvent(object): + def __init__(self, period): + self.period = int(period) + self.schedule() + + def schedule(self): + create(self, m5.curTick() + self.period) + + def __call__(self): + print "Progress! Time now %fs" % (m5.curTick()/1e12) + self.schedule() diff --git a/src/python/m5/main.py b/src/python/m5/main.py index 54368b91e..1695ed75f 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -188,6 +188,7 @@ def parse_args(): def main(): import defines + import event import info import internal @@ -295,7 +296,7 @@ def main(): if options.trace_start: def enable_trace(): internal.trace.cvar.enabled = True - internal.event.create(enable_trace, int(options.trace_start)) + event.create(enable_trace, int(options.trace_start)) else: internal.trace.cvar.enabled = True diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 67a28a61e..986220c3f 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -47,8 +47,8 @@ class BaseCPU(SimObject): defer_registration = Param.Bool(False, "defer registration with system (for sampling)") - clock = Param.Clock(Parent.clock, "clock speed") - phase = Param.Latency("0ns", "clock phase") + clock = Param.Clock('1t', "clock speed") + phase = Param.Latency('0ns', "clock phase") _mem_ports = [] diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py index b8df6229e..c389e4a7f 100644 --- a/src/python/m5/objects/PhysicalMemory.py +++ b/src/python/m5/objects/PhysicalMemory.py @@ -8,7 +8,7 @@ class PhysicalMemory(MemObject): functional = Port("Functional Access Port") range = Param.AddrRange(AddrRange('128MB'), "Device Address") file = Param.String('', "memory mapped file") - latency = Param.Latency(Parent.clock, "latency of an access") + latency = Param.Latency('1t', "latency of an access") zero = Param.Bool(False, "zero initialize memory") class DRAMMemory(PhysicalMemory): diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py index 8db4fa5a2..2b0e736e7 100644 --- a/src/python/m5/objects/Root.py +++ b/src/python/m5/objects/Root.py @@ -3,9 +3,4 @@ from m5.params import * class Root(SimObject): type = 'Root' - clock = Param.RootClock('1THz', "tick frequency") - max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)") - progress_interval = Param.Tick('0', - "print a progress message every n ticks (0 = never)") - output_file = Param.String('cout', "file to dump simulator output to") - checkpoint = Param.String('', "checkpoint file to load") + dummy = Param.Int(0, "We don't support objects without params") diff --git a/src/python/m5/params.py b/src/python/m5/params.py index e71e1c3c5..9892df97c 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -51,6 +51,7 @@ import sys import time import convert +import ticks from util import * # Dummy base class to identify types that are legitimate for SimObject @@ -360,6 +361,7 @@ class MemorySize(CheckedInt): self._check() class MemorySize32(CheckedInt): + cxx_type = 'uint32_t' size = 32 unsigned = True def __init__(self, value): @@ -632,47 +634,29 @@ class Enum(ParamValue): def __str__(self): return self.value -ticks_per_sec = None - # how big does a rounding error need to be before we warn about it? frequency_tolerance = 0.001 # 0.1% -# convert a floting-point # of ticks to integer, and warn if rounding -# discards too much precision -def tick_check(float_ticks): - if float_ticks == 0: - return 0 - int_ticks = int(round(float_ticks)) - err = (float_ticks - int_ticks) / float_ticks - if err > frequency_tolerance: - print >> sys.stderr, "Warning: rounding error > tolerance" - print >> sys.stderr, " %f rounded to %d" % (float_ticks, int_ticks) - #raise ValueError - return int_ticks - -def getLatency(value): - if isinstance(value, Latency) or isinstance(value, Clock): - return value.value - elif isinstance(value, Frequency) or isinstance(value, RootClock): - return 1 / value.value - elif isinstance(value, str): - try: - return convert.toLatency(value) - except ValueError: - try: - return 1 / convert.toFrequency(value) - except ValueError: - pass # fall through - raise ValueError, "Invalid Frequency/Latency value '%s'" % value - - -class Latency(NumericParamValue): +class TickParamValue(NumericParamValue): cxx_type = 'Tick' cxx_predecls = ['#include "sim/host.hh"'] swig_predecls = ['%import "python/m5/swig/stdint.i"\n' + '%import "sim/host.hh"'] + +class Latency(TickParamValue): def __init__(self, value): - self.value = getLatency(value) + if isinstance(value, (Latency, Clock)): + self.ticks = value.ticks + self.value = value.value + elif isinstance(value, Frequency): + self.ticks = value.ticks + self.value = 1.0 / value.value + elif value.endswith('t'): + self.ticks = True + self.value = int(value[:-1]) + else: + self.ticks = False + self.value = convert.toLatency(value) def __getattr__(self, attr): if attr in ('latency', 'period'): @@ -683,15 +667,25 @@ class Latency(NumericParamValue): # convert latency to ticks def ini_str(self): - return str(tick_check(self.value * ticks_per_sec)) + if self.ticks or self.value == 0: + return '%d' % self.value + else: + return '%d' % (ticks.fromSeconds(self.value)) -class Frequency(NumericParamValue): - cxx_type = 'Tick' - cxx_predecls = ['#include "sim/host.hh"'] - swig_predecls = ['%import "python/m5/swig/stdint.i"\n' + - '%import "sim/host.hh"'] +class Frequency(TickParamValue): def __init__(self, value): - self.value = 1 / getLatency(value) + if isinstance(value, (Latency, Clock)): + if value.value == 0: + self.value = 0 + else: + self.value = 1.0 / value.value + self.ticks = value.ticks + elif isinstance(value, Frequency): + self.value = value.value + self.ticks = value.ticks + else: + self.ticks = False + self.value = convert.toFrequency(value) def __getattr__(self, attr): if attr == 'frequency': @@ -700,30 +694,12 @@ class Frequency(NumericParamValue): return Latency(self) raise AttributeError, "Frequency object has no attribute '%s'" % attr - # convert frequency to ticks per period - def ini_str(self): - return self.period.ini_str() - -# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz). -# We can't inherit from Frequency because we don't want it to be directly -# assignable to a regular Frequency parameter. -class RootClock(ParamValue): - cxx_type = 'Tick' - cxx_predecls = ['#include "sim/host.hh"'] - swig_predecls = ['%import "python/m5/swig/stdint.i"\n' + - '%import "sim/host.hh"'] - def __init__(self, value): - self.value = 1 / getLatency(value) - - def __getattr__(self, attr): - if attr == 'frequency': - return Frequency(self) - if attr in ('latency', 'period'): - return Latency(self) - raise AttributeError, "Frequency object has no attribute '%s'" % attr - + # convert latency to ticks def ini_str(self): - return str(tick_check(self.value)) + if self.ticks or self.value == 0: + return '%d' % self.value + else: + return '%d' % (ticks.fromSeconds(1.0 / self.value)) # A generic frequency and/or Latency value. Value is stored as a latency, # but to avoid ambiguity this object does not support numeric ops (* or /). @@ -734,7 +710,18 @@ class Clock(ParamValue): swig_predecls = ['%import "python/m5/swig/stdint.i"\n' + '%import "sim/host.hh"'] def __init__(self, value): - self.value = getLatency(value) + if isinstance(value, (Latency, Clock)): + self.ticks = value.ticks + self.value = value.value + elif isinstance(value, Frequency): + self.ticks = value.ticks + self.value = 1.0 / value.value + elif value.endswith('t'): + self.ticks = True + self.value = int(value[:-1]) + else: + self.ticks = False + self.value = convert.anyToLatency(value) def __getattr__(self, attr): if attr == 'frequency': @@ -749,18 +736,23 @@ class Clock(ParamValue): class NetworkBandwidth(float,ParamValue): cxx_type = 'float' def __new__(cls, value): - val = convert.toNetworkBandwidth(value) / 8.0 + # convert to bits per second + val = convert.toNetworkBandwidth(value) return super(cls, NetworkBandwidth).__new__(cls, val) def __str__(self): return str(self.val) def ini_str(self): - return '%f' % (ticks_per_sec / float(self)) + # convert to seconds per byte + value = 8.0 / float(self) + # convert to ticks per byte + return '%f' % (ticks.fromSeconds(value)) class MemoryBandwidth(float,ParamValue): cxx_type = 'float' def __new__(self, value): + # we want the number of ticks per byte of data val = convert.toMemoryBandwidth(value) return super(cls, MemoryBandwidth).__new__(cls, val) @@ -768,7 +760,10 @@ class MemoryBandwidth(float,ParamValue): return str(self.val) def ini_str(self): - return '%f' % (ticks_per_sec / float(self)) + # convert to seconds per byte + value = 1.0 / float(self) + # convert to ticks per byte + return '%f' % (ticks.fromSeconds(value)) # # "Constants"... handy aliases for various values. @@ -1023,7 +1018,7 @@ __all__ = ['Param', 'VectorParam', 'Counter', 'Addr', 'Tick', 'Percent', 'TcpPort', 'UdpPort', 'EthernetAddr', 'MemorySize', 'MemorySize32', - 'Latency', 'Frequency', 'RootClock', 'Clock', + 'Latency', 'Frequency', 'Clock', 'NetworkBandwidth', 'MemoryBandwidth', 'Range', 'AddrRange', 'TickRange', 'MaxAddr', 'MaxTick', 'AllMemory', diff --git a/src/python/m5/ticks.py b/src/python/m5/ticks.py new file mode 100644 index 000000000..e91b470ff --- /dev/null +++ b/src/python/m5/ticks.py @@ -0,0 +1,89 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +import sys + +import convert +import internal + +tps = 1.0e12 # default to 1 THz (1 Tick == 1 ps) +tps_fixed = False # once set to true, can't be changed + +# fix the global frequency and tell C++ about it +def fixGlobalFrequency(): + global tps, tps_fixed + if not tps_fixed: + tps_fixed = True + internal.core.setClockFrequency(int(tps)) + print "Global frequency set at %d ticks per second" % int(tps) + +def setGlobalFrequency(ticksPerSecond): + global tps, tps_fixed + + if tps_fixed: + raise AttributeError, \ + "Global frequency already fixed at %f ticks/s." % tps + + if isinstance(ticksPerSecond, (int, long)): + tps = ticksPerSecond + elif isinstance(ticksPerSecond, float): + tps = ticksPerSecond + elif isinstance(ticksPerSecond, str): + tps = round(convert.anyToFrequency(ticksPerSecond)) + else: + raise TypeError, \ + "wrong type '%s' for ticksPerSecond" % type(ticksPerSecond) + +# how big does a rounding error need to be before we warn about it? +frequency_tolerance = 0.001 # 0.1% + +def fromSeconds(value): + if not isinstance(value, float): + raise TypeError, "can't convert '%s' to type tick" % type(value) + + # once someone needs to convert to seconds, the global frequency + # had better be fixed + if not tps_fixed: + raise AttributeError, \ + "In order to do conversions, the global frequency must be fixed" + + if value == 0: + return 0 + + # convert the value from time to ticks + value *= tps + + int_value = int(round(value)) + err = (value - int_value) / value + if err > frequency_tolerance: + print >>sys.stderr, "Warning: rounding error > tolerance" + print >>sys.stderr, " %f rounded to %d" % (value, int_value) + return int_value + +__all__ = [ 'setGlobalFrequency', 'fixGlobalFrequency', 'fromSeconds', + 'frequency_tolerance' ] diff --git a/src/python/swig/core.i b/src/python/swig/core.i index 116890763..3edfa4c7e 100644 --- a/src/python/swig/core.i +++ b/src/python/swig/core.i @@ -41,15 +41,23 @@ extern const char *compileDate; %} +%include "stdint.i" %include "std_string.i" +%include "sim/host.hh" void setOutputDir(const std::string &dir); +void setOutputFile(const std::string &file); void loadIniFile(PyObject *); void SimStartup(); void doExitCleanup(); char *compileDate; +void setClockFrequency(Tick ticksPerSecond); + +%immutable curTick; +Tick curTick; + %wrapper %{ // fix up module name to reflect the fact that it's inside the m5 package #undef SWIG_name diff --git a/src/python/swig/event.i b/src/python/swig/event.i index 51d7d89f0..9a2093c99 100644 --- a/src/python/swig/event.i +++ b/src/python/swig/event.i @@ -53,9 +53,6 @@ class CountedDrainEvent : public Event { CountedDrainEvent *createCountedDrain(); void cleanupCountedDrain(Event *drain_event); -%immutable curTick; -Tick curTick; - // minimal definition of SimExitEvent interface to wrap class SimLoopExitEvent { public: @@ -74,8 +71,6 @@ class SimLoopExitEvent { SimLoopExitEvent *simulate(Tick num_cycles = MaxTick); void exitSimLoop(const std::string &message, int exit_code); -Tick curTick; - %wrapper %{ // fix up module name to reflect the fact that it's inside the m5 package #undef SWIG_name diff --git a/src/sim/builder.cc b/src/sim/builder.cc index 8ef54ce52..532df36b1 100644 --- a/src/sim/builder.cc +++ b/src/sim/builder.cc @@ -35,7 +35,7 @@ #include "sim/builder.hh" #include "sim/host.hh" #include "sim/sim_object.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/sim/byteswap.hh b/src/sim/byteswap.hh index cbc0b5088..062fc4513 100644 --- a/src/sim/byteswap.hh +++ b/src/sim/byteswap.hh @@ -37,6 +37,7 @@ #ifndef __SIM_BYTE_SWAP_HH__ #define __SIM_BYTE_SWAP_HH__ +#include "base/bigint.hh" #include "base/misc.hh" #include "sim/host.hh" @@ -109,7 +110,7 @@ swap_byte16(uint16_t x) // This function lets the compiler figure out how to call the // swap_byte functions above for different data types. Since the -// sizeof() values are known at compiel time, it should inline to a +// sizeof() values are known at compile time, it should inline to a // direct call to the right swap_byteNN() function. template <typename T> static inline T swap_byte(T x) { @@ -125,6 +126,22 @@ static inline T swap_byte(T x) { panic("Can't byte-swap values larger than 64 bits"); } +template<> +static inline Twin64_t swap_byte<Twin64_t>(Twin64_t x) +{ + x.a = swap_byte(x.a); + x.b = swap_byte(x.b); + return x; +} + +template<> +static inline Twin32_t swap_byte<Twin32_t>(Twin32_t x) +{ + x.a = swap_byte(x.a); + x.b = swap_byte(x.b); + return x; +} + //The conversion functions with fixed endianness on both ends don't need to //be in a namespace template <typename T> static inline T betole(T value) {return swap_byte(value);} diff --git a/src/sim/core.cc b/src/sim/core.cc index 24cc33da2..c961e9eb8 100644 --- a/src/sim/core.cc +++ b/src/sim/core.cc @@ -34,15 +34,78 @@ #include "base/callback.hh" #include "base/output.hh" +#include "sim/core.hh" using namespace std; +Tick curTick = 0; + +namespace Clock { +/// The simulated frequency of curTick. (In ticks per second) +Tick Frequency; + +namespace Float { +double s; +double ms; +double us; +double ns; +double ps; + +double Hz; +double kHz; +double MHz; +double GHZ; +/* namespace Float */ } + +namespace Int { +Tick s; +Tick ms; +Tick us; +Tick ns; +Tick ps; +/* namespace Float */ } + +/* namespace Clock */ } + +void +setClockFrequency(Tick ticksPerSecond) +{ + using namespace Clock; + Frequency = ticksPerSecond; + Float::s = static_cast<double>(Frequency); + Float::ms = Float::s / 1.0e3; + Float::us = Float::s / 1.0e6; + Float::ns = Float::s / 1.0e9; + Float::ps = Float::s / 1.0e12; + + Float::Hz = 1.0 / Float::s; + Float::kHz = 1.0 / Float::ms; + Float::MHz = 1.0 / Float::us; + Float::GHZ = 1.0 / Float::ns; + + Int::s = Frequency; + Int::ms = Int::s / 1000; + Int::us = Int::ms / 1000; + Int::ns = Int::us / 1000; + Int::ps = Int::ns / 1000; + +} + void setOutputDir(const string &dir) { simout.setDirectory(dir); } +ostream *outputStream; +ostream *configStream; + +void +setOutputFile(const string &file) +{ + outputStream = simout.find(file); +} + /** * Queue of C++ callbacks to invoke on simulator exit. */ @@ -74,3 +137,4 @@ doExitCleanup() cout.flush(); } + diff --git a/src/sim/core.hh b/src/sim/core.hh index 2ef21c4b6..7360032c2 100644 --- a/src/sim/core.hh +++ b/src/sim/core.hh @@ -29,12 +29,57 @@ * Steve Reinhardt */ -#include <Python.h> +#ifndef __SIM_CORE_HH__ +#define __SIM_CORE_HH__ + #include <string> -#include "base/callback.hh" +#include "sim/host.hh" + +/// The universal simulation clock. +extern Tick curTick; +const Tick retryTime = 1000; + +namespace Clock { +/// The simulated frequency of curTick. +extern Tick Frequency; + +namespace Float { +extern double s; +extern double ms; +extern double us; +extern double ns; +extern double ps; + +extern double Hz; +extern double kHz; +extern double MHz; +extern double GHZ; +/* namespace Float */ } +namespace Int { +extern Tick s; +extern Tick ms; +extern Tick us; +extern Tick ns; +extern Tick ps; +/* namespace Int */ } +/* namespace Clock */ } + +void setClockFrequency(Tick ticksPerSecond); + +/// Output stream for simulator messages (e.g., cprintf()). Also used +/// as default stream for tracing and DPRINTF() messages (unless +/// overridden with trace:file option). +extern std::ostream *outputStream; +void setOutputFile(const std::string &file); void setOutputDir(const std::string &dir); +/// Output stream for configuration dump. +extern std::ostream *configStream; + +struct Callback; void registerExitCallback(Callback *callback); void doExitCleanup(); + +#endif /* __SIM_CORE_HH__ */ diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc index 356472d9a..bcd0d3df3 100644 --- a/src/sim/eventq.cc +++ b/src/sim/eventq.cc @@ -41,7 +41,7 @@ #include "sim/eventq.hh" #include "base/trace.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/sim/faults.cc b/src/sim/faults.cc index cea35482a..b09bbc177 100644 --- a/src/sim/faults.cc +++ b/src/sim/faults.cc @@ -29,10 +29,13 @@ * Gabe Black */ +#include "arch/isa_traits.hh" #include "base/misc.hh" -#include "sim/faults.hh" #include "cpu/thread_context.hh" #include "cpu/base.hh" +#include "sim/faults.hh" +#include "sim/process.hh" +#include "mem/page_table.hh" #if !FULL_SYSTEM void FaultBase::invoke(ThreadContext * tc) @@ -53,3 +56,26 @@ void UnimpFault::invoke(ThreadContext * tc) { panic("Unimpfault: %s\n", panicStr.c_str()); } +#if !FULL_SYSTEM +void PageTableFault::invoke(ThreadContext *tc) +{ + Process *p = tc->getProcessPtr(); + + // We've accessed the next page of the stack, so extend the stack + // to cover it. + if(vaddr < p->stack_min && vaddr >= p->stack_min - TheISA::PageBytes) + { + p->stack_min -= TheISA::PageBytes; + if(p->stack_base - p->stack_min > 8*1024*1024) + fatal("Over max stack size for one thread\n"); + p->pTable->allocate(p->stack_min, TheISA::PageBytes); + warn("Increasing stack size by one page."); + } + // Otherwise, we have an unexpected page fault. Report that fact, + // and what address was accessed to cause the fault. + else + { + panic("Page table fault when accessing virtual address %#x\n", vaddr); + } +} +#endif diff --git a/src/sim/faults.hh b/src/sim/faults.hh index 00264d8fc..2f0b5af62 100644 --- a/src/sim/faults.hh +++ b/src/sim/faults.hh @@ -76,4 +76,16 @@ class UnimpFault : public FaultBase void invoke(ThreadContext * tc); }; +#if !FULL_SYSTEM +class PageTableFault : public FaultBase +{ + private: + Addr vaddr; + public: + FaultName name() {return "M5 page table fault";} + PageTableFault(Addr va) : vaddr(va) {} + void invoke(ThreadContext * tc); +}; +#endif + #endif // __FAULTS_HH__ diff --git a/src/sim/main.cc b/src/sim/main.cc index 0341b7d5f..5bf4add4b 100644 --- a/src/sim/main.cc +++ b/src/sim/main.cc @@ -40,7 +40,7 @@ #include "python/swig/init.hh" #include "sim/async.hh" #include "sim/host.hh" -#include "sim/root.hh" +#include "sim/core.hh" using namespace std; diff --git a/src/sim/process.cc b/src/sim/process.cc index 130c81b01..2b283c9d1 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -61,7 +61,7 @@ #elif THE_ISA == MIPS_ISA #include "arch/mips/linux/process.hh" #elif THE_ISA == X86_ISA -//XXX There are no x86 processes yet +#include "arch/x86/linux/process.hh" #else #error "THE_ISA not set" #endif @@ -490,15 +490,15 @@ LiveProcess::create(const std::string &nm, System *system, int stdin_fd, } #elif THE_ISA == X86_ISA if (objFile->getArch() != ObjectFile::X86) - fatal("Object file architecture does not match compiled ISA (SPARC)."); - panic("There are no implemented x86 processes!\n"); + fatal("Object file architecture does not match compiled ISA (x86)."); switch (objFile->getOpSys()) { - /*case ObjectFile::Linux: + case ObjectFile::Linux: process = new X86LinuxProcess(nm, objFile, system, stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd, _uid, _euid, _gid, - _egid, _pid, _ppid);*/ + _egid, _pid, _ppid); + break; default: fatal("Unknown/unsupported operating system."); } diff --git a/src/sim/root.cc b/src/sim/root.cc index 565b57269..f4743af0a 100644 --- a/src/sim/root.cc +++ b/src/sim/root.cc @@ -36,91 +36,24 @@ #include <vector> #include "base/misc.hh" -#include "base/output.hh" #include "sim/builder.hh" -#include "sim/host.hh" -#include "sim/sim_events.hh" -#include "sim/sim_exit.hh" #include "sim/sim_object.hh" -#include "sim/root.hh" - -using namespace std; - -Tick curTick = 0; -ostream *outputStream; -ostream *configStream; - -/// The simulated frequency of curTick. (This is only here for a short time) -Tick ticksPerSecond; - -namespace Clock { -/// The simulated frequency of curTick. (In ticks per second) -Tick Frequency; - -namespace Float { -double s; -double ms; -double us; -double ns; -double ps; - -double Hz; -double kHz; -double MHz; -double GHZ; -/* namespace Float */ } - -namespace Int { -Tick s; -Tick ms; -Tick us; -Tick ns; -Tick ps; -/* namespace Float */ } - -/* namespace Clock */ } - // Dummy Object -class Root : public SimObject +struct Root : public SimObject { - private: - Tick max_tick; - Tick progress_interval; - - public: - Root(const std::string &name, Tick maxtick, Tick pi) - : SimObject(name), max_tick(maxtick), progress_interval(pi) - {} - - virtual void startup(); + Root(const std::string &name) : SimObject(name) {} }; -void -Root::startup() -{ - if (max_tick != 0) - schedExitSimLoop("reached maximum cycle count", curTick + max_tick); - - if (progress_interval != 0) - new ProgressEvent(&mainEventQueue, progress_interval); -} - BEGIN_DECLARE_SIM_OBJECT_PARAMS(Root) - Param<Tick> clock; - Param<Tick> max_tick; - Param<Tick> progress_interval; - Param<string> output_file; + Param<int> dummy; // needed below END_DECLARE_SIM_OBJECT_PARAMS(Root) BEGIN_INIT_SIM_OBJECT_PARAMS(Root) - INIT_PARAM(clock, "tick frequency"), - INIT_PARAM(max_tick, "maximum simulation time"), - INIT_PARAM(progress_interval, "print a progress message"), - INIT_PARAM(output_file, "file to dump simulator output to") + INIT_PARAM(dummy, "") // All SimObjects must have params END_INIT_SIM_OBJECT_PARAMS(Root) @@ -132,29 +65,7 @@ CREATE_SIM_OBJECT(Root) created = true; - outputStream = simout.find(output_file); - Root *root = new Root(getInstanceName(), max_tick, progress_interval); - - using namespace Clock; - Frequency = clock; - Float::s = static_cast<double>(Frequency); - Float::ms = Float::s / 1.0e3; - Float::us = Float::s / 1.0e6; - Float::ns = Float::s / 1.0e9; - Float::ps = Float::s / 1.0e12; - - Float::Hz = 1.0 / Float::s; - Float::kHz = 1.0 / Float::ms; - Float::MHz = 1.0 / Float::us; - Float::GHZ = 1.0 / Float::ns; - - Int::s = Frequency; - Int::ms = Int::s / 1000; - Int::us = Int::ms / 1000; - Int::ns = Int::us / 1000; - Int::ps = Int::ns / 1000; - - return root; + return new Root(getInstanceName()); } REGISTER_SIM_OBJECT("Root", Root) diff --git a/src/sim/sim_events.cc b/src/sim/sim_events.cc index 2ccc9dad2..a4457a11c 100644 --- a/src/sim/sim_events.cc +++ b/src/sim/sim_events.cc @@ -158,21 +158,3 @@ CheckSwapEvent::description() { return "check swap"; } - -// -// handle progress event: print message and reschedule -// -void -ProgressEvent::process() -{ - DPRINTFN("ProgressEvent\n"); - // reschedule for next interval - schedule(curTick + interval); -} - - -const char * -ProgressEvent::description() -{ - return "progress message"; -} diff --git a/src/sim/sim_events.hh b/src/sim/sim_events.hh index e1576b38c..94e2540b1 100644 --- a/src/sim/sim_events.hh +++ b/src/sim/sim_events.hh @@ -125,23 +125,4 @@ class CheckSwapEvent : public Event virtual const char *description(); }; -// -// Progress event: print out cycle every so often so we know we're -// making forward progress. -// -class ProgressEvent : public Event -{ - protected: - Tick interval; - - public: - ProgressEvent(EventQueue *q, Tick ival) - : Event(q), interval(ival) - { schedule(curTick + interval); } - - void process(); // process event - - virtual const char *description(); -}; - #endif // __SIM_SIM_EVENTS_HH__ |