diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/SConscript | 1 | ||||
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 17 | ||||
| -rw-r--r-- | src/cpu/o3/decode_impl.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/dyn_inst.hh | 11 | ||||
| -rw-r--r-- | src/cpu/o3/dyn_inst_impl.hh | 9 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/iew_impl.hh | 8 | ||||
| -rw-r--r-- | src/cpu/o3/inst_queue_impl.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 4 |
9 files changed, 62 insertions, 0 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript index edb4b2702..b24866ddd 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -173,6 +173,7 @@ DebugFlag('ExecKernel') DebugFlag('ExecAsid') DebugFlag('Fetch') DebugFlag('IntrControl') +DebugFlag('O3PipeView') DebugFlag('PCEvent') DebugFlag('Quiesce') diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 9225f525f..f579305dc 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -58,6 +58,7 @@ #include "debug/Commit.hh" #include "debug/CommitRate.hh" #include "debug/ExecFaulting.hh" +#include "debug/O3PipeView.hh" #include "params/DerivO3CPU.hh" #include "sim/faults.hh" @@ -1207,6 +1208,22 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num) // Finally clear the head ROB entry. rob->retireHead(tid); +#if TRACING_ON + // Print info needed by the pipeline activity viewer. + DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n", + head_inst->fetchTick, + head_inst->instAddr(), + head_inst->microPC(), + head_inst->seqNum, + head_inst->staticInst->disassemble(head_inst->instAddr())); + DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick); + DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick); + DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick); + DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick); + DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick); + DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick()); +#endif + // If this was a store, record it for this cycle. if (head_inst->isStore()) committedStores[tid] = true; diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index 4beabbc02..67d32f0fe 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -706,6 +706,10 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid) ++decodeDecodedInsts; --insts_available; +#if TRACING_ON + inst->decodeTick = curTick(); +#endif + // Ensure that if it was predicted as a branch, it really is a // branch. if (inst->readPredTaken() && !inst->isControl()) { diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 2e434ea02..5fe1b2609 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -123,6 +123,17 @@ class BaseO3DynInst : public BaseDynInst<Impl> int _numDestMiscRegs; public: + +#if TRACING_ON + /** Tick records used for the pipeline activity viewer. */ + Tick fetchTick; + Tick decodeTick; + Tick renameTick; + Tick dispatchTick; + Tick issueTick; + Tick completeTick; +#endif + /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh index 89d6528a1..9216c5fa7 100644 --- a/src/cpu/o3/dyn_inst_impl.hh +++ b/src/cpu/o3/dyn_inst_impl.hh @@ -85,6 +85,15 @@ BaseO3DynInst<Impl>::initVars() } _numDestMiscRegs = 0; + +#if TRACING_ON + fetchTick = 0; + decodeTick = 0; + renameTick = 0; + dispatchTick = 0; + issueTick = 0; + completeTick = 0; +#endif } template <class Impl> diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index c58892e84..832ca3767 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1312,6 +1312,10 @@ DefaultFetch<Impl>::fetch(bool &status_change) numInst++; +#if TRACING_ON + instruction->fetchTick = curTick(); +#endif + nextPC = thisPC; // If we're branching after this instruction, quite fetching diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 00a7ef0d9..aceca3c93 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -1147,6 +1147,10 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid) toRename->iewInfo[tid].dispatched++; ++iewDispatchedInsts; + +#if TRACING_ON + inst->dispatchTick = curTick(); +#endif } if (!insts_to_dispatch.empty()) { @@ -1619,6 +1623,10 @@ DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) iewExecutedInsts++; #endif +#if TRACING_ON + inst->completeTick = curTick(); +#endif + // // Control operations // diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 09e925e1d..def2c8f97 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -857,6 +857,10 @@ InstructionQueue<Impl>::scheduleReadyInsts() issuing_inst->setIssued(); ++total_issued; +#if TRACING_ON + issuing_inst->issueTick = curTick(); +#endif + if (!issuing_inst->isMemRef()) { // Memory instructions can not be freed from the IQ until they // complete. diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 25f77ea82..ee67c14f9 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -692,6 +692,10 @@ DefaultRename<Impl>::renameInsts(ThreadID tid) ++renamed_insts; +#if TRACING_ON + inst->renameTick = curTick(); +#endif + // Put instruction in rename queue. toIEW->insts[toIEWIndex] = inst; ++(toIEW->size); |