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-rw-r--r--src/arch/arm/table_walker.cc7
-rw-r--r--src/arch/x86/intmessage.hh2
-rw-r--r--src/arch/x86/pagetable_walker.cc9
-rw-r--r--src/cpu/checker/cpu.cc6
-rw-r--r--src/cpu/checker/cpu_impl.hh4
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc4
-rw-r--r--src/cpu/inorder/resources/cache_unit.hh4
-rw-r--r--src/cpu/o3/fetch_impl.hh3
-rw-r--r--src/cpu/o3/lsq_unit.hh18
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh6
-rw-r--r--src/cpu/ozone/front_end_impl.hh3
-rw-r--r--src/cpu/ozone/lw_lsq.hh5
-rw-r--r--src/cpu/ozone/lw_lsq_impl.hh2
-rw-r--r--src/cpu/simple/atomic.cc9
-rw-r--r--src/cpu/simple/timing.cc7
-rw-r--r--src/cpu/testers/directedtest/InvalidateGenerator.cc4
-rw-r--r--src/cpu/testers/directedtest/SeriesRequestGenerator.cc2
-rw-r--r--src/cpu/testers/memtest/memtest.cc6
-rw-r--r--src/cpu/testers/networktest/networktest.cc3
-rw-r--r--src/cpu/testers/rubytest/Check.cc8
-rw-r--r--src/dev/io_device.cc2
-rw-r--r--src/mem/bridge.cc17
-rw-r--r--src/mem/bridge.hh2
-rw-r--r--src/mem/bus.cc56
-rw-r--r--src/mem/cache/cache_impl.hh6
-rw-r--r--src/mem/cache/prefetch/base.cc2
-rw-r--r--src/mem/cache/tags/iic.cc3
-rw-r--r--src/mem/packet.hh32
-rw-r--r--src/mem/port.cc2
-rw-r--r--src/mem/port_proxy.cc2
-rw-r--r--src/mem/ruby/recorder/CacheRecorder.cc4
-rw-r--r--src/mem/ruby/system/RubyPort.cc2
32 files changed, 117 insertions, 125 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 73a691cff..591c16747 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -235,7 +235,7 @@ TableWalker::processWalk()
f = currState->fault;
} else {
RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId);
- PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
port.sendFunctional(pkt);
doL1Descriptor();
@@ -578,8 +578,9 @@ TableWalker::doL1Descriptor()
currState->tc->getCpuPtr()->ticks(1));
doL2Descriptor();
} else {
- RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, masterId);
- PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0,
+ masterId);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
port.sendFunctional(pkt);
doL2Descriptor();
diff --git a/src/arch/x86/intmessage.hh b/src/arch/x86/intmessage.hh
index 4a165a4a1..6bf180432 100644
--- a/src/arch/x86/intmessage.hh
+++ b/src/arch/x86/intmessage.hh
@@ -82,7 +82,7 @@ namespace X86ISA
RequestPtr req = new Request(x86InterruptAddress(id, offset),
size, Request::UNCACHEABLE,
Request::intMasterId);
- PacketPtr pkt = new Packet(req, MemCmd::MessageReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, MemCmd::MessageReq);
pkt->allocate();
return pkt;
}
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index c07af0c83..9e1d08c7b 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -492,7 +492,7 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
flags.set(Request::UNCACHEABLE, uncacheable);
RequestPtr request =
new Request(nextRead, oldRead->getSize(), flags, walker->masterId);
- read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
+ read = new Packet(request, MemCmd::ReadReq);
read->allocate();
// If we need to write, adjust the read packet to write the modified
// value back to memory.
@@ -500,7 +500,7 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
write = oldRead;
write->set<uint64_t>(pte);
write->cmd = MemCmd::WriteReq;
- write->setDest(Packet::Broadcast);
+ write->clearDest();
} else {
write = NULL;
delete oldRead->req;
@@ -561,8 +561,9 @@ Walker::WalkerState::setupWalk(Addr vaddr)
Request::Flags flags = Request::PHYSICAL;
if (cr3.pcd)
flags.set(Request::UNCACHEABLE);
- RequestPtr request = new Request(topAddr, dataSize, flags, walker->masterId);
- read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
+ RequestPtr request = new Request(topAddr, dataSize, flags,
+ walker->masterId);
+ read = new Packet(request, MemCmd::ReadReq);
read->allocate();
}
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 66341b0e0..901c3900f 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -170,9 +170,9 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
if (fault == NoFault &&
!memReq->getFlags().isSet(Request::NO_ACCESS)) {
PacketPtr pkt = new Packet(memReq,
- memReq->isLLSC() ?
- MemCmd::LoadLockedReq : MemCmd::ReadReq,
- Packet::Broadcast);
+ memReq->isLLSC() ?
+ MemCmd::LoadLockedReq :
+ MemCmd::ReadReq);
pkt->dataStatic(data);
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 167c3531f..dcc6b01f9 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -281,9 +281,7 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
break;
}
} else {
- PacketPtr pkt = new Packet(memReq,
- MemCmd::ReadReq,
- Packet::Broadcast);
+ PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq);
pkt->dataStatic(&machInst);
icachePort->sendFunctional(pkt);
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 10046f7f2..a5bb9cd24 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -814,7 +814,6 @@ CacheUnit::buildDataPacket(CacheRequest *cache_req)
cache_req->dataPkt = new CacheReqPacket(cache_req,
cache_req->pktCmd,
- Packet::Broadcast,
cache_req->instIdx);
DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n",
cache_req->getSlot(),
@@ -1035,8 +1034,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
cpu->dataMasterId(),
0);
- split_pkt = new Packet(cache_req->memReq, cache_req->pktCmd,
- Packet::Broadcast);
+ split_pkt = new Packet(cache_req->memReq, cache_req->pktCmd);
split_pkt->dataStatic(inst->splitMemData);
DPRINTF(InOrderCachePort, "Completing Split Access.\n");
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 3f3ef12e6..f0878d24d 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -252,8 +252,8 @@ class CacheReqPacket : public Packet
{
public:
CacheReqPacket(CacheRequest *_req,
- Command _cmd, short _dest, int _idx = 0)
- : Packet(&(*_req->memReq), _cmd, _dest), cacheReq(_req),
+ Command _cmd, int _idx = 0)
+ : Packet(&(*_req->memReq), _cmd), cacheReq(_req),
instIdx(_idx), hasSlot(false), reqData(NULL), memReq(NULL)
{
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 0ff515855..2480211e4 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -611,8 +611,7 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
}
// Build packet here.
- PacketPtr data_pkt = new Packet(mem_req,
- MemCmd::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(mem_req, MemCmd::ReadReq);
data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
cacheDataPC[tid] = block_PC;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 44898eb38..44c3df0bf 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -605,18 +605,15 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
ThreadContext *thread = cpu->tcBase(lsqID);
Tick delay;
- PacketPtr data_pkt =
- new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
data_pkt->dataStatic(load_inst->memData);
delay = TheISA::handleIprRead(thread, data_pkt);
} else {
assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
- PacketPtr fst_data_pkt =
- new Packet(sreqLow, MemCmd::ReadReq, Packet::Broadcast);
- PacketPtr snd_data_pkt =
- new Packet(sreqHigh, MemCmd::ReadReq, Packet::Broadcast);
+ PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq);
+ PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq);
fst_data_pkt->dataStatic(load_inst->memData);
snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
@@ -689,8 +686,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
"addr %#x, data %#x\n",
store_idx, req->getVaddr(), data);
- PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
- Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
data_pkt->dataStatic(load_inst->memData);
WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
@@ -772,7 +768,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
if (!lsq->cacheBlocked()) {
MemCmd command =
req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq;
- PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, command);
PacketPtr fst_data_pkt = NULL;
PacketPtr snd_data_pkt = NULL;
@@ -791,8 +787,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
} else {
// Create the split packets.
- fst_data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
- snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
+ fst_data_pkt = new Packet(sreqLow, command);
+ snd_data_pkt = new Packet(sreqHigh, command);
fst_data_pkt->dataStatic(load_inst->memData);
snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 2de349242..f4182e30d 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -823,13 +823,13 @@ LSQUnit<Impl>::writebackStores()
if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
// Build a single data packet if the store isn't split.
- data_pkt = new Packet(req, command, Packet::Broadcast);
+ data_pkt = new Packet(req, command);
data_pkt->dataStatic(inst->memData);
data_pkt->senderState = state;
} else {
// Create two packets if the store is split in two.
- data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
- snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
+ data_pkt = new Packet(sreqLow, command);
+ snd_data_pkt = new Packet(sreqHigh, command);
data_pkt->dataStatic(inst->memData);
snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 12aa0a321..66bcc6227 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -477,8 +477,7 @@ FrontEnd<Impl>::fetchCacheLine()
#endif
// Build packet here.
- PacketPtr data_pkt = new Packet(memReq,
- Packet::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(memReq, Packet::ReadReq);
data_pkt->dataStatic(cacheData);
if (!icachePort.sendTiming(data_pkt)) {
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index a581b242f..db8e53b43 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -571,7 +571,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
(*sq_it).inst->seqNum, inst->seqNum, req->getVaddr(),
*(inst->memData));
- PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, Packet::ReadReq);
data_pkt->dataStatic(inst->memData);
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
@@ -635,8 +635,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
PacketPtr data_pkt =
new Packet(req,
(req->isLLSC() ?
- MemCmd::LoadLockedReq : Packet::ReadReq),
- Packet::Broadcast);
+ MemCmd::LoadLockedReq : Packet::ReadReq));
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index c0c6d7276..79b2b8f16 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -577,7 +577,7 @@ OzoneLWLSQ<Impl>::writebackStores()
MemCmd command =
req->isSwap() ? MemCmd::SwapReq :
(req->isLLSC() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
- PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, command);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 90f4fa579..87f41a721 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -272,8 +272,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
// Now do the access.
if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
Packet pkt = Packet(req,
- req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
- Packet::Broadcast);
+ req->isLLSC() ? MemCmd::LoadLockedReq :
+ MemCmd::ReadReq);
pkt.dataStatic(data);
if (req->isMmappedIpr())
@@ -374,7 +374,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
}
if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
- Packet pkt = Packet(req, cmd, Packet::Broadcast);
+ Packet pkt = Packet(req, cmd);
pkt.dataStatic(data);
if (req->isMmappedIpr()) {
@@ -473,8 +473,7 @@ AtomicSimpleCPU::tick()
//if(predecoder.needMoreBytes())
//{
icache_access = true;
- Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
- Packet::Broadcast);
+ Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq);
ifetch_pkt.dataStatic(&inst);
if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index d52003f19..5dba51842 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -355,7 +355,7 @@ TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
cmd = MemCmd::SwapReq;
}
}
- pkt = new Packet(req, cmd, Packet::Broadcast);
+ pkt = new Packet(req, cmd);
}
void
@@ -376,8 +376,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
buildPacket(pkt2, req2, read);
req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
- PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
- Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
pkt->dataDynamicArray<uint8_t>(data);
pkt1->dataStatic<uint8_t>(data);
@@ -578,7 +577,7 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
if (fault == NoFault) {
DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
req->getVaddr(), req->getPaddr());
- ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ ifetch_pkt = new Packet(req, MemCmd::ReadReq);
ifetch_pkt->dataStatic(&inst);
DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc
index f01e6fb50..4c248ea05 100644
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc
@@ -68,13 +68,13 @@ InvalidateGenerator::initiate()
cmd = MemCmd::ReadReq;
port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester->
getCpuPort(m_active_read_node));
- pkt = new Packet(req, cmd, m_active_read_node);
+ pkt = new Packet(req, cmd);
} else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
DPRINTF(DirectedTest, "initiating invalidating write\n");
cmd = MemCmd::WriteReq;
port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester->
getCpuPort(m_active_inv_node));
- pkt = new Packet(req, cmd, m_active_inv_node);
+ pkt = new Packet(req, cmd);
} else {
panic("initiate was unexpectedly called\n");
}
diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
index 137d24b21..92dc46f85 100644
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
@@ -67,7 +67,7 @@ SeriesRequestGenerator::initiate()
} else {
cmd = MemCmd::ReadReq;
}
- PacketPtr pkt = new Packet(req, cmd, m_active_node);
+ PacketPtr pkt = new Packet(req, cmd);
uint8_t* dummyData = new uint8_t;
*dummyData = 0;
pkt->dataDynamic(dummyData);
diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc
index 7e34c2833..809b4dd93 100644
--- a/src/cpu/testers/memtest/memtest.cc
+++ b/src/cpu/testers/memtest/memtest.cc
@@ -328,8 +328,7 @@ MemTest::tick()
id, do_functional ? "functional " : "", req->getPaddr(),
blockAddr(req->getPaddr()), *result);
- PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
- pkt->setSrc(0);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
@@ -360,8 +359,7 @@ MemTest::tick()
do_functional ? "functional " : "", req->getPaddr(),
blockAddr(req->getPaddr()), data & 0xff);
- PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
- pkt->setSrc(0);
+ PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());
diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc
index 45a414539..aa8b54b8e 100644
--- a/src/cpu/testers/networktest/networktest.cc
+++ b/src/cpu/testers/networktest/networktest.cc
@@ -259,8 +259,7 @@ NetworkTest::generatePkt()
"Generated packet with destination %d, embedded in address %x\n",
destination, req->getPaddr());
- PacketPtr pkt = new Packet(req, requestType, 0);
- pkt->setSrc(0); //Not used
+ PacketPtr pkt = new Packet(req, requestType);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
pkt->senderState = NULL;
diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc
index 6f119af06..892e05dd0 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -108,7 +108,7 @@ Check::initiatePrefetch()
m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
req->setThreadContext(index, 0);
- PacketPtr pkt = new Packet(req, cmd, port->idx);
+ PacketPtr pkt = new Packet(req, cmd);
// push the subblock onto the sender state. The sequencer will
// update the subblock on the return
@@ -149,7 +149,7 @@ Check::initiateFlush()
cmd = MemCmd::FlushReq;
- PacketPtr pkt = new Packet(req, cmd, port->idx);
+ PacketPtr pkt = new Packet(req, cmd);
// push the subblock onto the sender state. The sequencer will
// update the subblock on the return
@@ -191,7 +191,7 @@ Check::initiateAction()
cmd = MemCmd::WriteReq;
// }
- PacketPtr pkt = new Packet(req, cmd, port->idx);
+ PacketPtr pkt = new Packet(req, cmd);
uint8_t* writeData = new uint8_t;
*writeData = m_value + m_store_count;
pkt->dataDynamic(writeData);
@@ -248,7 +248,7 @@ Check::initiateCheck()
m_tester_ptr->masterId(), curTick(), m_pc.getAddress());
req->setThreadContext(index, 0);
- PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
uint8_t* dataArray = new uint8_t[CHECK_SIZE];
pkt->dataDynamicArray(dataArray);
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index e1fc28949..5fadb2f49 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -270,7 +270,7 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
for (ChunkGenerator gen(addr, size, peerBlockSize());
!gen.done(); gen.next()) {
Request *req = new Request(gen.addr(), gen.size(), flag, masterId);
- PacketPtr pkt = new Packet(req, cmd, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, cmd);
// Increment the data pointer on a write
if (data)
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 4dcb2a537..ddbc154c0 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -144,9 +144,8 @@ Bridge::BridgeMasterPort::recvTiming(PacketPtr pkt)
// all checks are done when the request is accepted on the slave
// side, so we are guaranteed to have space for the response
-
- DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n",
- pkt->getSrc(), pkt->getDest(), pkt->getAddr());
+ DPRINTF(BusBridge, "recvTiming: response %s addr 0x%x\n",
+ pkt->cmdString(), pkt->getAddr());
DPRINTF(BusBridge, "Request queue size: %d\n", requestQueue.size());
@@ -161,8 +160,9 @@ Bridge::BridgeSlavePort::recvTiming(PacketPtr pkt)
// should only see requests on the slave side
assert(pkt->isRequest());
- DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n",
- pkt->getSrc(), pkt->getDest(), pkt->getAddr());
+
+ DPRINTF(BusBridge, "recvTiming: request %s addr 0x%x\n",
+ pkt->cmdString(), pkt->getAddr());
DPRINTF(BusBridge, "Response queue size: %d outresp: %d\n",
responseQueue.size(), outstandingResponses);
@@ -277,6 +277,9 @@ Bridge::BridgeSlavePort::queueForSendTiming(PacketPtr pkt)
// from original request
buf->fixResponse(pkt);
+ // the bridge assumes that at least one bus has set the
+ // destination field of the packet
+ assert(pkt->isDestValid());
DPRINTF(BusBridge, "response, new dest %d\n", pkt->getDest());
delete buf;
@@ -304,8 +307,8 @@ Bridge::BridgeMasterPort::trySend()
PacketPtr pkt = buf->pkt;
- DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n",
- buf->origSrc, pkt->getDest(), pkt->getAddr());
+ DPRINTF(BusBridge, "trySend: origSrc %d addr 0x%x\n",
+ buf->origSrc, pkt->getAddr());
// If the send was successful, make sure sender state was set to NULL
// otherwise we could get a NACK back of a packet that didn't expect a
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index 87b327ca3..45c7e3057 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -91,7 +91,7 @@ class Bridge : public MemObject
PacketPtr pkt;
bool nackedHere;
Packet::SenderState *origSenderState;
- short origSrc;
+ Packet::NodeID origSrc;
bool expectResponse;
PacketBuffer(PacketPtr _pkt, Tick t, bool nack = false)
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index eb26e268b..daf69c6df 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -213,24 +213,21 @@ Bus::recvTiming(PacketPtr pkt)
// test if the bus should be considered occupied for the current
// packet, and exclude express snoops from the check
if (!pkt->isExpressSnoop() && isOccupied(pkt, src_port)) {
- DPRINTF(Bus, "recvTiming: src %d dst %d %s 0x%x BUSY\n",
- src_id, pkt->getDest(), pkt->cmdString(), pkt->getAddr());
+ DPRINTF(Bus, "recvTiming: src %s %s 0x%x BUSY\n",
+ src_port->name(), pkt->cmdString(), pkt->getAddr());
return false;
}
- DPRINTF(Bus, "recvTiming: src %d dst %d %s 0x%x\n",
- src_id, pkt->getDest(), pkt->cmdString(), pkt->getAddr());
+ DPRINTF(Bus, "recvTiming: src %s %s 0x%x\n",
+ src_port->name(), pkt->cmdString(), pkt->getAddr());
Tick headerFinishTime = pkt->isExpressSnoop() ? 0 : calcPacketTiming(pkt);
Tick packetFinishTime = pkt->isExpressSnoop() ? 0 : pkt->finishTime;
// decide what to do based on the direction
if (pkt->isRequest()) {
- // the packet is a memory-mapped request and should be broadcasted to
- // our snoopers
- assert(pkt->getDest() == Packet::Broadcast);
-
- // forward to all snoopers but the source
+ // the packet is a memory-mapped request and should be
+ // broadcasted to our snoopers but the source
forwardTiming(pkt, src_id);
// remember if we add an outstanding req so we can undo it if
@@ -262,8 +259,8 @@ Bus::recvTiming(PacketPtr pkt)
if (add_outstanding)
outstandingReq.erase(pkt->req);
- DPRINTF(Bus, "recvTiming: src %d dst %d %s 0x%x RETRY\n",
- src_id, pkt->getDest(), pkt->cmdString(), pkt->getAddr());
+ DPRINTF(Bus, "recvTiming: src %s %s 0x%x RETRY\n",
+ src_port->name(), pkt->cmdString(), pkt->getAddr());
addToRetryList(src_port);
occupyBus(headerFinishTime);
@@ -299,12 +296,11 @@ Bus::recvTimingSnoop(PacketPtr pkt)
Packet::NodeID src_id = pkt->getSrc();
if (pkt->isRequest()) {
- DPRINTF(Bus, "recvTimingSnoop: src %d dst %d %s 0x%x\n",
- src_id, pkt->getDest(), pkt->cmdString(), pkt->getAddr());
+ DPRINTF(Bus, "recvTimingSnoop: src %d %s 0x%x\n",
+ src_id, pkt->cmdString(), pkt->getAddr());
// the packet is an express snoop request and should be
// broadcasted to our snoopers
- assert(pkt->getDest() == Packet::Broadcast);
assert(pkt->isExpressSnoop());
// forward to all snoopers
@@ -326,13 +322,13 @@ Bus::recvTimingSnoop(PacketPtr pkt)
SlavePort* src_port = slavePorts[src_id];
if (isOccupied(pkt, src_port)) {
- DPRINTF(Bus, "recvTimingSnoop: src %d dst %d %s 0x%x BUSY\n",
- src_id, pkt->getDest(), pkt->cmdString(), pkt->getAddr());
+ DPRINTF(Bus, "recvTimingSnoop: src %s %s 0x%x BUSY\n",
+ src_port->name(), pkt->cmdString(), pkt->getAddr());
return false;
}
- DPRINTF(Bus, "recvTimingSnoop: src %d dst %d %s 0x%x\n",
- src_id, pkt->getDest(), pkt->cmdString(), pkt->getAddr());
+ DPRINTF(Bus, "recvTimingSnoop: src %s %s 0x%x\n",
+ src_port->name(), pkt->cmdString(), pkt->getAddr());
// get the destination from the packet
Packet::NodeID dest = pkt->getDest();
@@ -532,11 +528,11 @@ Bus::findPort(Addr addr)
Tick
Bus::recvAtomic(PacketPtr pkt)
{
- DPRINTF(Bus, "recvAtomic: packet src %d dest %d addr 0x%x cmd %s\n",
- pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
+ DPRINTF(Bus, "recvAtomic: packet src %s addr 0x%x cmd %s\n",
+ slavePorts[pkt->getSrc()]->name(), pkt->getAddr(),
+ pkt->cmdString());
// we should always see a request routed based on the address
- assert(pkt->getDest() == Packet::Broadcast);
assert(pkt->isRequest());
// forward to all snoopers but the source
@@ -566,11 +562,11 @@ Bus::recvAtomic(PacketPtr pkt)
Tick
Bus::recvAtomicSnoop(PacketPtr pkt)
{
- DPRINTF(Bus, "recvAtomicSnoop: packet src %d dest %d addr 0x%x cmd %s\n",
- pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
+ DPRINTF(Bus, "recvAtomicSnoop: packet src %s addr 0x%x cmd %s\n",
+ masterPorts[pkt->getSrc()]->name(), pkt->getAddr(),
+ pkt->cmdString());
// we should always see a request routed based on the address
- assert(pkt->getDest() == Packet::Broadcast);
assert(pkt->isRequest());
// forward to all snoopers
@@ -621,7 +617,7 @@ Bus::forwardAtomic(PacketPtr pkt, int exclude_slave_port_id)
// restore original packet state for remaining snoopers
pkt->cmd = orig_cmd;
pkt->setSrc(orig_src_id);
- pkt->setDest(Packet::Broadcast);
+ pkt->clearDest();
}
}
}
@@ -637,13 +633,12 @@ Bus::recvFunctional(PacketPtr pkt)
if (!pkt->isPrint()) {
// don't do DPRINTFs on PrintReq as it clutters up the output
DPRINTF(Bus,
- "recvFunctional: packet src %d dest %d addr 0x%x cmd %s\n",
- pkt->getSrc(), pkt->getDest(), pkt->getAddr(),
+ "recvFunctional: packet src %s addr 0x%x cmd %s\n",
+ slavePorts[pkt->getSrc()]->name(), pkt->getAddr(),
pkt->cmdString());
}
// we should always see a request routed based on the address
- assert(pkt->getDest() == Packet::Broadcast);
assert(pkt->isRequest());
// forward to all snoopers but the source
@@ -664,13 +659,12 @@ Bus::recvFunctionalSnoop(PacketPtr pkt)
if (!pkt->isPrint()) {
// don't do DPRINTFs on PrintReq as it clutters up the output
DPRINTF(Bus,
- "recvFunctionalSnoop: packet src %d dest %d addr 0x%x cmd %s\n",
- pkt->getSrc(), pkt->getDest(), pkt->getAddr(),
+ "recvFunctionalSnoop: packet src %s addr 0x%x cmd %s\n",
+ masterPorts[pkt->getSrc()]->name(), pkt->getAddr(),
pkt->cmdString());
}
// we should always see a request routed based on the address
- assert(pkt->getDest() == Packet::Broadcast);
assert(pkt->isRequest());
// forward to all snoopers
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index fa6f6c860..fcdac1116 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -352,7 +352,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
class ForwardResponseRecord : public Packet::SenderState, public FastAlloc
{
Packet::SenderState *prevSenderState;
- int prevSrc;
+ Packet::NodeID prevSrc;
#ifndef NDEBUG
BaseCache *cache;
#endif
@@ -606,7 +606,7 @@ Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
// block is invalid
cmd = needsExclusive ? MemCmd::ReadExReq : MemCmd::ReadReq;
}
- PacketPtr pkt = new Packet(cpu_pkt->req, cmd, Packet::Broadcast, blkSize);
+ PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
pkt->allocate();
return pkt;
@@ -1002,7 +1002,7 @@ Cache<TagStore>::writebackBlk(BlkType *blk)
Request *writebackReq =
new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0,
Request::wbMasterId);
- PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, -1);
+ PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback);
if (blk->isWritable()) {
writeback->setSupplyExclusive();
}
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 467550823..4d1f7c81c 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -234,7 +234,7 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick time)
// create a prefetch memreq
Request *prefetchReq = new Request(*addrIter, blkSize, 0, masterId);
PacketPtr prefetch =
- new Packet(prefetchReq, MemCmd::HardPFReq, Packet::Broadcast);
+ new Packet(prefetchReq, MemCmd::HardPFReq);
prefetch->allocate();
prefetch->req->setThreadContext(pkt->req->contextId(),
pkt->req->threadId());
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 3501ec378..260b89194 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -370,8 +370,7 @@ IIC::freeReplacementBlock(PacketList & writebacks)
*/
Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
blkSize, 0, Request::wbMasterId);
- PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback,
- -1);
+ PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback);
writeback->allocate();
memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize);
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index ce5748c24..e49fa67b8 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* Copyright (c) 2010 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -317,10 +329,6 @@ class Packet : public FastAlloc, public Printable
/// The time at which the first chunk of the packet will be transmitted
Tick firstWordTime;
- /// The special destination address indicating that the packet
- /// should be routed based on its address.
- static const NodeID Broadcast = -1;
-
/**
* A virtual base opaque structure used to hold state associated
* with the packet but specific to the sending device (e.g., an
@@ -478,6 +486,8 @@ class Packet : public FastAlloc, public Printable
NodeID getDest() const { assert(flags.isSet(VALID_DST)); return dest; }
/// Accessor function to set the destination index of the packet.
void setDest(NodeID _dest) { dest = _dest; flags.set(VALID_DST); }
+ /// Reset destination field, e.g. to turn a response into a request again.
+ void clearDest() { flags.clear(VALID_DST); }
Addr getAddr() const { assert(flags.isSet(VALID_ADDR)); return addr; }
unsigned getSize() const { assert(flags.isSet(VALID_SIZE)); return size; }
@@ -513,9 +523,9 @@ class Packet : public FastAlloc, public Printable
* not be valid. The command and destination addresses must be
* supplied.
*/
- Packet(Request *_req, MemCmd _cmd, NodeID _dest)
- : flags(VALID_DST), cmd(_cmd), req(_req), data(NULL),
- dest(_dest), bytesValidStart(0), bytesValidEnd(0),
+ Packet(Request *_req, MemCmd _cmd)
+ : cmd(_cmd), req(_req), data(NULL),
+ bytesValidStart(0), bytesValidEnd(0),
time(curTick()), senderState(NULL)
{
if (req->hasPaddr()) {
@@ -533,9 +543,9 @@ class Packet : public FastAlloc, public Printable
* a request that is for a whole block, not the address from the
* req. this allows for overriding the size/addr of the req.
*/
- Packet(Request *_req, MemCmd _cmd, NodeID _dest, int _blkSize)
- : flags(VALID_DST), cmd(_cmd), req(_req), data(NULL),
- dest(_dest), bytesValidStart(0), bytesValidEnd(0),
+ Packet(Request *_req, MemCmd _cmd, int _blkSize)
+ : cmd(_cmd), req(_req), data(NULL),
+ bytesValidStart(0), bytesValidEnd(0),
time(curTick()), senderState(NULL)
{
if (req->hasPaddr()) {
@@ -659,7 +669,7 @@ class Packet : public FastAlloc, public Printable
assert(wasNacked());
cmd = origCmd;
assert(needsResponse());
- setDest(Broadcast);
+ clearDest();
}
void
diff --git a/src/mem/port.cc b/src/mem/port.cc
index 92c6aaab8..4b7b040cb 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -120,7 +120,7 @@ void
MasterPort::printAddr(Addr a)
{
Request req(a, 1, 0, Request::funcMasterId);
- Packet pkt(&req, MemCmd::PrintReq, Packet::Broadcast);
+ Packet pkt(&req, MemCmd::PrintReq);
Packet::PrintReqState prs(std::cerr);
pkt.senderState = &prs;
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index c1fd41d3c..38162e1bf 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -48,7 +48,7 @@ PortProxy::blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd) const
for (ChunkGenerator gen(addr, size, _port.peerBlockSize());
!gen.done(); gen.next()) {
req.setPhys(gen.addr(), gen.size(), 0, Request::funcMasterId);
- Packet pkt(&req, cmd, Packet::Broadcast);
+ Packet pkt(&req, cmd);
pkt.dataStatic(p);
_port.sendFunctional(&pkt);
p += gen.size();
diff --git a/src/mem/ruby/recorder/CacheRecorder.cc b/src/mem/ruby/recorder/CacheRecorder.cc
index a886f3238..c5593d945 100644
--- a/src/mem/ruby/recorder/CacheRecorder.cc
+++ b/src/mem/ruby/recorder/CacheRecorder.cc
@@ -77,7 +77,7 @@ CacheRecorder::enqueueNextFlushRequest()
RubySystem::getBlockSizeBytes(),0,
Request::funcMasterId);
MemCmd::Command requestType = MemCmd::FlushReq;
- Packet *pkt = new Packet(req, requestType, -1);
+ Packet *pkt = new Packet(req, requestType);
Sequencer* m_sequencer_ptr = m_seq_map[rec->m_cntrl_id];
assert(m_sequencer_ptr != NULL);
@@ -113,7 +113,7 @@ CacheRecorder::enqueueNextFetchRequest()
RubySystem::getBlockSizeBytes(),0, Request::funcMasterId);
}
- Packet *pkt = new Packet(req, requestType, -1);
+ Packet *pkt = new Packet(req, requestType);
pkt->dataStatic(traceRecord->m_data);
Sequencer* m_sequencer_ptr = m_seq_map[traceRecord->m_cntrl_id];
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 74a60f863..ef9f59645 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -699,7 +699,7 @@ RubyPort::ruby_eviction_callback(const Address& address)
Request req(address.getAddress(), 0, 0, Request::funcMasterId);
for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
if ((*p)->getMasterPort().isSnooping()) {
- Packet *pkt = new Packet(&req, MemCmd::InvalidationReq, -1);
+ Packet *pkt = new Packet(&req, MemCmd::InvalidationReq);
// send as a snoop request
(*p)->sendNextCycle(pkt, true);
}