5 files changed, 0 insertions, 11 deletions
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index aaa0f0b2a..7acd0448a 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -42,8 +42,6 @@ typedef uint64_t ExtMachInst;
 
 typedef GenericISA::SimplePCState<MachInst> PCState;
 
-typedef uint64_t LargestRead;
-
 enum annotes
 {
     ANNOTE_NONE = 0,
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 29828be75..9fd945abe 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -524,9 +524,6 @@ namespace ArmISA
         SXTX = 7
     };
 
-    typedef uint64_t LargestRead;
-    // Need to use 64 bits to make sure that read requests get handled properly
-
     typedef int RegContextParam;
     typedef int RegContextVal;
 
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index c549e81ca..7a8483dcc 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -42,8 +42,6 @@ typedef uint64_t ExtMachInst;
 
 typedef GenericISA::DelaySlotPCState<MachInst> PCState;
 
-typedef uint64_t LargestRead;
-
 //used in FP convert & round function
 enum ConvertType{
     SINGLE_TO_DOUBLE,
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index 7d0a7617c..ec88b9e2c 100644
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -43,8 +43,6 @@ typedef uint64_t ExtMachInst;
 
 typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
 
-typedef Twin64_t LargestRead;
-
 }
 
 #endif
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index ebd88136e..c28336dc9 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -91,8 +91,6 @@ const int SyscallPseudoReturnReg = INTREG_RDX;
 
 typedef uint64_t IntReg;
 typedef uint64_t CCReg;
-//XXX Should this be a 128 bit structure for XMM memory ops?
-typedef uint64_t LargestRead;
 typedef uint64_t MiscReg;
 
 //These floating point types are correct for mmx, but not