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-rw-r--r--src/SConscript7
-rw-r--r--src/arch/alpha/faults.hh6
-rw-r--r--src/arch/alpha/pagetable.hh3
-rw-r--r--src/arch/sparc/faults.cc2
-rw-r--r--src/arch/sparc/isa/base.isa7
-rw-r--r--src/arch/sparc/tlb.hh5
-rw-r--r--src/arch/sparc/utility.hh1
-rw-r--r--src/base/loader/raw_object.cc9
-rw-r--r--src/base/remote_gdb.cc2
-rw-r--r--src/base/trace.hh8
-rw-r--r--src/cpu/base.hh4
-rw-r--r--src/cpu/exetrace.cc32
-rw-r--r--src/cpu/m5legion_interface.h28
-rw-r--r--src/cpu/o3/alpha/cpu_builder.cc12
-rw-r--r--src/cpu/o3/alpha/cpu_impl.hh2
-rw-r--r--src/cpu/ozone/cpu_builder.cc10
-rw-r--r--src/cpu/simple/atomic.cc10
-rw-r--r--src/cpu/simple/timing.cc10
-rw-r--r--src/dev/ethertap.cc14
-rw-r--r--src/dev/ide_atareg.h14
-rw-r--r--src/dev/pcidev.cc54
-rw-r--r--src/python/m5/objects/BaseCPU.py6
-rw-r--r--src/sim/param.hh2
-rw-r--r--src/sim/pseudo_inst.cc48
24 files changed, 192 insertions, 104 deletions
diff --git a/src/SConscript b/src/SConscript
index 44bcb5320..929ed8278 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -316,16 +316,17 @@ else:
makeEnv('debug', '.do',
CCFLAGS = Split('%s -O0' % debug_flag),
- CPPDEFINES = 'DEBUG')
+ CPPDEFINES = ['DEBUG', 'TRACING_ON=1'])
# Optimized binary
makeEnv('opt', '.o',
- CCFLAGS = Split('-g -O3'))
+ CCFLAGS = Split('-g -O3'),
+ CPPDEFINES = ['TRACING_ON=1'])
# "Fast" binary
makeEnv('fast', '.fo', strip = True,
CCFLAGS = Split('-O3'),
- CPPDEFINES = 'NDEBUG')
+ CPPDEFINES = ['NDEBUG', 'TRACING_ON=0'])
# Profiled binary
makeEnv('prof', '.po',
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 3ef4d5521..e2c3441e9 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -32,9 +32,13 @@
#ifndef __ALPHA_FAULTS_HH__
#define __ALPHA_FAULTS_HH__
-#include "arch/alpha/pagetable.hh"
+#include "config/full_system.hh"
#include "sim/faults.hh"
+#if FULL_SYSTEM
+#include "arch/alpha/pagetable.hh"
+#endif
+
// The design of the "name" and "vect" functions is in sim/faults.hh
namespace AlphaISA
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 3108c0a3e..7ec4a6a75 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -38,7 +38,6 @@
namespace AlphaISA {
-#if FULL_SYSTEM
struct VAddr
{
static const int ImplBits = 43;
@@ -106,7 +105,7 @@ namespace AlphaISA {
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
-#endif
+
};
#endif // __ARCH_ALPHA_PAGETABLE_H__
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 2564bc6a9..4cf411d3b 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -494,7 +494,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
{
//XXX The following constant might belong in a header file.
- const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL;
+ const Addr RSTVAddr = 0xFFF0000000ULL;
PC = RSTVAddr | ((TT << 5) & 0xFF);
NPC = PC + sizeof(MachInst);
}
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 122ad2b52..aa24c75be 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -244,7 +244,12 @@ output decoder {{
bool passesCondition(uint32_t codes, uint32_t condition)
{
CondCodes condCodes;
- condCodes.bits = codes;
+ condCodes.bits = 0;
+ condCodes.c = codes & 0x1 ? 1 : 0;
+ condCodes.v = codes & 0x2 ? 1 : 0;
+ condCodes.z = codes & 0x4 ? 1 : 0;
+ condCodes.n = codes & 0x8 ? 1 : 0;
+
switch(condition)
{
case Always:
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 7a9a6aea1..136103f44 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -40,6 +40,9 @@ class ThreadContext;
namespace SparcISA
{
+ const int PAddrImplBits = 40;
+ const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
+
class TLB : public SimObject
{
public:
@@ -59,7 +62,7 @@ namespace SparcISA
{
//For now, always assume the address is already physical.
//Also assume that there are 40 bits of physical address space.
- req->setPaddr(req->getVaddr() & ((1ULL << 40) - 1));
+ req->setPaddr(req->getVaddr() & PAddrImplMask);
return NoFault;
}
};
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index e51677cdf..5c7fe343d 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -33,6 +33,7 @@
#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/tlb.hh"
#include "base/misc.hh"
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"
diff --git a/src/base/loader/raw_object.cc b/src/base/loader/raw_object.cc
index 79ddb81fe..1faf33426 100644
--- a/src/base/loader/raw_object.cc
+++ b/src/base/loader/raw_object.cc
@@ -29,6 +29,7 @@
*/
#include "base/loader/raw_object.hh"
+#include "base/loader/symtab.hh"
#include "base/trace.hh"
ObjectFile *
@@ -62,11 +63,19 @@ RawObject::RawObject(const std::string &_filename, int _fd, size_t _len,
bool
RawObject::loadGlobalSymbols(SymbolTable *symtab)
{
+ int fnameStart = filename.rfind('/',filename.size()) + 1;
+ int extStart = filename.rfind('.',filename.size());
+ symtab->insert(text.baseAddr, filename.substr(fnameStart,
+ extStart-fnameStart) + "_start");
return true;
}
bool
RawObject::loadLocalSymbols(SymbolTable *symtab)
{
+ int fnameStart = filename.rfind('/',filename.size()) + 1;
+ int extStart = filename.rfind('.',filename.size());
+ symtab->insert(text.baseAddr, filename.substr(fnameStart,
+ extStart-fnameStart) + "_start");
return true;
}
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 55fb97ce9..59a9b87d5 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -421,7 +421,7 @@ BaseRemoteGDB::recv(char *bp, int maxlen)
putbyte(bp[0]);
putbyte(bp[1]);
len -= 3;
- bcopy(bp + 3, bp, len);
+ memcpy(bp, bp+3, len);
}
break;
}
diff --git a/src/base/trace.hh b/src/base/trace.hh
index 8df5dd893..9b053990c 100644
--- a/src/base/trace.hh
+++ b/src/base/trace.hh
@@ -39,14 +39,6 @@
#include "sim/host.hh"
#include "sim/root.hh"
-#ifndef TRACING_ON
-#ifndef NDEBUG
-#define TRACING_ON 1
-#else
-#define TRACING_ON 0
-#endif
-#endif
-
#include "base/traceflags.hh"
namespace Trace {
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 9257778ef..788f77e3a 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -155,6 +155,10 @@ class BaseCPU : public MemObject
int cpu_id;
#if FULL_SYSTEM
Tick profile;
+
+ bool do_statistics_insts;
+ bool do_checkpoint_insts;
+ bool do_quiesce;
#endif
Tick progress_interval;
BaseCPU *checker;
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index ef06e0699..113f0fe74 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -39,12 +39,17 @@
#include "arch/regfile.hh"
#include "arch/utility.hh"
#include "base/loader/symtab.hh"
+#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "sim/param.hh"
#include "sim/system.hh"
+#if FULL_SYSTEM
+#include "arch/tlb.hh"
+#endif
+
//XXX This is temporary
#include "arch/isa_specific.hh"
#include "cpu/m5legion_interface.h"
@@ -232,17 +237,22 @@ Trace::InstRecord::dump(ostream &outs)
bool diffPC = false;
bool diffInst = false;
bool diffRegs = false;
+ Addr m5Pc, lgnPc;
+
if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
while (!compared) {
+ m5Pc = PC & TheISA::PAddrImplMask;
+ lgnPc = shared_data->pc & TheISA::PAddrImplMask;
if (shared_data->flags == OWN_M5) {
- if (shared_data->pc != PC)
+ if (lgnPc != m5Pc)
diffPC = true;
if (shared_data->instruction != staticInst->machInst)
diffInst = true;
- for (int i = 0; i < TheISA::NumIntRegs; i++) {
- if (thread->readIntReg(i) != shared_data->intregs[i])
+ for (int i = 0; i < TheISA::NumRegularIntRegs; i++) {
+ if (thread->readIntReg(i) != shared_data->intregs[i]) {
diffRegs = true;
+ }
}
if (diffPC || diffInst || diffRegs ) {
@@ -253,19 +263,19 @@ Trace::InstRecord::dump(ostream &outs)
outs << " [Instruction]";
if (diffRegs)
outs << " [IntRegs]";
- outs << endl << endl;;
+ outs << endl << endl;
- outs << setfill(' ') << setw(15)
+ outs << right << setfill(' ') << setw(15)
<< "M5 PC: " << "0x"<< setw(16) << setfill('0')
- << hex << PC << endl;
+ << hex << m5Pc << endl;
outs << setfill(' ') << setw(15)
<< "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
- << shared_data->pc << endl << endl;
+ << lgnPc << endl << endl;
outs << setfill(' ') << setw(15)
<< "M5 Inst: " << "0x"<< setw(8)
<< setfill('0') << hex << staticInst->machInst
- << staticInst->disassemble(PC, debugSymbolTable)
+ << staticInst->disassemble(m5Pc, debugSymbolTable)
<< endl;
StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread));
@@ -273,7 +283,7 @@ Trace::InstRecord::dump(ostream &outs)
<< " Legion Inst: "
<< "0x" << setw(8) << setfill('0') << hex
<< shared_data->instruction
- << legionInst->disassemble(shared_data->pc, debugSymbolTable)
+ << legionInst->disassemble(lgnPc, debugSymbolTable)
<< endl;
outs << endl;
@@ -386,7 +396,7 @@ Trace::InstRecord::setParams()
// If were going to be in lockstep with Legion
// Setup shared memory, and get otherwise ready
if (flags[LEGION_LOCKSTEP]) {
- int shmfd = shmget(getuid(), sizeof(SharedData), 0777);
+ int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
if (shmfd < 0)
fatal("Couldn't get shared memory fd. Is Legion running?");
@@ -401,6 +411,8 @@ Trace::InstRecord::setParams()
fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
shared_data->version);
+ // step legion forward one cycle so we can get register values
+ shared_data->flags = OWN_LEGION;
}
}
diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h
index 9338d9ca0..373fbeb11 100644
--- a/src/cpu/m5legion_interface.h
+++ b/src/cpu/m5legion_interface.h
@@ -30,7 +30,7 @@
#include <unistd.h>
-#define VERSION 0xA1000002
+#define VERSION 0xA1000005
#define OWN_M5 0x000000AA
#define OWN_LEGION 0x00000055
@@ -41,9 +41,35 @@ typedef struct {
uint32_t version;
uint64_t pc;
+ uint64_t new_pc;
uint32_t instruction;
+ uint32_t new_instruction;
uint64_t intregs[32];
+ uint64_t tpc[8];
+ uint64_t tnpc[8];
+ uint64_t tstate[8];
+ uint16_t tt[8];
+ uint64_t tba;
+
+ uint64_t hpstate;
+ uint64_t htstate[8];
+ uint64_t htba;
+ uint16_t pstate;
+
+ uint64_t y;
+ uint8_t ccr;
+ uint8_t tl;
+ uint8_t gl;
+ uint8_t asi;
+ uint8_t pil;
+
+ uint8_t cwp;
+ uint8_t cansave;
+ uint8_t canrestore;
+ uint8_t otherwin;
+ uint8_t cleanwin;
+
} SharedData;
/** !!! ^^^ Increment VERSION on change ^^^ !!! **/
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index be8ad8de6..09ccc7f65 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -57,6 +57,10 @@ Param<int> cpu_id;
SimObjectParam<AlphaISA::ITB *> itb;
SimObjectParam<AlphaISA::DTB *> dtb;
Param<Tick> profile;
+
+Param<bool> do_quiesce;
+Param<bool> do_checkpoint_insts;
+Param<bool> do_statistics_insts;
#else
SimObjectVectorParam<Process *> workload;
#endif // FULL_SYSTEM
@@ -163,6 +167,10 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
INIT_PARAM(itb, "Instruction translation buffer"),
INIT_PARAM(dtb, "Data translation buffer"),
INIT_PARAM(profile, ""),
+
+ INIT_PARAM(do_quiesce, ""),
+ INIT_PARAM(do_checkpoint_insts, ""),
+ INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "Processes to run"),
#endif // FULL_SYSTEM
@@ -306,6 +314,10 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->itb = itb;
params->dtb = dtb;
params->profile = profile;
+
+ params->do_quiesce = do_quiesce;
+ params->do_checkpoint_insts = do_checkpoint_insts;
+ params->do_statistics_insts = do_statistics_insts;
#else
params->workload = workload;
#endif // FULL_SYSTEM
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 618716fc6..15b50cb15 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -231,7 +231,7 @@ Fault
AlphaO3CPU<Impl>::hwrei(unsigned tid)
{
// Need to clear the lock flag upon returning from an interrupt.
- this->setMiscReg(TheISA::Lock_Flag_DepTag, false, tid);
+ this->setMiscReg(AlphaISA::MISCREG_LOCKFLAG, false, tid);
this->thread[tid]->kernelStats->hwrei();
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 39337dbff..155f0ce09 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -64,6 +64,10 @@ Param<int> cpu_id;
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
+
+Param<bool> do_quiesce;
+Param<bool> do_checkpoint_insts;
+Param<bool> do_statistics_insts
#else
SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;
@@ -184,6 +188,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
INIT_PARAM(itb, "Instruction translation buffer"),
INIT_PARAM(dtb, "Data translation buffer"),
INIT_PARAM(profile, ""),
+ INIT_PARAM(do_quiesce, ""),
+ INIT_PARAM(do_checkpoint_insts, ""),
+ INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "Processes to run"),
// INIT_PARAM(page_table, "Page table"),
@@ -341,6 +348,9 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
params->itb = itb;
params->dtb = dtb;
params->profile = profile;
+ params->do_quiesce = do_quiesce;
+ params->do_checkpoint_insts = do_checkpoint_insts;
+ params->do_statistics_insts = do_statistics_insts;
#else
params->workload = workload;
// params->pTable = page_table;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4f68cfd6f..e9679cc7c 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -500,6 +500,10 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
+
+ Param<bool> do_quiesce;
+ Param<bool> do_checkpoint_insts;
+ Param<bool> do_statistics_insts;
#else
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
@@ -532,6 +536,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(profile, ""),
+ INIT_PARAM(do_quiesce, ""),
+ INIT_PARAM(do_checkpoint_insts, ""),
+ INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
@@ -569,6 +576,9 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
params->itb = itb;
params->dtb = dtb;
params->profile = profile;
+ params->do_quiesce = do_quiesce;
+ params->do_checkpoint_insts = do_checkpoint_insts;
+ params->do_statistics_insts = do_statistics_insts;
#else
params->process = workload;
#endif
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index abf316095..db2c940c0 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -665,6 +665,10 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
+
+ Param<bool> do_quiesce;
+ Param<bool> do_checkpoint_insts;
+ Param<bool> do_statistics_insts;
#else
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
@@ -697,6 +701,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(profile, ""),
+ INIT_PARAM(do_quiesce, ""),
+ INIT_PARAM(do_checkpoint_insts, ""),
+ INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
@@ -732,6 +739,9 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
params->itb = itb;
params->dtb = dtb;
params->profile = profile;
+ params->do_quiesce = do_quiesce;
+ params->do_checkpoint_insts = do_checkpoint_insts;
+ params->do_statistics_insts = do_statistics_insts;
#else
params->process = workload;
#endif
diff --git a/src/dev/ethertap.cc b/src/dev/ethertap.cc
index 2d72383c5..65089a8b2 100644
--- a/src/dev/ethertap.cc
+++ b/src/dev/ethertap.cc
@@ -178,7 +178,7 @@ EtherTap::recvPacket(EthPacketPtr packet)
DPRINTF(Ethernet, "EtherTap output len=%d\n", packet->length);
DDUMP(EthernetData, packet->data, packet->length);
- u_int32_t len = htonl(packet->length);
+ uint32_t len = htonl(packet->length);
write(socket, &len, sizeof(len));
write(socket, packet->data, packet->length);
@@ -199,11 +199,11 @@ EtherTap::process(int revent)
return;
}
- char *data = buffer + sizeof(u_int32_t);
+ char *data = buffer + sizeof(uint32_t);
if (!(revent & POLLIN))
return;
- if (buffer_offset < data_len + sizeof(u_int32_t)) {
+ if (buffer_offset < data_len + sizeof(uint32_t)) {
int len = read(socket, buffer + buffer_offset, buflen - buffer_offset);
if (len == 0) {
detach();
@@ -213,23 +213,23 @@ EtherTap::process(int revent)
buffer_offset += len;
if (data_len == 0)
- data_len = ntohl(*(u_int32_t *)buffer);
+ data_len = ntohl(*(uint32_t *)buffer);
DPRINTF(Ethernet, "Received data from peer: len=%d buffer_offset=%d "
"data_len=%d\n", len, buffer_offset, data_len);
}
- while (data_len != 0 && buffer_offset >= data_len + sizeof(u_int32_t)) {
+ while (data_len != 0 && buffer_offset >= data_len + sizeof(uint32_t)) {
EthPacketPtr packet;
packet = new EthPacketData(data_len);
packet->length = data_len;
memcpy(packet->data, data, data_len);
- buffer_offset -= data_len + sizeof(u_int32_t);
+ buffer_offset -= data_len + sizeof(uint32_t);
assert(buffer_offset >= 0);
if (buffer_offset > 0) {
memmove(buffer, data + data_len, buffer_offset);
- data_len = ntohl(*(u_int32_t *)buffer);
+ data_len = ntohl(*(uint32_t *)buffer);
} else
data_len = 0;
diff --git a/src/dev/ide_atareg.h b/src/dev/ide_atareg.h
index 5320529c8..df16d09d5 100644
--- a/src/dev/ide_atareg.h
+++ b/src/dev/ide_atareg.h
@@ -35,11 +35,25 @@
#if defined(linux)
#include <endian.h>
+#elif defined(__sun__)
+#include <sys/isa_defs.h>
#else
#include <machine/endian.h>
#endif
+#ifdef LITTLE_ENDIAN
#define ATA_BYTE_ORDER LITTLE_ENDIAN
+#elif defined(BIG_ENDIAN)
+#define ATA_BYTE_ORDER BIG_ENDIAN
+#elif defined(_LITTLE_ENDIAN)
+#define ATA_BYTE_ORDER 1
+#define LITTLE_ENDIAN 1
+#elif defined(_BIG_ENDIAN)
+#define ATA_BYTE_ORDER 0
+#define LITTLE_ENDIAN 1
+#else
+#error "No endianess defined"
+#endif
/*
* Drive parameter structure for ATA/ATAPI.
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index 383fc494f..1c2465dd1 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -387,33 +387,33 @@ CREATE_SIM_OBJECT(PciConfigData)
{
PciConfigData *data = new PciConfigData(getInstanceName());
- data->config.vendor = htole(VendorID);
- data->config.device = htole(DeviceID);
- data->config.command = htole(Command);
- data->config.status = htole(Status);
- data->config.revision = htole(Revision);
- data->config.progIF = htole(ProgIF);
- data->config.subClassCode = htole(SubClassCode);
- data->config.classCode = htole(ClassCode);
- data->config.cacheLineSize = htole(CacheLineSize);
- data->config.latencyTimer = htole(LatencyTimer);
- data->config.headerType = htole(HeaderType);
- data->config.bist = htole(BIST);
-
- data->config.baseAddr[0] = htole(BAR0);
- data->config.baseAddr[1] = htole(BAR1);
- data->config.baseAddr[2] = htole(BAR2);
- data->config.baseAddr[3] = htole(BAR3);
- data->config.baseAddr[4] = htole(BAR4);
- data->config.baseAddr[5] = htole(BAR5);
- data->config.cardbusCIS = htole(CardbusCIS);
- data->config.subsystemVendorID = htole(SubsystemVendorID);
- data->config.subsystemID = htole(SubsystemID);
- data->config.expansionROM = htole(ExpansionROM);
- data->config.interruptLine = htole(InterruptLine);
- data->config.interruptPin = htole(InterruptPin);
- data->config.minimumGrant = htole(MinimumGrant);
- data->config.maximumLatency = htole(MaximumLatency);
+ data->config.vendor = htole(VendorID.returnValue());
+ data->config.device = htole(DeviceID.returnValue());
+ data->config.command = htole(Command.returnValue());
+ data->config.status = htole(Status.returnValue());
+ data->config.revision = htole(Revision.returnValue());
+ data->config.progIF = htole(ProgIF.returnValue());
+ data->config.subClassCode = htole(SubClassCode.returnValue());
+ data->config.classCode = htole(ClassCode.returnValue());
+ data->config.cacheLineSize = htole(CacheLineSize.returnValue());
+ data->config.latencyTimer = htole(LatencyTimer.returnValue());
+ data->config.headerType = htole(HeaderType.returnValue());
+ data->config.bist = htole(BIST.returnValue());
+
+ data->config.baseAddr[0] = htole(BAR0.returnValue());
+ data->config.baseAddr[1] = htole(BAR1.returnValue());
+ data->config.baseAddr[2] = htole(BAR2.returnValue());
+ data->config.baseAddr[3] = htole(BAR3.returnValue());
+ data->config.baseAddr[4] = htole(BAR4.returnValue());
+ data->config.baseAddr[5] = htole(BAR5.returnValue());
+ data->config.cardbusCIS = htole(CardbusCIS.returnValue());
+ data->config.subsystemVendorID = htole(SubsystemVendorID.returnValue());
+ data->config.subsystemID = htole(SubsystemID.returnValue());
+ data->config.expansionROM = htole(ExpansionROM.returnValue());
+ data->config.interruptLine = htole(InterruptLine.returnValue());
+ data->config.interruptPin = htole(InterruptPin.returnValue());
+ data->config.minimumGrant = htole(MinimumGrant.returnValue());
+ data->config.maximumLatency = htole(MaximumLatency.returnValue());
data->BARSize[0] = BAR0Size;
data->BARSize[1] = BAR1Size;
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index b6e05627d..2f702a4bf 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -15,6 +15,12 @@ class BaseCPU(SimObject):
cpu_id = Param.Int("CPU identifier")
if build_env['FULL_SYSTEM']:
+ do_quiesce = Param.Bool(True, "enable quiesce instructions")
+ do_checkpoint_insts = Param.Bool(True,
+ "enable checkpoint pseudo instructions")
+ do_statistics_insts = Param.Bool(True,
+ "enable statistics pseudo instructions")
+
if build_env['TARGET_ISA'] == 'sparc':
dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
itb = Param.SparcITB(SparcITB(), "Instruction TLB")
diff --git a/src/sim/param.hh b/src/sim/param.hh
index 1bc55c125..2aa0456da 100644
--- a/src/sim/param.hh
+++ b/src/sim/param.hh
@@ -242,6 +242,8 @@ class Param : public BaseParam
return value;
}
+ T returnValue() const { return value; }
+
// display value to stream
virtual void showValue(std::ostream &os) const;
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 66036def1..4a8c0eb66 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -40,7 +40,6 @@
#include "cpu/thread_context.hh"
#include "cpu/quiesce_event.hh"
#include "arch/kernel_stats.hh"
-#include "sim/param.hh"
#include "sim/pseudo_inst.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
@@ -57,10 +56,6 @@ using namespace TheISA;
namespace AlphaPseudo
{
- bool doStatisticsInsts;
- bool doCheckpointInsts;
- bool doQuiesce;
-
void
arm(ThreadContext *tc)
{
@@ -71,7 +66,7 @@ namespace AlphaPseudo
void
quiesce(ThreadContext *tc)
{
- if (!doQuiesce)
+ if (!tc->getCpuPtr()->params->do_quiesce)
return;
DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name());
@@ -84,7 +79,7 @@ namespace AlphaPseudo
void
quiesceNs(ThreadContext *tc, uint64_t ns)
{
- if (!doQuiesce || ns == 0)
+ if (!tc->getCpuPtr()->params->do_quiesce || ns == 0)
return;
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
@@ -107,7 +102,7 @@ namespace AlphaPseudo
void
quiesceCycles(ThreadContext *tc, uint64_t cycles)
{
- if (!doQuiesce || cycles == 0)
+ if (!tc->getCpuPtr()->params->do_quiesce || cycles == 0)
return;
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
@@ -197,7 +192,7 @@ namespace AlphaPseudo
void
resetstats(ThreadContext *tc, Tick delay, Tick period)
{
- if (!doStatisticsInsts)
+ if (!tc->getCpuPtr()->params->do_statistics_insts)
return;
@@ -211,7 +206,7 @@ namespace AlphaPseudo
void
dumpstats(ThreadContext *tc, Tick delay, Tick period)
{
- if (!doStatisticsInsts)
+ if (!tc->getCpuPtr()->params->do_statistics_insts)
return;
@@ -252,7 +247,7 @@ namespace AlphaPseudo
void
dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
{
- if (!doStatisticsInsts)
+ if (!tc->getCpuPtr()->params->do_statistics_insts)
return;
@@ -266,7 +261,7 @@ namespace AlphaPseudo
void
m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
{
- if (!doCheckpointInsts)
+ if (!tc->getCpuPtr()->params->do_checkpoint_insts)
return;
Tick when = curTick + delay * Clock::Int::ns;
@@ -278,7 +273,7 @@ namespace AlphaPseudo
uint64_t
readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
{
- const string &file = tc->getCpuPtr()->system->params()->readfile;
+ const string &file = tc->getSystemPtr()->params()->readfile;
if (file.empty()) {
return ULL(0);
}
@@ -310,33 +305,6 @@ namespace AlphaPseudo
return result;
}
- class Context : public ParamContext
- {
- public:
- Context(const string &section) : ParamContext(section) {}
- void checkParams();
- };
-
- Context context("pseudo_inst");
-
- Param<bool> __quiesce(&context, "quiesce",
- "enable quiesce instructions",
- true);
- Param<bool> __statistics(&context, "statistics",
- "enable statistics pseudo instructions",
- true);
- Param<bool> __checkpoint(&context, "checkpoint",
- "enable checkpoint pseudo instructions",
- true);
-
- void
- Context::checkParams()
- {
- doQuiesce = __quiesce;
- doStatisticsInsts = __statistics;
- doCheckpointInsts = __checkpoint;
- }
-
void debugbreak(ThreadContext *tc)
{
debug_break();
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-29 11:20:54 +0000