diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 50 |
1 files changed, 29 insertions, 21 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 035decf9a..fdb41bf75 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2013 ARM Limited +# Copyright (c) 2012-2013, 2015 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -47,29 +47,37 @@ from Tags import * class BaseCache(MemObject): type = 'BaseCache' cxx_header = "mem/cache/base.hh" - assoc = Param.Int("associativity") - hit_latency = Param.Cycles("The hit latency for this cache") - response_latency = Param.Cycles( - "Additional cache latency for the return path to core on a miss"); + + size = Param.MemorySize("Capacity") + assoc = Param.Unsigned("Associativity") + + hit_latency = Param.Cycles("Hit latency") + response_latency = Param.Cycles("Latency for the return path on a miss"); + max_miss_count = Param.Counter(0, - "number of misses to handle before calling exit") - mshrs = Param.Int("number of MSHRs (max outstanding requests)") - demand_mshr_reserve = Param.Int(1, "mshrs to reserve for demand access") - size = Param.MemorySize("capacity in bytes") + "Number of misses to handle before calling exit") + + mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") + demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") + tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") + write_buffers = Param.Unsigned(8, "Number of write buffers") + forward_snoops = Param.Bool(True, - "forward snoops from mem side to cpu side") + "Forward snoops from mem side to cpu side") is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)") - tgts_per_mshr = Param.Int("max number of accesses per MSHR") - two_queue = Param.Bool(False, - "whether the lifo should have two queue replacement") - write_buffers = Param.Int(8, "number of write buffers") - prefetch_on_access = Param.Bool(False, - "notify the hardware prefetcher on every access (not just misses)") + prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") - cpu_side = SlavePort("Port on side closer to CPU") - mem_side = MasterPort("Port on side closer to MEM") - addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port") - system = Param.System(Parent.any, "System we belong to") + prefetch_on_access = Param.Bool(False, + "Notify the hardware prefetcher on every access (not just misses)") + + tags = Param.BaseTags(LRU(), "Tag store (replacement policy)") sequential_access = Param.Bool(False, "Whether to access tags and data sequentially") - tags = Param.BaseTags(LRU(), "Tag Store for LRU caches") + + cpu_side = SlavePort("Upstream port closer to the CPU and/or device") + mem_side = MasterPort("Downstream port closer to memory") + + addr_ranges = VectorParam.AddrRange([AllMemory], + "Address range for the CPU-side port (to allow striping)") + + system = Param.System(Parent.any, "System we belong to") |