diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/arm/table_walker.cc | 3 | ||||
-rw-r--r-- | src/arch/arm/tlb.cc | 12 | ||||
-rw-r--r-- | src/arch/arm/tlb.hh | 3 | ||||
-rw-r--r-- | src/cpu/base.cc | 21 | ||||
-rw-r--r-- | src/sim/tlb.hh | 6 |
5 files changed, 43 insertions, 2 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 98dc1760d..88f2a455f 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -92,8 +92,7 @@ TableWalker::getPort(const std::string &if_name, int idx) { if (if_name == "port") { if (port != NULL) - fatal("%s: port already connected to %s", - name(), port->getPeer()->name()); + return port; System *sys = params()->sys; Tick minb = params()->min_backoff; Tick maxb = params()->max_backoff; diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 6d6da15c8..f142e03f8 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -693,6 +693,18 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, return fault; } +Port* +TLB::getPort() +{ +#if FULL_SYSTEM + return tableWalker->getPort("port"); +#else + return NULL; +#endif +} + + + ArmISA::TLB * ArmTLBParams::create() { diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 0b8bc1046..21062ea0d 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -209,6 +209,9 @@ class TLB : public BaseTLB void regStats(); + // Get the port from the table walker and return it + virtual Port *getPort(); + // Caching misc register values here. // Writing to misc registers needs to invalidate them. // translateFunctional/translateSe/translateFs checks if they are diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 556e7ec6f..e0d29577d 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -33,6 +33,7 @@ #include <string> #include <sstream> +#include "arch/tlb.hh" #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "base/misc.hh" @@ -359,6 +360,26 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) if (DTRACE(Context)) ThreadContext::compare(oldTC, newTC); */ + + Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port; + old_itb_port = oldTC->getITBPtr()->getPort(); + old_dtb_port = oldTC->getDTBPtr()->getPort(); + new_itb_port = newTC->getITBPtr()->getPort(); + new_dtb_port = newTC->getDTBPtr()->getPort(); + + // Move over any table walker ports if they exist + if (new_itb_port && !new_itb_port->isConnected()) { + assert(old_itb_port); + Port *peer = old_itb_port->getPeer();; + new_itb_port->setPeer(peer); + peer->setPeer(new_itb_port); + } + if (new_dtb_port && !new_dtb_port->isConnected()) { + assert(old_dtb_port); + Port *peer = old_dtb_port->getPeer();; + new_dtb_port->setPeer(peer); + peer->setPeer(new_dtb_port); + } } #if FULL_SYSTEM diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh index ddd3127e5..a3e5c22c7 100644 --- a/src/sim/tlb.hh +++ b/src/sim/tlb.hh @@ -38,6 +38,7 @@ class ThreadContext; class Packet; +class Port; class BaseTLB : public SimObject { @@ -52,6 +53,11 @@ class BaseTLB : public SimObject public: virtual void demapPage(Addr vaddr, uint64_t asn) = 0; + /** Get any port that the TLB or hardware table walker needs. + * This is used for migrating port connections during a takeOverFrom() + * call. */ + virtual Port* getPort() { return NULL; } + class Translation { public: |