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-rw-r--r--src/arch/sparc/isa/decoder.isa166
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa4
-rw-r--r--src/arch/sparc/miscregfile.cc7
-rw-r--r--src/base/bigint.hh14
-rw-r--r--src/cpu/simple/atomic.cc11
-rw-r--r--src/cpu/simple/timing.cc10
6 files changed, 207 insertions, 5 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 70afe19b6..0edb959f0 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -816,6 +816,58 @@ decode OP default Unknown::unknown()
}
0x35: decode OPF{
format FpBasic{
+ 0x01: fmovs_fcc0({{
+ if(passesFpCondition(Fsr<11:10>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x02: fmovd_fcc0({{
+ if(passesFpCondition(Fsr<11:10>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x03: FpUnimpl::fmovq_fcc0();
+ 0x25: fmovrsz({{
+ if(Rs1 == 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x26: fmovrdz({{
+ if(Rs1 == 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x27: FpUnimpl::fmovrqz();
+ 0x41: fmovs_fcc1({{
+ if(passesFpCondition(Fsr<33:32>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x42: fmovd_fcc1({{
+ if(passesFpCondition(Fsr<33:32>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x43: FpUnimpl::fmovq_fcc1();
+ 0x45: fmovrslez({{
+ if(Rs1 <= 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x46: fmovrdlez({{
+ if(Rs1 <= 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x47: FpUnimpl::fmovrqlez();
0x51: fcmps({{
uint8_t fcc;
if(isnan(Frs1s) || isnan(Frs2s))
@@ -874,6 +926,110 @@ decode OP default Unknown::unknown()
Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
}});
0x57: FpUnimpl::fcmpeq();
+ 0x65: fmovrslz({{
+ if(Rs1 < 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x66: fmovrdlz({{
+ if(Rs1 < 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x67: FpUnimpl::fmovrqlz();
+ 0x81: fmovs_fcc2({{
+ if(passesFpCondition(Fsr<35:34>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x82: fmovd_fcc2({{
+ if(passesFpCondition(Fsr<35:34>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x83: FpUnimpl::fmovq_fcc2();
+ 0xA5: fmovrsnz({{
+ if(Rs1 != 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0xA6: fmovrdnz({{
+ if(Rs1 != 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0xA7: FpUnimpl::fmovrqnz();
+ 0xC1: fmovs_fcc3({{
+ if(passesFpCondition(Fsr<37:36>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0xC2: fmovd_fcc3({{
+ if(passesFpCondition(Fsr<37:36>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0xC3: FpUnimpl::fmovq_fcc3();
+ 0xC5: fmovrsgz({{
+ if(Rs1 > 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0xC6: fmovrdgz({{
+ if(Rs1 > 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0xC7: FpUnimpl::fmovrqgz();
+ 0xE5: fmovrsgez({{
+ if(Rs1 >= 0)
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0xE6: fmovrdgez({{
+ if(Rs1 >= 0)
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0xE7: FpUnimpl::fmovrqgez();
+ 0x101: fmovs_icc({{
+ if(passesCondition(Ccr<3:0>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x102: fmovd_icc({{
+ if(passesCondition(Ccr<3:0>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x103: FpUnimpl::fmovq_icc();
+ 0x181: fmovs_xcc({{
+ if(passesCondition(Ccr<7:4>, COND4))
+ Frds = Frs2s;
+ else
+ Frds = Frds;
+ }});
+ 0x182: fmovd_xcc({{
+ if(passesCondition(Ccr<7:4>, COND4))
+ Frd = Frs2;
+ else
+ Frd = Frd;
+ }});
+ 0x183: FpUnimpl::fmovq_xcc();
default: FailUnimpl::fpop2();
}
}
@@ -1164,7 +1320,10 @@ decode OP default Unknown::unknown()
0x04: stw({{Mem.uw = Rd.sw;}});
0x05: stb({{Mem.ub = Rd.sb;}});
0x06: sth({{Mem.uhw = Rd.shw;}});
- 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
+ 0x07: sttw({{
+ (Mem.tuw).a = RdLow<31:0>;
+ (Mem.tuw).b = RdHigh<31:0>;
+ }});
}
format Load {
0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
@@ -1254,7 +1413,10 @@ decode OP default Unknown::unknown()
0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
- 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
+ 0x17: sttwa({{
+ (Mem.tuw).a = RdLow<31:0>;
+ (Mem.tuw).b = RdHigh<31:0>;
+ }}, {{EXT_ASI}});
}
format LoadAlt {
0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 1d884d6c3..dfe937371 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -224,7 +224,7 @@ def template StoreExecute {{
}
if(storeCond && fault == NoFault)
{
- fault = xc->write((uint%(mem_acc_size)s_t)Mem,
+ fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
if(fault == NoFault)
@@ -257,7 +257,7 @@ def template StoreInitiateAcc {{
}
if(storeCond && fault == NoFault)
{
- fault = xc->write((uint%(mem_acc_size)s_t)Mem,
+ fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
if(fault == NoFault)
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 20bc4ae5d..ac30afde9 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -654,7 +654,12 @@ void MiscRegFile::setReg(int miscReg,
#endif
return;
case MISCREG_CWP:
- new_val = val > NWindows ? NWindows - 1 : val;
+ new_val = val >= NWindows ? NWindows - 1 : val;
+ if (val >= NWindows) {
+ new_val = NWindows - 1;
+ warn("Attempted to set the CWP to %d with NWindows = %d\n",
+ val, NWindows);
+ }
tc->changeRegFileContext(CONTEXT_CWP, new_val);
break;
case MISCREG_GL:
diff --git a/src/base/bigint.hh b/src/base/bigint.hh
index ed48c67fe..d60684231 100644
--- a/src/base/bigint.hh
+++ b/src/base/bigint.hh
@@ -28,6 +28,8 @@
* Authors: Ali Saidi
*/
+#include "base/misc.hh"
+
#include <iostream>
#ifndef __BASE_BIGINT_HH__
@@ -49,6 +51,12 @@ struct m5_twin64_t {
b = x;
return *this;
}
+
+ operator uint64_t()
+ {
+ panic("Tried to cram a twin64_t into an integer!\n");
+ return a;
+ }
};
struct m5_twin32_t {
@@ -67,6 +75,12 @@ struct m5_twin32_t {
b = x;
return *this;
}
+
+ operator uint32_t()
+ {
+ panic("Tried to cram a twin32_t into an integer!\n");
+ return a;
+ }
};
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ca4627bbf..6a14a8aa5 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -446,6 +446,17 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+template
+Fault
+AtomicSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+AtomicSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
template
Fault
AtomicSimpleCPU::write(uint64_t data, Addr addr,
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2e602648a..45da7c3eb 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -398,6 +398,16 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
Fault
+TimingSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+TimingSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
TimingSimpleCPU::write(uint64_t data, Addr addr,
unsigned flags, uint64_t *res);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 07:51:52 +0000