diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 3 | ||||
| -rw-r--r-- | src/sim/pseudo_inst.cc | 7 | ||||
| -rw-r--r-- | src/sim/pseudo_inst.hh | 1 |
3 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 3b187d625..711be0bd5 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -157,6 +157,9 @@ 0x21: m5exit({{ PseudoInst::m5exit(xc->tcBase(), Rdi); }}, IsNonSpeculative); + 0x22: m5fail({{ + PseudoInst::m5fail(xc->tcBase(), Rdi, Rsi); + }}, IsNonSpeculative); 0x30: m5initparam({{ Rax = PseudoInst::initParam(xc->tcBase()); }}, IsNonSpeculative); diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index aafa5672b..a57bdb2ce 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -219,6 +219,13 @@ m5exit(ThreadContext *tc, Tick delay) } void +m5fail(ThreadContext *tc, Tick delay, uint64_t code) +{ + Tick when = curTick() + delay * SimClock::Int::ns; + exitSimLoop("m5_fail instruction encountered", code, when); +} + +void loadsymbol(ThreadContext *tc) { if (!FullSystem) diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index 4a6493a66..efcd44a69 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -54,6 +54,7 @@ uint64_t initParam(ThreadContext *xc); uint64_t rpns(ThreadContext *tc); void wakeCPU(ThreadContext *tc, uint64_t cpuid); void m5exit(ThreadContext *tc, Tick delay); +void m5fail(ThreadContext *tc, Tick delay, uint64_t code); void resetstats(ThreadContext *tc, Tick delay, Tick period); void dumpstats(ThreadContext *tc, Tick delay, Tick period); void dumpresetstats(ThreadContext *tc, Tick delay, Tick period); |