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-rw-r--r--src/arch/alpha/interrupts.hh4
-rwxr-xr-xsrc/arch/mips/interrupts.cc6
-rwxr-xr-xsrc/arch/mips/interrupts.hh28
-rw-r--r--src/arch/sparc/interrupts.hh37
-rw-r--r--src/arch/sparc/miscregfile.cc4
-rw-r--r--src/arch/sparc/tlb.cc8
-rw-r--r--src/arch/sparc/ua2005.cc32
-rw-r--r--src/arch/x86/interrupts.cc10
-rw-r--r--src/arch/x86/interrupts.hh50
-rw-r--r--src/cpu/base.cc8
-rw-r--r--src/cpu/base.hh17
-rw-r--r--src/cpu/intr_control.cc4
-rw-r--r--src/cpu/o3/commit_impl.hh4
-rw-r--r--src/cpu/o3/cpu.cc4
-rw-r--r--src/cpu/o3/cpu.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh2
-rw-r--r--src/cpu/ozone/cpu.hh2
-rw-r--r--src/cpu/ozone/cpu_impl.hh4
-rw-r--r--src/cpu/ozone/inorder_back_end_impl.hh3
-rw-r--r--src/cpu/ozone/lw_back_end_impl.hh5
-rw-r--r--src/cpu/simple/base.cc6
-rw-r--r--src/cpu/simple/base.hh2
-rw-r--r--src/cpu/simple_thread.cc2
23 files changed, 129 insertions, 115 deletions
diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index e7a451d4d..89db134ff 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -101,7 +101,7 @@ class Interrupts : public SimObject
}
void
- clear_all()
+ clearAll()
{
DPRINTF(Interrupt, "Interrupts all cleared\n");
@@ -124,7 +124,7 @@ class Interrupts : public SimObject
}
bool
- check_interrupts(ThreadContext *tc) const
+ checkInterrupts(ThreadContext *tc) const
{
return (intstatus != 0) && !(tc->readPC() & 0x3);
}
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index e04d22631..99f96fafc 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -76,7 +76,7 @@ static inline void setCauseIP_(ThreadContext *tc, uint8_t val) {
intstatus &= ~(1 << int_num);
}
- void Interrupts::clear_all()
+ void Interrupts::clearAll()
{
DPRINTF(Interrupt, "Interrupts all cleared\n");
intstatus = 0;
@@ -189,14 +189,14 @@ void Interrupts::clear(int int_num, int index)
fatal("Must use Thread COntext when clearing MIPS Interrupts in M5");
}
-void Interrupts::clear_all(ThreadContext *tc)
+void Interrupts::clearAll(ThreadContext *tc)
{
DPRINTF(Interrupt, "Interrupts all cleared\n");
uint8_t intstatus = 0;
setCauseIP_(tc, intstatus);
}
-void Interrupts::clear_all()
+void Interrupts::clearAll()
{
fatal("Must use Thread COntext when clearing MIPS Interrupts in M5");
}
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index 99a8f6fa0..af71e4636 100755
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -57,23 +57,23 @@ class Interrupts
// for posting an interrupt. It sets a bit
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
void post(int int_num, int index);
// clear(int int_num, int index) is responsible
// for clearing an interrupt. It clear a bit
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
void clear(int int_num, int index);
- // clear_all() is responsible
+ // clearAll() is responsible
// for clearing all interrupts. It clears all bits
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
- void clear_all();
+ void clearAll();
// getInterrupt(ThreadContext * tc) checks if an interrupt
// should be returned. It ands the interrupt mask and
@@ -91,7 +91,7 @@ class Interrupts
void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
- bool check_interrupts(ThreadContext * tc) const{
+ bool checkInterrupts(ThreadContext *tc) const {
//return (intstatus != 0) && !(tc->readPC() & 0x3);
if (oncputimerintr == false){
updateIntrInfo(tc);
@@ -119,7 +119,7 @@ class Interrupts
// for posting an interrupt. It sets a bit
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
void post(int int_num, ThreadContext* tc);
void post(int int_num, int index);
@@ -128,19 +128,19 @@ class Interrupts
// for clearing an interrupt. It clear a bit
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
void clear(int int_num, ThreadContext* tc);
void clear(int int_num, int index);
- // clear_all() is responsible
+ // clearAll() is responsible
// for clearing all interrupts. It clears all bits
// in intstatus corresponding to Cause IP*. The
// MIPS register Cause is updated by updateIntrInfo
- // which is called by check_interrupts
+ // which is called by checkInterrupts
//
- void clear_all(ThreadContext* tc);
- void clear_all();
+ void clearAll(ThreadContext* tc);
+ void clearAll();
// getInterrupt(ThreadContext * tc) checks if an interrupt
// should be returned. It ands the interrupt mask and
@@ -158,7 +158,9 @@ class Interrupts
bool interruptsPending(ThreadContext *tc) const;
bool onCpuTimerInterrupt(ThreadContext *tc) const;
- bool check_interrupts(ThreadContext * tc) const{
+ bool
+ checkInterrupts(ThreadContext *tc) const
+ {
return interruptsPending(tc);
}
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index 7d1496d8e..66b3792b5 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -45,7 +45,6 @@ class Interrupts : public SimObject
{
private:
-
uint64_t interrupts[NumInterruptTypes];
uint64_t intStatus;
@@ -60,10 +59,11 @@ class Interrupts : public SimObject
Interrupts(Params * p) : SimObject(p)
{
- clear_all();
+ clearAll();
}
- int InterruptLevel(uint64_t softint)
+ int
+ InterruptLevel(uint64_t softint)
{
if (softint & 0x10000 || softint & 0x1)
return 14;
@@ -76,7 +76,8 @@ class Interrupts : public SimObject
return 0;
}
- void post(int int_num, int index)
+ void
+ post(int int_num, int index)
{
DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
assert(int_num >= 0 && int_num < NumInterruptTypes);
@@ -86,7 +87,8 @@ class Interrupts : public SimObject
intStatus |= ULL(1) << int_num;
}
- void clear(int int_num, int index)
+ void
+ clear(int int_num, int index)
{
DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
assert(int_num >= 0 && int_num < NumInterruptTypes);
@@ -97,7 +99,8 @@ class Interrupts : public SimObject
intStatus &= ~(ULL(1) << int_num);
}
- void clear_all()
+ void
+ clearAll()
{
for (int i = 0; i < NumInterruptTypes; ++i) {
interrupts[i] = 0;
@@ -105,12 +108,14 @@ class Interrupts : public SimObject
intStatus = 0;
}
- bool check_interrupts(ThreadContext * tc) const
+ bool
+ checkInterrupts(ThreadContext *tc) const
{
return intStatus;
}
- Fault getInterrupt(ThreadContext * tc)
+ Fault
+ getInterrupt(ThreadContext *tc)
{
int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
@@ -153,8 +158,8 @@ class Interrupts : public SimObject
return new DevMondo;
}
if (interrupts[IT_SOFT_INT]) {
- return new
- InterruptLevelN(InterruptLevel(interrupts[IT_SOFT_INT]));
+ int level = InterruptLevel(interrupts[IT_SOFT_INT]);
+ return new InterruptLevelN(level);
}
if (interrupts[IT_RES_ERROR]) {
@@ -165,24 +170,28 @@ class Interrupts : public SimObject
return NoFault;
}
- void updateIntrInfo(ThreadContext * tc)
+ void
+ updateIntrInfo(ThreadContext *tc)
{
}
- uint64_t get_vec(int int_num)
+ uint64_t
+ get_vec(int int_num)
{
assert(int_num >= 0 && int_num < NumInterruptTypes);
return interrupts[int_num];
}
- void serialize(std::ostream &os)
+ void
+ serialize(std::ostream &os)
{
SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
SERIALIZE_SCALAR(intStatus);
}
- void unserialize(Checkpoint *cp, const std::string &section)
+ void
+ unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
UNSERIALIZE_SCALAR(intStatus);
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index b0c5dbda9..b22ceb657 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -542,9 +542,9 @@ void MiscRegFile::setReg(int miscReg,
tl = val;
#if FULL_SYSTEM
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
- tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
+ tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
else
- tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
+ tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
#endif
return;
case MISCREG_CWP:
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 61f0985db..b6a450ffe 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1021,7 +1021,7 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
dynamic_cast<SparcISA::Interrupts *>(
tc->getCpuPtr()->getInterruptController());
temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
- tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
+ tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
pkt->set(temp);
}
break;
@@ -1268,15 +1268,15 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
SparcISA::Interrupts * interrupts =
dynamic_cast<SparcISA::Interrupts *>(
tc->getCpuPtr()->getInterruptController());
- while(interrupts->get_vec(IT_INT_VEC) & data) {
+ while (interrupts->get_vec(IT_INT_VEC) & data) {
msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
- tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
+ tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
}
}
break;
case ASI_SWVR_UDB_INTR_W:
tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
- post_interrupt(bits(data,5,0),0);
+ postInterrupt(bits(data, 5, 0), 0);
break;
default:
doMmuWriteError:
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 7b8524703..e1276b812 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -44,20 +44,20 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
// If PIL < 14, copy over the tm and sm bits
if (pil < 14 && softint & 0x10000)
- cpu->post_interrupt(IT_SOFT_INT, 16);
+ cpu->postInterrupt(IT_SOFT_INT, 16);
else
- cpu->clear_interrupt(IT_SOFT_INT, 16);
+ cpu->clearInterrupt(IT_SOFT_INT, 16);
if (pil < 14 && softint & 0x1)
- cpu->post_interrupt(IT_SOFT_INT, 0);
+ cpu->postInterrupt(IT_SOFT_INT, 0);
else
- cpu->clear_interrupt(IT_SOFT_INT, 0);
+ cpu->clearInterrupt(IT_SOFT_INT, 0);
// Copy over any of the other bits that are set
for (int bit = 15; bit > 0; --bit) {
if (1 << bit & softint && bit > pil)
- cpu->post_interrupt(IT_SOFT_INT, bit);
+ cpu->postInterrupt(IT_SOFT_INT, bit);
else
- cpu->clear_interrupt(IT_SOFT_INT, bit);
+ cpu->clearInterrupt(IT_SOFT_INT, bit);
}
}
@@ -124,9 +124,9 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
case MISCREG_HINTP:
setRegNoEffect(miscReg, val);
if (hintp)
- cpu->post_interrupt(IT_HINTP, 0);
+ cpu->postInterrupt(IT_HINTP, 0);
else
- cpu->clear_interrupt(IT_HINTP, 0);
+ cpu->clearInterrupt(IT_HINTP, 0);
break;
case MISCREG_HTBA:
@@ -138,25 +138,25 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
case MISCREG_QUEUE_CPU_MONDO_TAIL:
setRegNoEffect(miscReg, val);
if (cpu_mondo_head != cpu_mondo_tail)
- cpu->post_interrupt(IT_CPU_MONDO, 0);
+ cpu->postInterrupt(IT_CPU_MONDO, 0);
else
- cpu->clear_interrupt(IT_CPU_MONDO, 0);
+ cpu->clearInterrupt(IT_CPU_MONDO, 0);
break;
case MISCREG_QUEUE_DEV_MONDO_HEAD:
case MISCREG_QUEUE_DEV_MONDO_TAIL:
setRegNoEffect(miscReg, val);
if (dev_mondo_head != dev_mondo_tail)
- cpu->post_interrupt(IT_DEV_MONDO, 0);
+ cpu->postInterrupt(IT_DEV_MONDO, 0);
else
- cpu->clear_interrupt(IT_DEV_MONDO, 0);
+ cpu->clearInterrupt(IT_DEV_MONDO, 0);
break;
case MISCREG_QUEUE_RES_ERROR_HEAD:
case MISCREG_QUEUE_RES_ERROR_TAIL:
setRegNoEffect(miscReg, val);
if (res_error_head != res_error_tail)
- cpu->post_interrupt(IT_RES_ERROR, 0);
+ cpu->postInterrupt(IT_RES_ERROR, 0);
else
- cpu->clear_interrupt(IT_RES_ERROR, 0);
+ cpu->clearInterrupt(IT_RES_ERROR, 0);
break;
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
@@ -185,9 +185,9 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
setRegNoEffect(miscReg, val | HPSTATE::id);
#if FULL_SYSTEM
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
- cpu->post_interrupt(IT_TRAP_LEVEL_ZERO, 0);
+ cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
else
- cpu->clear_interrupt(IT_TRAP_LEVEL_ZERO, 0);
+ cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
#endif
break;
case MISCREG_HTSTATE:
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index bfb4d5b9c..a16ea5360 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -470,7 +470,7 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
}
bool
-X86ISA::Interrupts::check_interrupts(ThreadContext * tc) const
+X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
{
RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
if (pendingUnmaskableInt) {
@@ -492,9 +492,9 @@ X86ISA::Interrupts::check_interrupts(ThreadContext * tc) const
}
Fault
-X86ISA::Interrupts::getInterrupt(ThreadContext * tc)
+X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
{
- assert(check_interrupts(tc));
+ assert(checkInterrupts(tc));
// These are all probably fairly uncommon, so we'll make them easier to
// check for.
if (pendingUnmaskableInt) {
@@ -523,9 +523,9 @@ X86ISA::Interrupts::getInterrupt(ThreadContext * tc)
}
void
-X86ISA::Interrupts::updateIntrInfo(ThreadContext * tc)
+X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
{
- assert(check_interrupts(tc));
+ assert(checkInterrupts(tc));
if (pendingUnmaskableInt) {
if (pendingSmi) {
DPRINTF(LocalApic, "SMI sent to core.\n");
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index a998e2b12..8c7316217 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -70,8 +70,7 @@
class ThreadContext;
-namespace X86ISA
-{
+namespace X86ISA {
class Interrupts : public BasicPioDevice, IntDev
{
@@ -189,7 +188,8 @@ class Interrupts : public BasicPioDevice, IntDev
*/
typedef X86LocalApicParams Params;
- void setClock(Tick newClock)
+ void
+ setClock(Tick newClock)
{
clock = newClock;
}
@@ -243,7 +243,8 @@ class Interrupts : public BasicPioDevice, IntDev
uint32_t readReg(ApicRegIndex miscReg);
void setReg(ApicRegIndex reg, uint32_t val);
- void setRegNoEffect(ApicRegIndex reg, uint32_t val)
+ void
+ setRegNoEffect(ApicRegIndex reg, uint32_t val)
{
regs[reg] = val;
}
@@ -252,14 +253,14 @@ class Interrupts : public BasicPioDevice, IntDev
* Constructor.
*/
- Interrupts(Params * p) : BasicPioDevice(p), IntDev(this),
- latency(p->pio_latency), clock(0),
- apicTimerEvent(this),
- pendingSmi(false), smiVector(0),
- pendingNmi(false), nmiVector(0),
- pendingExtInt(false), extIntVector(0),
- pendingInit(false), initVector(0),
- pendingUnmaskableInt(false)
+ Interrupts(Params * p)
+ : BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
+ apicTimerEvent(this),
+ pendingSmi(false), smiVector(0),
+ pendingNmi(false), nmiVector(0),
+ pendingExtInt(false), extIntVector(0),
+ pendingInit(false), initVector(0),
+ pendingUnmaskableInt(false)
{
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
@@ -273,20 +274,22 @@ class Interrupts : public BasicPioDevice, IntDev
* Functions for retrieving interrupts for the CPU to handle.
*/
- bool check_interrupts(ThreadContext * tc) const;
- Fault getInterrupt(ThreadContext * tc);
- void updateIntrInfo(ThreadContext * tc);
+ bool checkInterrupts(ThreadContext *tc) const;
+ Fault getInterrupt(ThreadContext *tc);
+ void updateIntrInfo(ThreadContext *tc);
/*
* Serialization.
*/
- void serialize(std::ostream & os)
+ void
+ serialize(std::ostream &os)
{
panic("Interrupts::serialize unimplemented!\n");
}
- void unserialize(Checkpoint * cp, const std::string & section)
+ void
+ unserialize(Checkpoint *cp, const std::string &section)
{
panic("Interrupts::unserialize unimplemented!\n");
}
@@ -295,22 +298,25 @@ class Interrupts : public BasicPioDevice, IntDev
* Old functions needed for compatability but which will be phased out
* eventually.
*/
- void post(int int_num, int index)
+ void
+ post(int int_num, int index)
{
panic("Interrupts::post unimplemented!\n");
}
- void clear(int int_num, int index)
+ void
+ clear(int int_num, int index)
{
panic("Interrupts::clear unimplemented!\n");
}
- void clear_all()
+ void
+ clearAll()
{
- panic("Interrupts::clear_all unimplemented!\n");
+ panic("Interrupts::clearAll unimplemented!\n");
}
};
-};
+} // namespace X86ISA
#endif // __ARCH_X86_INTERRUPTS_HH__
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index def1e9920..8c461cccb 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -379,21 +379,21 @@ BaseCPU::ProfileEvent::process()
}
void
-BaseCPU::post_interrupt(int int_num, int index)
+BaseCPU::postInterrupt(int int_num, int index)
{
interrupts->post(int_num, index);
}
void
-BaseCPU::clear_interrupt(int int_num, int index)
+BaseCPU::clearInterrupt(int int_num, int index)
{
interrupts->clear(int_num, index);
}
void
-BaseCPU::clear_interrupts()
+BaseCPU::clearInterrupts()
{
- interrupts->clear_all();
+ interrupts->clearAll();
}
void
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index b0eece2a1..2d25c9e56 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -108,9 +108,7 @@ class BaseCPU : public MemObject
#if FULL_SYSTEM
protected:
-// uint64_t interrupts[TheISA::NumInterruptLevels];
-// uint64_t intstatus;
- TheISA::Interrupts * interrupts;
+ TheISA::Interrupts *interrupts;
public:
TheISA::Interrupts *
@@ -119,12 +117,15 @@ class BaseCPU : public MemObject
return interrupts;
}
- virtual void post_interrupt(int int_num, int index);
- virtual void clear_interrupt(int int_num, int index);
- virtual void clear_interrupts();
+ virtual void postInterrupt(int int_num, int index);
+ virtual void clearInterrupt(int int_num, int index);
+ virtual void clearInterrupts();
- bool check_interrupts(ThreadContext * tc) const
- { return interrupts->check_interrupts(tc); }
+ bool
+ checkInterrupts(ThreadContext *tc) const
+ {
+ return interrupts->checkInterrupts(tc);
+ }
class ProfileEvent : public Event
{
diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
index c3a11ad91..de7f9245e 100644
--- a/src/cpu/intr_control.cc
+++ b/src/cpu/intr_control.cc
@@ -50,7 +50,7 @@ IntrControl::post(int cpu_id, int int_num, int index)
DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
- cpu->post_interrupt(int_num, index);
+ cpu->postInterrupt(int_num, index);
}
void
@@ -59,7 +59,7 @@ IntrControl::clear(int cpu_id, int int_num, int index)
DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
- cpu->clear_interrupt(int_num, index);
+ cpu->clearInterrupt(int_num, index);
}
IntrControl *
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 68fc6ef3b..46c4158f6 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -665,7 +665,7 @@ DefaultCommit<Impl>::handleInterrupt()
DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
}
} else if (commitStatus[0] != TrapPending &&
- cpu->check_interrupts(cpu->tcBase(0)) &&
+ cpu->checkInterrupts(cpu->tcBase(0)) &&
!trapSquash[0] &&
!tcSquash[0]) {
// Process interrupts if interrupts are enabled, not in PAL
@@ -695,7 +695,7 @@ DefaultCommit<Impl>::commit()
// Check for any interrupt, and start processing it. Or if we
// have an outstanding interrupt and are at a point when it is
// valid to take an interrupt, process it.
- if (cpu->check_interrupts(cpu->tcBase(0))) {
+ if (cpu->checkInterrupts(cpu->tcBase(0))) {
handleInterrupt();
}
#endif // FULL_SYSTEM
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 41b7e8b14..04f344930 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -895,9 +895,9 @@ FullO3CPU<Impl>::activateWhenReady(int tid)
#if FULL_SYSTEM
template <class Impl>
void
-FullO3CPU<Impl>::post_interrupt(int int_num, int index)
+FullO3CPU<Impl>::postInterrupt(int int_num, int index)
{
- BaseCPU::post_interrupt(int_num, index);
+ BaseCPU::postInterrupt(int_num, index);
if (this->thread[0]->status() == ThreadContext::Suspended) {
DPRINTF(IPI,"Suspended Processor awoke\n");
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 406d965be..8cfc9affa 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -412,7 +412,7 @@ class FullO3CPU : public BaseO3CPU
#if FULL_SYSTEM
/** Posts an interrupt. */
- void post_interrupt(int int_num, int index);
+ void postInterrupt(int int_num, int index);
/** HW return from error interrupt. */
Fault hwrei(unsigned tid);
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index a521c3636..d8ec70bb8 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -132,7 +132,7 @@ O3ThreadContext<Impl>::suspend(int delay)
/*
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
- if (cpu->check_interrupts()) {
+ if (cpu->checkInterrupts()) {
assert(status() == ThreadContext::Active);
return;
}
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 845cbbd95..491e6ba93 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -332,7 +332,7 @@ class OzoneCPU : public BaseCPU
Status _status;
public:
- void post_interrupt(int int_num, int index);
+ void postInterrupt(int int_num, int index);
void zero_fill_64(Addr addr) {
static int warned = 0;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index c8e0dfe3d..a7efa3596 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -579,9 +579,9 @@ OzoneCPU<Impl>::dbg_vtophys(Addr addr)
#if FULL_SYSTEM
template <class Impl>
void
-OzoneCPU<Impl>::post_interrupt(int int_num, int index)
+OzoneCPU<Impl>::postInterrupt(int int_num, int index)
{
- BaseCPU::post_interrupt(int_num, index);
+ BaseCPU::postInterrupt(int_num, index);
if (_status == Idle) {
DPRINTF(IPI,"Suspended Processor awoke\n");
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index cf8634a42..798b628d6 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -149,8 +149,7 @@ InorderBackEnd<Impl>::tick()
// if (interrupt) then set thread PC, stall front end, record that
// I'm waiting for it to drain. (for now just squash)
#if FULL_SYSTEM
- if (interruptBlocked ||
- cpu->check_interrupts(tc)) {
+ if (interruptBlocked || cpu->checkInterrupts(tc)) {
if (!robEmpty()) {
interruptBlocked = true;
//AlphaDep
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index a5d79a789..60c42edd3 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -525,10 +525,7 @@ template <class Impl>
void
LWBackEnd<Impl>::checkInterrupts()
{
- if (cpu->checkInterrupts &&
- cpu->check_interrupts(tc) &&
- !trapSquash &&
- !tcSquash) {
+ if (cpu->checkInterrupts(tc) && !trapSquash && !tcSquash) {
frontEnd->interruptPending = true;
if (robEmpty() && !LSQ.hasStoresToWB()) {
// Will need to squash all instructions currently in flight and have
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d207bda14..b3379cddb 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -303,9 +303,9 @@ BaseSimpleCPU::dbg_vtophys(Addr addr)
#if FULL_SYSTEM
void
-BaseSimpleCPU::post_interrupt(int int_num, int index)
+BaseSimpleCPU::postInterrupt(int int_num, int index)
{
- BaseCPU::post_interrupt(int_num, index);
+ BaseCPU::postInterrupt(int_num, index);
if (thread->status() == ThreadContext::Suspended) {
DPRINTF(Quiesce,"Suspended Processor awoke\n");
@@ -318,7 +318,7 @@ void
BaseSimpleCPU::checkForInterrupts()
{
#if FULL_SYSTEM
- if (check_interrupts(tc)) {
+ if (checkInterrupts(tc)) {
Fault interrupt = interrupts->getInterrupt(tc);
if (interrupt != NoFault) {
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b7fcf1708..dc736c22e 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -98,7 +98,7 @@ class BaseSimpleCPU : public BaseCPU
}
public:
- void post_interrupt(int int_num, int index);
+ void postInterrupt(int int_num, int index);
void zero_fill_64(Addr addr) {
static int warned = 0;
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 42da659f2..68683e568 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -241,7 +241,7 @@ SimpleThread::suspend()
/*
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
- if (cpu->check_interrupts()) {
+ if (cpu->checkInterrupts()) {
assert(status() == ThreadContext::Active);
return;
}