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-rw-r--r--src/arch/alpha/faults.cc4
-rw-r--r--src/cpu/o3/alpha_cpu.hh4
-rw-r--r--src/cpu/o3/alpha_cpu_impl.hh16
-rw-r--r--src/cpu/o3/commit_impl.hh5
-rw-r--r--src/cpu/o3/fetch.hh2
-rw-r--r--src/cpu/o3/lsq_unit.hh2
-rw-r--r--src/mem/page_table.cc28
-rw-r--r--src/mem/page_table.hh11
-rw-r--r--src/sim/pseudo_inst.cc6
-rw-r--r--src/sim/serialize.hh3
10 files changed, 50 insertions, 31 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 06765768a..eef4361fd 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -194,11 +194,13 @@ void PageTableFault::invoke(ThreadContext *tc)
// We've accessed the next page
if (vaddr > p->stack_min - PageBytes) {
+ warn("Increasing stack %#x:%#x to %#x:%#x because of access to %#x",
+ p->stack_min, p->stack_base, p->stack_min - PageBytes,
+ p->stack_base, vaddr);
p->stack_min -= PageBytes;
if (p->stack_base - p->stack_min > 8*1024*1024)
fatal("Over max stack size for one thread\n");
p->pTable->allocate(p->stack_min, PageBytes);
- warn("Increasing stack size by one page.");
} else {
FaultBase::invoke(tc);
}
diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index 55b975142..d7f3d5801 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -384,8 +384,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
bool inPalMode(uint64_t PC)
{ return AlphaISA::PcPAL(PC); }
- /** Traps to handle given fault. */
- void trap(Fault fault, unsigned tid);
bool simPalCheck(int palFunc, unsigned tid);
/** Processes any interrupts. */
@@ -395,6 +393,8 @@ class AlphaO3CPU : public FullO3CPU<Impl>
void halt() { panic("Halt not implemented!\n"); }
#endif
+ /** Traps to handle given fault. */
+ void trap(Fault fault, unsigned tid);
#if !FULL_SYSTEM
/** Executes a syscall.
diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh
index 532611fb6..eca6fbbcb 100644
--- a/src/cpu/o3/alpha_cpu_impl.hh
+++ b/src/cpu/o3/alpha_cpu_impl.hh
@@ -755,14 +755,6 @@ AlphaO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
template <class Impl>
void
-AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid)
-{
- // Pass the thread's TC into the invoke method.
- fault->invoke(this->threadContexts[tid]);
-}
-
-template <class Impl>
-void
AlphaO3CPU<Impl>::processInterrupts()
{
// Check for interrupts here. For now can copy the code that
@@ -823,6 +815,14 @@ AlphaO3CPU<Impl>::processInterrupts()
#endif // FULL_SYSTEM
+template <class Impl>
+void
+AlphaO3CPU<Impl>::trap(Fault fault, unsigned tid)
+{
+ // Pass the thread's TC into the invoke method.
+ fault->invoke(this->threadContexts[tid]);
+}
+
#if !FULL_SYSTEM
template <class Impl>
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 176f83246..cd7dd47d4 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -991,7 +991,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
if (inst_fault != NoFault) {
head_inst->setCompleted();
-#if FULL_SYSTEM
DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
head_inst->seqNum, head_inst->readPC());
@@ -1035,10 +1034,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
generateTrapEvent(tid);
return false;
-#else // !FULL_SYSTEM
- panic("fault (%d) detected @ PC %08p", inst_fault,
- head_inst->PC);
-#endif // FULL_SYSTEM
}
updateComInstStats(head_inst);
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 790c28f09..7fcd21b7d 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -36,7 +36,7 @@
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/pc_event.hh"
-#include "mem/packet.hh"
+#include "mem/packet_impl.hh"
#include "mem/port.hh"
#include "sim/eventq.hh"
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 9b67e61f2..74b8fe5bb 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -40,7 +40,7 @@
#include "config/full_system.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
-#include "mem/packet.hh"
+#include "mem/packet_impl.hh"
#include "mem/port.hh"
/**
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 7daf31900..a34a0393a 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -54,6 +54,9 @@ PageTable::PageTable(System *_system, Addr _pageSize)
system(_system)
{
assert(isPowerOf2(pageSize));
+ pTableCache[0].vaddr = 0;
+ pTableCache[1].vaddr = 0;
+ pTableCache[2].vaddr = 0;
}
PageTable::~PageTable()
@@ -95,7 +98,7 @@ PageTable::allocate(Addr vaddr, int size)
assert(pageOffset(vaddr) == 0);
for (; size > 0; size -= pageSize, vaddr += pageSize) {
- std::map<Addr,Addr>::iterator iter = pTable.find(vaddr);
+ m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
if (iter != pTable.end()) {
// already mapped
@@ -103,6 +106,12 @@ PageTable::allocate(Addr vaddr, int size)
}
pTable[vaddr] = system->new_page();
+ pTableCache[2].paddr = pTableCache[1].paddr;
+ pTableCache[2].vaddr = pTableCache[1].vaddr;
+ pTableCache[1].paddr = pTableCache[0].paddr;
+ pTableCache[1].vaddr = pTableCache[0].vaddr;
+ pTableCache[0].paddr = pTable[vaddr];
+ pTableCache[0].vaddr = vaddr;
}
}
@@ -112,7 +121,22 @@ bool
PageTable::translate(Addr vaddr, Addr &paddr)
{
Addr page_addr = pageAlign(vaddr);
- std::map<Addr,Addr>::iterator iter = pTable.find(page_addr);
+ paddr = 0;
+
+ if (pTableCache[0].vaddr == vaddr) {
+ paddr = pTableCache[0].paddr;
+ return true;
+ }
+ if (pTableCache[1].vaddr == vaddr) {
+ paddr = pTableCache[1].paddr;
+ return true;
+ }
+ if (pTableCache[2].vaddr == vaddr) {
+ paddr = pTableCache[2].paddr;
+ return true;
+ }
+
+ m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
if (iter == pTable.end()) {
return false;
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index f7212d423..494c0ce9a 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -37,9 +37,9 @@
#define __PAGE_TABLE__
#include <string>
-#include <map>
#include "arch/isa_traits.hh"
+#include "base/hashmap.hh"
#include "base/trace.hh"
#include "mem/request.hh"
#include "mem/packet.hh"
@@ -53,7 +53,14 @@ class System;
class PageTable
{
protected:
- std::map<Addr,Addr> pTable;
+ m5::hash_map<Addr,Addr> pTable;
+
+ struct cacheElement {
+ Addr paddr;
+ Addr vaddr;
+ } ;
+
+ struct cacheElement pTableCache[3];
const Addr pageSize;
const Addr offsetMask;
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index ae52cdd41..b2854e491 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -209,12 +209,6 @@ namespace AlphaPseudo
{
if (!doCheckpointInsts)
return;
-
-
- Tick when = curTick + delay * Clock::Int::ns;
- Tick repeat = period * Clock::Int::ns;
-
- Checkpoint::setup(when, repeat);
}
uint64_t
diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index 5a820b27e..a80dc99e4 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -241,9 +241,6 @@ class Checkpoint
// Filename for base checkpoint file within directory.
static const char *baseFilename;
-
- // Set up a checkpoint creation event or series of events.
- static void setup(Tick when, Tick period = 0);
};
#endif // __SERIALIZE_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 01:48:00 +0000