diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/inorder/resources/bpred_unit.cc | 2 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/branch_predictor.cc | 27 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/fetch_seq_unit.cc | 12 |
3 files changed, 19 insertions, 22 deletions
diff --git a/src/cpu/inorder/resources/bpred_unit.cc b/src/cpu/inorder/resources/bpred_unit.cc index 310053409..9e15a4fee 100644 --- a/src/cpu/inorder/resources/bpred_unit.cc +++ b/src/cpu/inorder/resources/bpred_unit.cc @@ -273,8 +273,6 @@ BPredUnit::predict(DynInstPtr &inst, TheISA::PCState &predPC, ThreadID tid) "...predHist.size(): %i\n", tid, inst->seqNum, predHist[tid].size()); - inst->setBranchPred(pred_taken); - return pred_taken; } diff --git a/src/cpu/inorder/resources/branch_predictor.cc b/src/cpu/inorder/resources/branch_predictor.cc index dc036df64..c849ba163 100644 --- a/src/cpu/inorder/resources/branch_predictor.cc +++ b/src/cpu/inorder/resources/branch_predictor.cc @@ -84,14 +84,20 @@ BranchPredictor::execute(int slot_num) DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, " "skipping prediction \n", tid, inst->seqNum); } else { - TheISA::PCState predPC = inst->pcState(); - TheISA::advancePC(predPC, inst->staticInst); + TheISA::PCState pred_PC = inst->pcState(); + TheISA::advancePC(pred_PC, inst->staticInst); +#if ISA_HAS_DELAY_SLOT + // By default set target to NNPC (e.g. PC + 8) + // so that a not-taken branch will update + // correctly + pred_PC.advance(); +#endif if (inst->isControl()) { // If not, the pred_PC be updated to pc+8 // If predicted, the pred_PC will be updated to new target // value - bool predict_taken = branchPred.predict(inst, predPC, tid); + bool predict_taken = branchPred.predict(inst, pred_PC, tid); if (predict_taken) { DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch " @@ -103,19 +109,12 @@ BranchPredictor::execute(int slot_num) predictedNotTaken++; } - inst->setPredTarg(predPC); - inst->setBranchPred(predict_taken); - - DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is " - "%s.\n", tid, seq_num, predPC); - - } else { - inst->setPredTarg(predPC); - //DPRINTF(InOrderBPred, "[tid:%i]: Ignoring [sn:%i] " - // "because this isn't " - // "a control instruction.\n", tid, seq_num); } + + inst->setPredTarg(pred_PC); + DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is " + "%s.\n", tid, seq_num, pred_PC); } bpred_req->done(); diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc index 7fd57cc75..6ed949df3 100644 --- a/src/cpu/inorder/resources/fetch_seq_unit.cc +++ b/src/cpu/inorder/resources/fetch_seq_unit.cc @@ -68,8 +68,6 @@ FetchSeqUnit::init() void FetchSeqUnit::execute(int slot_num) { - // After this is working, change this to a reinterpret cast - // for performance considerations ResourceRequest* fs_req = reqMap[slot_num]; DynInstPtr inst = fs_req->inst; ThreadID tid = inst->readTid(); @@ -78,6 +76,9 @@ FetchSeqUnit::execute(int slot_num) fs_req->fault = NoFault; + DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid, + pc[tid]); + switch (fs_req->cmd) { case AssignNextPC: @@ -86,14 +87,13 @@ FetchSeqUnit::execute(int slot_num) inst->pcState(pc[tid]); inst->setMemAddr(pc[tid].instAddr()); - pc[tid].advance(); //XXX HACK! - inst->setPredTarg(pc[tid]); + // Advance to next PC (typically PC + 4) + pc[tid].advance(); inst->setSeqNum(cpu->getAndIncrementInstSeq(tid)); DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to " - "PC %s\n", tid, inst->seqNum, - inst->pcState()); + "PC %s\n", tid, inst->seqNum, inst->pcState()); fs_req->done(); } else { |