summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/arch/alpha/regfile.hh7
-rw-r--r--src/arch/alpha/types.hh7
-rw-r--r--src/arch/mips/regfile.cc6
-rw-r--r--src/arch/mips/regfile/regfile.hh4
-rw-r--r--src/arch/mips/types.hh3
-rw-r--r--src/arch/sparc/miscregfile.cc3
-rw-r--r--src/arch/sparc/regfile.cc15
-rw-r--r--src/arch/sparc/regfile.hh2
-rw-r--r--src/arch/sparc/types.hh8
-rw-r--r--src/arch/x86/regfile.cc5
-rw-r--r--src/arch/x86/regfile.hh2
-rw-r--r--src/arch/x86/types.hh11
-rw-r--r--src/cpu/checker/thread_context.hh6
-rwxr-xr-xsrc/cpu/o3/thread_context.hh9
-rw-r--r--src/cpu/ozone/cpu.hh3
-rw-r--r--src/cpu/simple_thread.hh6
-rw-r--r--src/cpu/thread_context.hh9
17 files changed, 0 insertions, 106 deletions
diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index d6d2f587e..e431e7570 100644
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -206,13 +206,6 @@ class RegFile {
void serialize(EventManager *em, std::ostream &os);
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section);
-
- void
- changeContext(RegContextParam param, RegContextVal val)
- {
- //This would be an alternative place to call/implement
- //the swapPALShadow function
- }
};
static inline int
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
index 94a4cb0e9..7905114b8 100644
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -57,13 +57,6 @@ union AnyReg
MiscReg ctrlreg;
};
-enum RegContextParam
-{
- CONTEXT_PALMODE
-};
-
-typedef bool RegContextVal;
-
enum annotes
{
ANNOTE_NONE = 0,
diff --git a/src/arch/mips/regfile.cc b/src/arch/mips/regfile.cc
index 0c670af6d..e05bfe2df 100644
--- a/src/arch/mips/regfile.cc
+++ b/src/arch/mips/regfile.cc
@@ -188,12 +188,6 @@ RegFile::unserialize(Checkpoint *cp, const std::string &section)
}
-
-void RegFile::changeContext(RegContextParam param, RegContextVal val)
-{
- panic("Change Context Not Implemented for MipsISA");
-}
-
static inline int flattenIntIndex(ThreadContext * tc, int reg)
{
return reg;
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 076cf45f5..ebf793396 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -104,10 +104,6 @@ namespace MipsISA
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section);
- void changeContext(RegContextParam param, RegContextVal val)
- {
- }
-
};
} // namespace MipsISA
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
index 4208cb2d8..b459d9e14 100644
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -60,9 +60,6 @@ namespace MipsISA
MiscReg ctrlreg;
} AnyReg;
- typedef int RegContextParam;
- typedef int RegContextVal;
-
//used in FP convert & round function
enum ConvertType{
SINGLE_TO_DOUBLE,
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index d66cefa7a..b0c5dbda9 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -551,11 +551,8 @@ void MiscRegFile::setReg(int miscReg,
new_val = val >= NWindows ? NWindows - 1 : val;
if (val >= NWindows)
new_val = NWindows - 1;
-
- tc->changeRegFileContext(CONTEXT_CWP, new_val);
break;
case MISCREG_GL:
- tc->changeRegFileContext(CONTEXT_GLOBALS, val);
break;
case MISCREG_PIL:
case MISCREG_SOFTINT:
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 8815b094c..f390be508 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -241,21 +241,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
UNSERIALIZE_SCALAR(nnpc);
}
-void RegFile::changeContext(RegContextParam param, RegContextVal val)
-{
- switch(param)
- {
- case CONTEXT_CWP:
- intRegFile.setCWP(val);
- break;
- case CONTEXT_GLOBALS:
- intRegFile.setGlobals(val);
- break;
- default:
- panic("Tried to set illegal context parameter in the SPARC regfile.\n");
- }
-}
-
void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index da7e022e9..dd4e1f684 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -117,8 +117,6 @@ namespace SparcISA
const std::string &section);
public:
-
- void changeContext(RegContextParam param, RegContextVal val);
};
int flattenIntIndex(ThreadContext * tc, int reg);
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index d19e2a99f..dd369cc26 100644
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -51,14 +51,6 @@ namespace SparcISA
MiscReg ctrlreg;
} AnyReg;
- enum RegContextParam
- {
- CONTEXT_CWP,
- CONTEXT_GLOBALS
- };
-
- typedef int RegContextVal;
-
typedef uint16_t RegIndex;
struct CoreSpecific {
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 78fde7474..7d01c4bb4 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -248,11 +248,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
UNSERIALIZE_SCALAR(nextRip);
}
-void RegFile::changeContext(RegContextParam param, RegContextVal val)
-{
- panic("changeContext not implemented for x86!\n");
-}
-
void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
panic("copyMiscRegs not implemented for x86!\n");
diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh
index 3c2387346..75c0290d3 100644
--- a/src/arch/x86/regfile.hh
+++ b/src/arch/x86/regfile.hh
@@ -145,8 +145,6 @@ namespace X86ISA
const std::string &section);
public:
-
- void changeContext(RegContextParam param, RegContextVal val);
};
int flattenIntIndex(ThreadContext * tc, int reg);
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 90df38d13..29420352b 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -246,17 +246,6 @@ namespace X86ISA
MiscReg ctrlReg;
} AnyReg;
- //XXX This is very hypothetical. X87 instructions would need to
- //change their "context" constantly. It's also not clear how
- //this would be handled as far as out of order execution.
- //Maybe x87 instructions are in order?
- enum RegContextParam
- {
- CONTEXT_X87_TOP
- };
-
- typedef int RegContextVal;
-
typedef uint16_t RegIndex;
struct CoreSpecific {
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 4ede74c64..75ac959db 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -294,12 +294,6 @@ class CheckerThreadContext : public ThreadContext
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- {
- actualTC->changeRegFileContext(param, val);
- checkerTC->changeRegFileContext(param, val);
- }
};
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index d92f85317..c529b002b 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -281,15 +281,6 @@ class O3ThreadContext : public ThreadContext
this->cpu->setNextNPC(val, this->thread->readTid());
}
- virtual void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- {
-#if THE_ISA != SPARC_ISA
- panic("changeRegFileContext not implemented.");
-#endif
- }
-
-
/** This function exits the thread context in the CPU and returns
* 1 if the CPU has no more active threads (meaning it's OK to exit);
* Used in syscall-emulation mode when a thread executes the 'exit'
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index aeafb603a..ee5e9e668 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -271,9 +271,6 @@ class OzoneCPU : public BaseCPU
void setFuncExeInst(Counter new_val)
{ thread->funcExeInst = new_val; }
#endif
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- { panic("Not supported on Alpha!"); }
};
// Ozone specific thread context
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 69d7b2548..d26e984a3 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -405,12 +405,6 @@ class SimpleThread : public ThreadState
process->syscall(callnum, tc);
}
#endif
-
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- {
- regs.changeContext(param, val);
- }
};
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 9dffbd8c6..2b9f41b70 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -272,9 +272,6 @@ class ThreadContext
virtual int exit() { return 1; };
#endif
- virtual void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val) = 0;
-
/** function to compare two thread contexts (for debugging) */
static void compare(ThreadContext *one, ThreadContext *two);
};
@@ -467,12 +464,6 @@ class ProxyThreadContext : public ThreadContext
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
-
- void changeRegFileContext(TheISA::RegContextParam param,
- TheISA::RegContextVal val)
- {
- actualTC->changeRegFileContext(param, val);
- }
};
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 10:10:21 +0000