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-rw-r--r--src/mem/physical.cc40
-rw-r--r--src/mem/physical.hh3
-rw-r--r--src/python/m5/objects/PhysicalMemory.py3
-rw-r--r--src/python/swig/pyobject.cc1
4 files changed, 30 insertions, 17 deletions
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 5d7d7382a..2ca3f1c83 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -52,7 +52,7 @@ using namespace std;
using namespace TheISA;
PhysicalMemory::PhysicalMemory(Params *p)
- : MemObject(p->name), pmemAddr(NULL), port(NULL), lat(p->latency), _params(p)
+ : MemObject(p->name), pmemAddr(NULL), lat(p->latency), _params(p)
{
if (params()->addrRange.size() % TheISA::PageBytes != 0)
panic("Memory Size not divisible by page size\n");
@@ -76,9 +76,10 @@ PhysicalMemory::PhysicalMemory(Params *p)
void
PhysicalMemory::init()
{
- if (!port)
- panic("PhysicalMemory not connected to anything!");
- port->sendStatusChange(Port::RangeChange);
+ for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
+ if (*pi)
+ (*pi)->sendStatusChange(Port::RangeChange);
+ }
}
PhysicalMemory::~PhysicalMemory()
@@ -335,19 +336,26 @@ PhysicalMemory::doFunctionalAccess(PacketPtr pkt)
Port *
PhysicalMemory::getPort(const std::string &if_name, int idx)
{
- if (if_name == "port" && idx == -1) {
- if (port != NULL)
- panic("PhysicalMemory::getPort: additional port requested to memory!");
- port = new MemoryPort(name() + "-port", this);
- return port;
- } else if (if_name == "functional") {
- /* special port for functional writes at startup. And for memtester */
- return new MemoryPort(name() + "-funcport", this);
- } else {
+ if (if_name != "port") {
panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
}
+
+ if (idx >= ports.size()) {
+ ports.resize(idx+1);
+ }
+
+ if (ports[idx] != NULL) {
+ panic("PhysicalMemory::getPort: port %d already assigned", idx);
+ }
+
+ MemoryPort *port =
+ new MemoryPort(csprintf("%s-port%d", name(), idx), this);
+
+ ports[idx] = port;
+ return port;
}
+
void
PhysicalMemory::recvStatusChange(Port::Status status)
{
@@ -420,7 +428,11 @@ PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt)
unsigned int
PhysicalMemory::drain(Event *de)
{
- int count = port->drain(de);
+ int count = 0;
+ for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
+ count += (*pi)->drain(de);
+ }
+
if (count)
changeState(Draining);
else
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index f7200b502..e3355d6aa 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -141,9 +141,10 @@ class PhysicalMemory : public MemObject
}
uint8_t *pmemAddr;
- MemoryPort *port;
int pagePtr;
Tick lat;
+ std::vector<MemoryPort*> ports;
+ typedef std::vector<MemoryPort*>::iterator PortIterator;
public:
Addr new_page();
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index c389e4a7f..83dbc7710 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -4,8 +4,7 @@ from MemObject import *
class PhysicalMemory(MemObject):
type = 'PhysicalMemory'
- port = Port("the access port")
- functional = Port("Functional Access Port")
+ port = VectorPort("the access port")
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file")
latency = Param.Latency('1t', "latency of an access")
diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc
index 11141fa84..2a5f2b9fb 100644
--- a/src/python/swig/pyobject.cc
+++ b/src/python/swig/pyobject.cc
@@ -62,6 +62,7 @@ lookupPort(SimObject *so, const std::string &name, int i)
/**
* Connect the described MemObject ports. Called from Python via SWIG.
+ * The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports.
*/
int
connectPorts(SimObject *o1, const std::string &name1, int i1,