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-rw-r--r--src/base/bitfield.hh3
-rw-r--r--src/base/statistics.hh20
-rw-r--r--src/dev/i8254xGBe.cc20
-rw-r--r--src/dev/io_device.cc5
-rw-r--r--src/dev/ns_gige.cc5
-rw-r--r--src/dev/sinic.cc5
-rw-r--r--src/mem/bus.cc23
-rw-r--r--src/mem/cache/cache_builder.cc6
-rw-r--r--src/python/SConscript2
-rw-r--r--src/python/m5/objects/BaseCache.py3
-rw-r--r--src/python/m5/objects/Bridge.py7
-rw-r--r--src/python/m5/objects/Device.py6
-rw-r--r--src/python/m5/params.py2
-rw-r--r--src/sim/eventq.hh17
-rw-r--r--src/sim/pseudo_inst.cc10
15 files changed, 65 insertions, 69 deletions
diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 69cce2245..518bad6b8 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -96,8 +96,9 @@ inline
T
insertBits(T val, int first, int last, B bit_val)
{
+ T t_bit_val = bit_val;
T bmask = mask(first - last + 1) << last;
- return ((bit_val << last) & bmask) | (val & ~bmask);
+ return ((t_bit_val << last) & bmask) | (val & ~bmask);
}
/**
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 761b30c2b..8d3f53d4c 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -2094,9 +2094,13 @@ class UnaryNode : public Node
return vresult;
}
- Result total() const {
- Op op;
- return op(l->total());
+ Result total() const
+ {
+ const VResult &vec = this->result();
+ Result total = 0;
+ for (int i = 0; i < size(); i++)
+ total += vec[i];
+ return total;
}
virtual size_t size() const { return l->size(); }
@@ -2149,9 +2153,13 @@ class BinaryNode : public Node
return vresult;
}
- Result total() const {
- Op op;
- return op(l->total(), r->total());
+ Result total() const
+ {
+ const VResult &vec = this->result();
+ Result total = 0;
+ for (int i = 0; i < size(); i++)
+ total += vec[i];
+ return total;
}
virtual size_t size() const {
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index e54249dee..e0272c655 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -727,12 +727,8 @@ IGbE::RxDescCache::pktComplete()
if (igbe->regs.rdtr.delay()) {
DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n",
igbe->regs.rdtr.delay() * igbe->intClock());
- if (igbe->rdtrEvent.scheduled())
- igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
- igbe->intClock());
- else
- igbe->rdtrEvent.schedule(curTick + igbe->regs.rdtr.delay() *
- igbe->intClock());
+ igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
+ igbe->intClock(),true);
}
if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
@@ -895,6 +891,7 @@ IGbE::TxDescCache::pktComplete()
pktPtr = NULL;
DPRINTF(EthernetDesc, "Partial Packet Descriptor Done\n");
+ enableSm();
return;
}
@@ -946,12 +943,8 @@ IGbE::TxDescCache::pktComplete()
DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
if (igbe->regs.tidv.idv()) {
DPRINTF(EthernetDesc, "setting tidv\n");
- if (igbe->tidvEvent.scheduled())
- igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
- igbe->intClock());
- else
- igbe->tidvEvent.schedule(curTick + igbe->regs.tidv.idv() *
- igbe->intClock());
+ igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
+ igbe->intClock(), true);
}
if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
@@ -979,6 +972,7 @@ IGbE::TxDescCache::pktComplete()
DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n");
writeback((igbe->cacheBlockSize()-1)>>4);
}
+ enableSm();
igbe->checkDrain();
}
@@ -1158,6 +1152,8 @@ IGbE::txStateMachine()
return;
}
+ DPRINTF(EthernetSM, "TXS: Nothing to do, stopping ticking\n");
+ txTick = false;
}
bool
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index 9384c4b92..d430ace72 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -111,10 +111,7 @@ DmaPort::recvTiming(PacketPtr pkt)
else if (backoffTime < device->maxBackoffDelay)
backoffTime <<= 1;
- if (backoffEvent.scheduled())
- backoffEvent.reschedule(curTick + backoffTime);
- else
- backoffEvent.schedule(curTick + backoffTime);
+ backoffEvent.reschedule(curTick + backoffTime, true);
DPRINTF(DMA, "Backoff time set to %d ticks\n", backoffTime);
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index bec1fb848..d9985f808 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -2310,10 +2310,7 @@ NSGigE::transferDone()
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
- if (txEvent.scheduled())
- txEvent.reschedule(curTick + cycles(1));
- else
- txEvent.schedule(curTick + cycles(1));
+ txEvent.reschedule(curTick + cycles(1), true);
}
bool
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index 1a72652da..420761620 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -1199,10 +1199,7 @@ Device::transferDone()
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
- if (txEvent.scheduled())
- txEvent.reschedule(curTick + cycles(1));
- else
- txEvent.schedule(curTick + cycles(1));
+ txEvent.reschedule(curTick + cycles(1), true);
}
bool
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 6682ade55..95d4e2873 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -171,8 +171,9 @@ bool
Bus::recvTiming(PacketPtr pkt)
{
Port *port;
- DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n",
- pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
+ DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s result %d\n",
+ pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString(),
+ pkt->result);
BusPort *pktPort;
if (pkt->getSrc() == defaultId)
@@ -272,20 +273,14 @@ Bus::recvRetry(int id)
retryList.pop_front();
inRetry = false;
- if (id != -1) {
- //Bring tickNextIdle up to the present
- while (tickNextIdle < curTick)
- tickNextIdle += clock;
-
- //Burn a cycle for the missed grant.
+ //Bring tickNextIdle up to the present
+ while (tickNextIdle < curTick)
tickNextIdle += clock;
- if (!busIdle.scheduled()) {
- busIdle.schedule(tickNextIdle);
- } else {
- busIdle.reschedule(tickNextIdle);
- }
- } // id != -1
+ //Burn a cycle for the missed grant.
+ tickNextIdle += clock;
+
+ busIdle.reschedule(tickNextIdle, true);
}
}
//If we weren't able to drain before, we might be able to now.
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 318b57d50..e887f711e 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -134,7 +134,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
Param<bool> prefetch_cache_check_push;
Param<bool> prefetch_use_cpu_id;
Param<bool> prefetch_data_accesses_only;
- Param<int> hit_latency;
END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
@@ -190,8 +189,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
- INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false),
- INIT_PARAM_DFLT(hit_latency, "Hit Latecny for a succesful access", 1)
+ INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
END_INIT_SIM_OBJECT_PARAMS(BaseCache)
@@ -211,7 +209,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
BUILD_NULL_PREFETCHER(TAGS); \
} \
Cache<TAGS, c>::Params params(tags, mq, coh, base_params, \
- pf, prefetch_access, hit_latency, \
+ pf, prefetch_access, latency, \
true, \
store_compressed, \
adaptive_compression, \
diff --git a/src/python/SConscript b/src/python/SConscript
index 3c5ab4da1..562278aa0 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -81,7 +81,6 @@ SimObject('m5/objects/Ethernet.py')
SimObject('m5/objects/FUPool.py')
SimObject('m5/objects/FastCPU.py')
#SimObject('m5/objects/FreebsdSystem.py')
-SimObject('m5/objects/FullCPU.py')
SimObject('m5/objects/FuncUnit.py')
SimObject('m5/objects/FuncUnitConfig.py')
SimObject('m5/objects/FunctionalMemory.py')
@@ -97,7 +96,6 @@ SimObject('m5/objects/O3CPU.py')
SimObject('m5/objects/OzoneCPU.py')
SimObject('m5/objects/Pci.py')
SimObject('m5/objects/PhysicalMemory.py')
-SimObject('m5/objects/PipeTrace.py')
SimObject('m5/objects/Platform.py')
SimObject('m5/objects/Process.py')
SimObject('m5/objects/Repl.py')
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index 773a11bea..7df5215e4 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -9,7 +9,7 @@ class BaseCache(MemObject):
"Use an adaptive compression scheme")
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
- latency = Param.Int("Latency")
+ latency = Param.Latency("Latency")
compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
compression_latency = Param.Latency('0ns',
@@ -59,6 +59,5 @@ class BaseCache(MemObject):
"Use the CPU ID to seperate calculations of prefetches")
prefetch_data_accesses_only = Param.Bool(False,
"Only prefetch on data not on instruction accesses")
- hit_latency = Param.Int(1,"Hit Latency of the cache")
cpu_side = Port("Port on side closer to CPU")
mem_side = Port("Port on side closer to MEM")
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
index e123c2891..33b24ad3c 100644
--- a/src/python/m5/objects/Bridge.py
+++ b/src/python/m5/objects/Bridge.py
@@ -5,9 +5,12 @@ class Bridge(MemObject):
type = 'Bridge'
side_a = Port('Side A port')
side_b = Port('Side B port')
- queue_size_a = Param.Int(16, "The number of requests to buffer")
- queue_size_b = Param.Int(16, "The number of requests to buffer")
+ req_size_a = Param.Int(16, "The number of requests to buffer")
+ req_size_b = Param.Int(16, "The number of requests to buffer")
+ resp_size_a = Param.Int(16, "The number of requests to buffer")
+ resp_size_b = Param.Int(16, "The number of requests to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")
+ nack_delay = Param.Latency('0ns', "The latency of this bridge")
write_ack = Param.Bool(False, "Should this bridge ack writes")
fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
index f4b873a60..90fbfb552 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/python/m5/objects/Device.py
@@ -19,6 +19,12 @@ class DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True
dma = Port(Self.pio.peerObj.port, "DMA port")
+ min_backoff_delay = Param.Latency('4ns',
+ "min time between a nack packet being received and the next request made by the device")
+ max_backoff_delay = Param.Latency('10us',
+ "max time between a nack packet being received and the next request made by the device")
+
+
class IsaFake(BasicPioDevice):
type = 'IsaFake'
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index da7ddd65e..88b162874 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -348,7 +348,7 @@ class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True
class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100
class Float(ParamValue, float):
- pass
+ cxx_type = 'double'
class MemorySize(CheckedInt):
cxx_type = 'uint64_t'
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index a57e9077e..974313968 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -210,7 +210,8 @@ class Event : public Serializable, public FastAlloc
void schedule(Tick t);
/// Reschedule the event with the current priority
- void reschedule(Tick t);
+ // always parameter means to schedule if not already scheduled
+ void reschedule(Tick t, bool always = false);
/// Remove the event from the current schedule
void deschedule();
@@ -402,16 +403,22 @@ Event::deschedule()
}
inline void
-Event::reschedule(Tick t)
+Event::reschedule(Tick t, bool always)
{
- assert(scheduled());
- clearFlags(Squashed);
+ assert(scheduled() || always);
#if TRACING_ON
when_scheduled = curTick;
#endif
_when = t;
- queue->reschedule(this);
+
+ if (scheduled()) {
+ clearFlags(Squashed);
+ queue->reschedule(this);
+ } else {
+ setFlags(Scheduled);
+ queue->schedule(this);
+ }
}
inline void
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 56a779674..10127aa5f 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -87,10 +87,7 @@ namespace PseudoInst
Tick resume = curTick + Clock::Int::ns * ns;
- if (quiesceEvent->scheduled())
- quiesceEvent->reschedule(resume);
- else
- quiesceEvent->schedule(resume);
+ quiesceEvent->reschedule(resume, true);
DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
tc->getCpuPtr()->name(), ns, resume);
@@ -110,10 +107,7 @@ namespace PseudoInst
Tick resume = curTick + tc->getCpuPtr()->cycles(cycles);
- if (quiesceEvent->scheduled())
- quiesceEvent->reschedule(resume);
- else
- quiesceEvent->schedule(resume);
+ quiesceEvent->reschedule(resume, true);
DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
tc->getCpuPtr()->name(), cycles, resume);
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-30 20:07:50 +0000