diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/micro_asm.py | 9 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/data_transfer/stack_operations.py | 1 | ||||
| -rw-r--r-- | src/arch/x86/isa/macroop.isa | 19 | ||||
| -rw-r--r-- | src/arch/x86/isa/specialize.isa | 2 | ||||
| -rw-r--r-- | src/arch/x86/predecoder.cc | 1 | ||||
| -rw-r--r-- | src/arch/x86/predecoder.hh | 5 | ||||
| -rw-r--r-- | src/arch/x86/types.hh | 23 | ||||
| -rw-r--r-- | src/arch/x86/utility.hh | 2 | ||||
| -rw-r--r-- | src/base/fenv.c | 2 |
9 files changed, 51 insertions, 13 deletions
diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py index 307c9118b..a8a63e1f8 100644 --- a/src/arch/micro_asm.py +++ b/src/arch/micro_asm.py @@ -232,8 +232,15 @@ def t_ANY_ID(t): # Parameters are a string of text which don't contain an unescaped statement # statement terminator, ie a newline or semi colon. def t_params_PARAMS(t): - r'([^\n;]|((?<=\\)[\n;]))+' + r'([^\n;\\]|(\\[\n;\\]))+' t.lineno += t.value.count('\n') + unescapeParamsRE = re.compile(r'(\\[\n;\\])') + def unescapeParams(mo): + val = mo.group(0) + print "About to sub %s for %s" % (val[1], val) + return val[1] + print "Looking for matches in %s" % t.value + t.value = unescapeParamsRE.sub(unescapeParams, t.value) t.lexer.begin('asm') return t diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py index 3223d9b0f..fff0f749f 100644 --- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py @@ -55,6 +55,7 @@ microcode = ''' def macroop POP { + .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" # There needs to be a load here to actually "pop" the data addi "INTREG_RSP", "INTREG_RSP", "env.dataSize" }; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index bc7fc8015..2d928d7c9 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -132,10 +132,11 @@ def template MacroConstructor {{ inline X86Macroop::%(class_name)s::%(class_name)s(ExtMachInst machInst, EmulEnv env) : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s) { - %(constructor)s; - //alloc_microops is the code that sets up the microops - //array in the parent class. - %(alloc_microops)s; + %(adjust_env)s; + %(constructor)s; + //alloc_microops is the code that sets up the microops + //array in the parent class. + %(alloc_microops)s; } }}; @@ -147,11 +148,15 @@ def template MacroConstructor {{ let {{ from micro_asm import Combinational_Macroop, Rom_Macroop class X86Macroop(Combinational_Macroop): + def setAdjustEnv(self, val): + self.adjust_env = val def __init__(self, name): super(X86Macroop, self).__init__(name) self.directives = { + "adjust_env" : self.setAdjustEnv } self.declared = False + self.adjust_env = "" def getAllocator(self, env): return "new X86Macroop::%s(machInst, %s)" % (self.name, env.getAllocator()) def getDeclaration(self): @@ -174,7 +179,8 @@ let {{ micropc += 1 iop = InstObjParams(self.name, self.name, "Macroop", {"code" : "", "num_microops" : numMicroops, - "alloc_microops" : allocMicroops}) + "alloc_microops" : allocMicroops, + "adjust_env" : self.adjust_env}) return MacroConstructor.subst(iop); }}; @@ -218,13 +224,10 @@ let {{ %(dataSize)s)''' % \ self.__dict__ def addReg(self, reg): - print "Adding reg \"%s\"" % reg if not self.regUsed: - print "Added as reg" self.reg = reg self.regUsed = True elif not self.regmUsed: - print "Added as regm" self.regm = reg self.regmUsed = True else: diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index 37f523efc..96add3ab5 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -101,7 +101,7 @@ let {{ # This function specializes the given piece of code to use a particular # set of argument types described by "opTypes". def specializeInst(Name, opTypes, env): - print "Specializing %s with opTypes %s" % (Name, opTypes) + # print "Specializing %s with opTypes %s" % (Name, opTypes) while len(opTypes): # Parse the operand type string we're working with opType = OpType(opTypes[0]) diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc index 5c98a1831..72b60385b 100644 --- a/src/arch/x86/predecoder.cc +++ b/src/arch/x86/predecoder.cc @@ -77,6 +77,7 @@ namespace X86ISA emi.modRM = 0; emi.sib = 0; + emi.mode = 0; } void Predecoder::process() diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index 0708875c1..3c858f061 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -176,7 +176,10 @@ namespace X86ISA tc(_tc), basePC(0), origPC(0), offset(0), outOfBytes(true), emiIsReady(false), state(ResetState) - {} + { + emi.mode.mode = LongMode; + emi.mode.submode = SixtyFourBitMode; + } ThreadContext * getTC() { diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 225258358..fc9f1d82b 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -120,6 +120,24 @@ namespace X86ISA Bitfield<2,0> bottom3; EndBitUnion(Opcode) + BitUnion8(OperatingMode) + Bitfield<3> mode; + Bitfield<2,0> submode; + EndBitUnion(OperatingMode) + + enum X86Mode { + LongMode, + LegacyMode + }; + + enum X86SubMode { + SixtyFourBitMode, + CompatabilityMode, + ProtectedMode, + Virtual8086Mode, + RealMode + }; + //The intermediate structure the x86 predecoder returns. struct ExtMachInst { @@ -151,6 +169,9 @@ namespace X86ISA uint8_t opSize; //The effective address size. uint8_t addrSize; + + //Mode information + OperatingMode mode; }; inline static std::ostream & @@ -172,6 +193,8 @@ namespace X86ISA inline static bool operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) { + if(emi1.mode != emi2.mode) + return false; if(emi1.legacy != emi2.legacy) return false; if(emi1.rex != emi2.rex) diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 1c98e7fbc..ed401a519 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -79,7 +79,7 @@ namespace __hash_namespace { ((uint64_t)emi.opcode.prefixB << 8) | ((uint64_t)emi.opcode.op)) ^ emi.immediate ^ emi.displacement ^ - emi.opSize; + emi.mode ^ emi.opSize; }; }; } diff --git a/src/base/fenv.c b/src/base/fenv.c index 269913a60..2ec2f796f 100644 --- a/src/base/fenv.c +++ b/src/base/fenv.c @@ -39,7 +39,7 @@ static const int m5_round_ops[] = {FE_DOWNWARD, FE_TONEAREST, FE_TOWARDZERO, FE void m5_fesetround(int rm) { - assert(rm > 0 && rm < 4); + assert(rm >= 0 && rm < 4); fesetround(m5_round_ops[rm]); } |