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-rw-r--r--src/cpu/simple/timing.cc1
-rw-r--r--src/cpu/simple/timing.hh7
2 files changed, 5 insertions, 3 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 87a5245b2..075d05d81 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -109,7 +109,6 @@ TimingSimpleCPU::drain(DrainManager *drain_manager)
if (_status == Idle ||
(_status == BaseSimpleCPU::Running && isDrained())) {
- assert(!fetchEvent.scheduled());
DPRINTF(Drain, "No need to drain.\n");
return 0;
} else {
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index cab2057ea..52807ba08 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -320,11 +320,14 @@ class TimingSimpleCPU : public BaseSimpleCPU
* of a gem5 microcode sequence.
*
* <li>Stay at PC is true.
+ *
+ * <li>A fetch event is scheduled. Normally this would never be the
+ case with microPC() == 0, but right after a context is
+ activated it can happen.
* </ul>
*/
bool isDrained() {
- return microPC() == 0 &&
- !stayAtPC;
+ return microPC() == 0 && !stayAtPC && !fetchEvent.scheduled();
}
/**