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-rw-r--r--src/mem/RubyMemory.py1
-rw-r--r--src/mem/rubymem.cc10
-rw-r--r--src/mem/rubymem.hh1
3 files changed, 8 insertions, 4 deletions
diff --git a/src/mem/RubyMemory.py b/src/mem/RubyMemory.py
index ddd97572c..2ad794a3f 100644
--- a/src/mem/RubyMemory.py
+++ b/src/mem/RubyMemory.py
@@ -45,3 +45,4 @@ class RubyMemory(PhysicalMemory):
num_dmas = Param.Int(0, "Number of DMA ports connected to the Ruby memory")
dma_port = VectorPort("Ruby_dma_ports")
pio_port = Port("Ruby_pio_port")
+ ports_per_core = Param.Int(2, "Number of per core. Typical two: icache + dcache")
diff --git a/src/mem/rubymem.cc b/src/mem/rubymem.cc
index aecc0af32..9a1a7927d 100644
--- a/src/mem/rubymem.cc
+++ b/src/mem/rubymem.cc
@@ -58,6 +58,8 @@ RubyMemory::RubyMemory(const Params *p)
ruby_clock = p->clock;
ruby_phase = p->phase;
+ ports_per_cpu = p->ports_per_core;
+
DPRINTF(Ruby, "creating Ruby Memory from file %s\n",
p->config_file.c_str());
@@ -230,14 +232,14 @@ RubyMemory::getPort(const std::string &if_name, int idx)
//
// Currently this code assumes that each cpu has both a
- // icache and dcache port and therefore divides by two. This will be
- // fixed once we unify the configuration systems and Ruby sequencers
+ // icache and dcache port and therefore divides by ports per cpu. This will
+ // be fixed once we unify the configuration systems and Ruby sequencers
// directly support M5 ports.
//
- assert(idx/2 < ruby_ports.size());
+ assert(idx/ports_per_cpu < ruby_ports.size());
Port *port = new Port(csprintf("%s-port%d", name(), idx),
this,
- ruby_ports[idx/2]);
+ ruby_ports[idx/ports_per_cpu]);
ports[idx] = port;
return port;
diff --git a/src/mem/rubymem.hh b/src/mem/rubymem.hh
index dd0a492f5..2672dcb77 100644
--- a/src/mem/rubymem.hh
+++ b/src/mem/rubymem.hh
@@ -130,6 +130,7 @@ class RubyMemory : public PhysicalMemory
Tick ruby_clock;
Tick ruby_phase;
RubyExitCallback* rubyExitCB;
+ int ports_per_cpu;
public:
static std::map<int64_t, PacketPtr> pending_requests;