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-rw-r--r--src/arch/sparc/floatregfile.cc4
-rw-r--r--src/cpu/exetrace.cc19
-rw-r--r--src/dev/sparc/dtod.cc27
-rw-r--r--src/dev/sparc/dtod.hh15
4 files changed, 54 insertions, 11 deletions
diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc
index 1bb78c67b..6f04ca829 100644
--- a/src/arch/sparc/floatregfile.cc
+++ b/src/arch/sparc/floatregfile.cc
@@ -137,10 +137,12 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
case SingleWidth:
result32 = gtoh((uint32_t)val);
memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
+ DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32);
break;
case DoubleWidth:
result64 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
+ DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64);
break;
case QuadWidth:
panic("Quad width FP not implemented.");
@@ -163,10 +165,12 @@ Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
case SingleWidth:
result32 = gtoh((uint32_t)val);
memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
+ DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result32);
break;
case DoubleWidth:
result64 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
+ DPRINTF(Sparc, "Write FP64 bits register %d = 0x%x\n", floatReg, result64);
break;
case QuadWidth:
panic("Quad width FP not implemented.");
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index bfd701271..85b08ee32 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -358,13 +358,14 @@ Trace::InstRecord::dump(ostream &outs)
(SparcISA::MachInst)staticInst->machInst) {
diffInst = true;
}
- for (int i = 0; i < TheISA::NumIntArchRegs; i++) {
+ // assume we have %g0 working correctly
+ for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
if (thread->readIntReg(i) != shared_data->intregs[i]) {
diffIntRegs = true;
}
}
for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
- if (thread->readFloatRegBits(i,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
+ if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
diffFpRegs = true;
}
}
@@ -428,15 +429,15 @@ Trace::InstRecord::dump(ostream &outs)
//if(shared_data->canrestore !=
// thread->readMiscReg(MISCREG_CANRESTORE))
if(shared_data->canrestore !=
- thread->readMiscReg(NumIntArchRegs + 4))
+ thread->readIntReg(NumIntArchRegs + 4))
diffCanrestore = true;
//if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
if(shared_data->otherwin !=
- thread->readIntReg(NumIntArchRegs + 5))
+ thread->readIntReg(NumIntArchRegs + 6))
diffOtherwin = true;
//if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
if(shared_data->cleanwin !=
- thread->readMiscReg(NumIntArchRegs + 6))
+ thread->readIntReg(NumIntArchRegs + 5))
diffCleanwin = true;
for (int i = 0; i < 64; i++) {
@@ -553,11 +554,11 @@ Trace::InstRecord::dump(ostream &outs)
shared_data->pstate);
printRegPair(outs, "Y",
//thread->readMiscReg(MISCREG_Y),
- thread->readMiscReg(NumIntArchRegs + 1),
+ thread->readIntReg(NumIntArchRegs + 1),
shared_data->y);
printRegPair(outs, "Ccr",
//thread->readMiscReg(MISCREG_CCR),
- thread->readMiscReg(NumIntArchRegs + 2),
+ thread->readIntReg(NumIntArchRegs + 2),
shared_data->ccr);
printRegPair(outs, "Tl",
thread->readMiscReg(MISCREG_TL),
@@ -584,11 +585,11 @@ Trace::InstRecord::dump(ostream &outs)
shared_data->canrestore);
printRegPair(outs, "Otherwin",
//thread->readMiscReg(MISCREG_OTHERWIN),
- thread->readIntReg(NumIntArchRegs + 5),
+ thread->readIntReg(NumIntArchRegs + 6),
shared_data->otherwin);
printRegPair(outs, "Cleanwin",
//thread->readMiscReg(MISCREG_CLEANWIN),
- thread->readIntReg(NumIntArchRegs + 6),
+ thread->readIntReg(NumIntArchRegs + 5),
shared_data->cleanwin);
outs << endl;
for (int i = 1; i <= MaxTL; i++) {
diff --git a/src/dev/sparc/dtod.cc b/src/dev/sparc/dtod.cc
index 50e158c12..42275c60a 100644
--- a/src/dev/sparc/dtod.cc
+++ b/src/dev/sparc/dtod.cc
@@ -51,11 +51,21 @@ using namespace TheISA;
DumbTOD::DumbTOD(Params *p)
: BasicPioDevice(p)
{
+ struct tm tm;
+ char *tz;
+
pioSize = 0x08;
- struct tm tm;
parseTime(p->init_time, &tm);
- todTime = timegm(&tm);
+ tz = getenv("TZ");
+ setenv("TZ", "", 1);
+ tzset();
+ todTime = mktime(&tm);
+ if (tz)
+ setenv("TZ", tz, 1);
+ else
+ unsetenv("TZ");
+ tzset();
DPRINTFN("Real-time clock set to %s\n", asctime(&tm));
DPRINTFN("Real-time clock set to %d\n", todTime);
@@ -82,6 +92,19 @@ DumbTOD::write(PacketPtr pkt)
panic("Dumb tod device doesn't support writes\n");
}
+void
+DumbTOD::serialize(std::ostream &os)
+{
+ SERIALIZE_SCALAR(todTime);
+}
+
+void
+DumbTOD::unserialize(Checkpoint *cp, const std::string &section)
+{
+ UNSERIALIZE_SCALAR(todTime);
+}
+
+
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
Param<Addr> pio_addr;
diff --git a/src/dev/sparc/dtod.hh b/src/dev/sparc/dtod.hh
index 26d4ecc08..ddf9fcc96 100644
--- a/src/dev/sparc/dtod.hh
+++ b/src/dev/sparc/dtod.hh
@@ -64,6 +64,21 @@ class DumbTOD : public BasicPioDevice
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
+
+ /**
+ * Serialize this object to the given output stream.
+ * @param os The stream to serialize to.
+ */
+ virtual void serialize(std::ostream &os);
+
+ /**
+ * Reconstruct the state of this object from a checkpoint.
+ * @param cp The checkpoint use.
+ * @param section The section name of this object
+ */
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+
};
#endif // __DEV_BADDEV_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 07:57:50 +0000