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-rw-r--r--src/mem/cache/base_cache.cc2
-rw-r--r--src/mem/cache/base_cache.hh26
-rw-r--r--src/mem/cache/cache.hh8
-rw-r--r--src/mem/cache/cache_builder.cc4
-rw-r--r--src/mem/cache/cache_impl.hh3
-rw-r--r--src/mem/cache/miss/blocking_buffer.cc3
-rw-r--r--src/mem/cache/miss/miss_queue.cc3
-rw-r--r--src/mem/cache/miss/mshr.cc3
-rw-r--r--src/mem/cache/prefetch/base_prefetcher.cc3
-rw-r--r--src/mem/cache/tags/iic.cc7
-rw-r--r--src/mem/cache/tags/lru.cc3
11 files changed, 39 insertions, 26 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 89e23ce31..c1ed6d3d4 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -99,7 +99,7 @@ BaseCache::CachePort::clearBlocked()
}
Port*
-BaseCache::getPort(const std::string &if_name)
+BaseCache::getPort(const std::string &if_name, int idx)
{
if(if_name == "cpu_side")
{
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 977e0ae29..2754fab5a 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -41,6 +41,7 @@
#include <list>
#include <inttypes.h>
+#include "base/misc.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "mem/mem_object.hh"
@@ -122,14 +123,29 @@ class BaseCache : public MemObject
CachePort *memSidePort;
public:
- virtual Port *getPort(const std::string &if_name);
+ virtual Port *getPort(const std::string &if_name, int idx = -1);
private:
//To be defined in cache_impl.hh not in base class
- virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide);
- virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
- virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
- virtual void recvStatusChange(Port::Status status, bool isCpuSide);
+ virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
+ {
+ fatal("No implementation");
+ }
+
+ virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide)
+ {
+ fatal("No implementation");
+ }
+
+ virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide)
+ {
+ fatal("No implementation");
+ }
+
+ virtual void recvStatusChange(Port::Status status, bool isCpuSide)
+ {
+ fatal("No implementation");
+ }
/**
* Bit vector of the blocking reasons for the access path.
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index d2af1d8bf..788715e76 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -146,16 +146,16 @@ class Cache : public BaseCache
/** Instantiates a basic cache object. */
Cache(const std::string &_name, Params &params);
- bool doTimingAccess(Packet *pkt, CachePort *cachePort,
+ virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
bool isCpuSide);
- Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
+ virtual Tick doAtomicAccess(Packet *pkt, CachePort *cachePort,
bool isCpuSide);
- void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
+ virtual void doFunctionalAccess(Packet *pkt, CachePort *cachePort,
bool isCpuSide);
- void recvStatusChange(Port::Status status, bool isCpuSide);
+ virtual void recvStatusChange(Port::Status status, bool isCpuSide);
void regStats();
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 8758dc57a..05a149a1c 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -230,7 +230,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
do_copy, base_params, \
/*in_bus, out_bus,*/ pf, \
- prefetch_access); \
+ prefetch_access, hit_latency); \
Cache<CacheTags<t, comp>, b, c> *retval = \
new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
params); \
@@ -242,7 +242,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
out_bus->rangeChange(); \
return retval; \
-*/return true; \
+*/return retval; \
} while (0)
#define BUILD_CACHE_PANIC(x) do { \
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index dbf2e49f1..f1e9c3698 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -588,8 +588,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
- uint8_t* temp_data = new uint8_t[blkSize];
- busPkt->dataDynamicArray<uint8_t>(temp_data);
+ busPkt->allocate();
busPkt->time = curTick;
diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index d745cb8c6..10d53b109 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -210,8 +210,7 @@ BlockingBuffer::doWriteback(Addr addr, int asid,
// Generate request
Request * req = new Request(addr, size, 0);
Packet * pkt = new Packet(req, Packet::Writeback, -1);
- uint8_t *new_data = new uint8_t[size];
- pkt->dataDynamicArray<uint8_t>(new_data);
+ pkt->allocate();
if (data) {
memcpy(pkt->getPtr<uint8_t>(), data, size);
}
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 34290351d..99ebab017 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -714,8 +714,7 @@ MissQueue::doWriteback(Addr addr, int asid,
// Generate request
Request * req = new Request(addr, size, 0);
Packet * pkt = new Packet(req, Packet::Writeback, -1);
- uint8_t *new_data = new uint8_t[size];
- pkt->dataDynamicArray<uint8_t>(new_data);
+ pkt->allocate();
if (data) {
memcpy(pkt->getPtr<uint8_t>(), data, size);
}
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index fe8cbeea4..05a2fe1c5 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -90,8 +90,7 @@ MSHR::allocateAsBuffer(Packet * &target)
asid = target->req->getAsid();
threadNum = target->req->getThreadNum();
pkt = new Packet(target->req, target->cmd, -1);
- uint8_t *new_data = new uint8_t[target->getSize()];
- pkt->dataDynamicArray<uint8_t>(new_data);
+ pkt->allocate();
pkt->senderState = (Packet::SenderState*)this;
pkt->time = curTick;
}
diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base_prefetcher.cc
index 29da53746..897551989 100644
--- a/src/mem/cache/prefetch/base_prefetcher.cc
+++ b/src/mem/cache/prefetch/base_prefetcher.cc
@@ -181,8 +181,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
Request * prefetchReq = new Request(*addr, blkSize, 0);
Packet * prefetch;
prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1);
- uint8_t *new_data = new uint8_t[blkSize];
- prefetch->dataDynamicArray<uint8_t>(new_data);
+ prefetch->allocate();
prefetch->req->setThreadContext(pkt->req->getCpuNum(),
pkt->req->getThreadNum());
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 0071ca283..847fabc88 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -430,10 +430,11 @@ IIC::freeReplacementBlock(PacketList & writebacks)
tag_ptr->data,
tag_ptr->size);
*/
- Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
+ Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
blkSize, 0);
- Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
- writeback->dataDynamic<uint8_t>(tag_ptr->data);
+ Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
+ writeback->allocate();
+ memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize);
writebacks.push_back(writeback);
}
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 81b84e11e..b7259bd3a 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -280,7 +280,8 @@ LRU::doCopy(Addr source, Addr dest, int asid, PacketList &writebacks)
dest_blk->set),
blkSize, 0);
Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
- writeback->dataDynamic<uint8_t>(dest_blk->data);
+ writeback->allocate();
+ memcpy(writeback->getPtr<uint8_t>(),dest_blk->data, blkSize);
writebacks.push_back(writeback);
}
dest_blk->tag = extractTag(dest);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 16:16:53 +0000