3 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 270940df2..115cf7fa7 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -806,6 +806,9 @@ decode OPCODE default Unknown::unknown() {
             0x04: quiesceTime({{
                 R0 = PseudoInst::quiesceTime(xc->tcBase());
             }}, IsNonSpeculative, IsUnverifiable);
+            0x07: rpns({{
+                R0 = PseudoInst::rpns(xc->tcBase());
+            }}, IsNonSpeculative, IsUnverifiable);
             0x10: deprecated_ivlb({{
                 warn_once("Obsolete M5 ivlb instruction encountered.\n");
             }});
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 409a6e009..e43279376 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -125,6 +125,12 @@ quiesceTime(ThreadContext *tc)
     return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns;
 }
 
+uint64_t
+rpns(ThreadContext *tc)
+{
+    return curTick / Clock::Int::ns;
+}
+
 void
 m5exit(ThreadContext *tc, Tick delay)
 {
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index 40702fced..80f58f80d 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -47,6 +47,7 @@ void quiesce(ThreadContext *tc);
 void quiesceNs(ThreadContext *tc, uint64_t ns);
 void quiesceCycles(ThreadContext *tc, uint64_t cycles);
 uint64_t quiesceTime(ThreadContext *tc);
+uint64_t rpns(ThreadContext *tc);
 void m5exit(ThreadContext *tc, Tick delay);
 void loadsymbol(ThreadContext *xc);
 void resetstats(ThreadContext *tc, Tick delay, Tick period);