diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/sim/System.py | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/sim/System.py b/src/sim/System.py index 031331375..2cc171881 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -43,12 +43,6 @@ class System(MemObject): cxx_header = "sim/system.hh" system_port = MasterPort("System port") - # Override the clock from the ClockedObject which looks at the - # parent clock by default. The 1 GHz default system clock serves - # as a start for the modules that rely on the parent to provide - # the clock. - clock = '1GHz' - @classmethod def export_method_cxx_predecls(cls, code): code('#include "sim/system.hh"') |