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-rw-r--r--src/arch/generic/mmapped_ipr.cc4
-rw-r--r--src/arch/generic/mmapped_ipr.hh21
-rw-r--r--src/arch/x86/tlb.cc2
-rw-r--r--src/mem/request.hh4
4 files changed, 13 insertions, 18 deletions
diff --git a/src/arch/generic/mmapped_ipr.cc b/src/arch/generic/mmapped_ipr.cc
index 3d85eea9f..1a356a5d5 100644
--- a/src/arch/generic/mmapped_ipr.cc
+++ b/src/arch/generic/mmapped_ipr.cc
@@ -53,7 +53,7 @@ Cycles
GenericISA::handleGenericIprRead(ThreadContext *xc, Packet *pkt)
{
Addr va(pkt->getAddr());
- Addr cls((va & IPR_CLASS_MASK) >> IPR_CLASS_SHIFT);
+ Addr cls(va >> IPR_CLASS_SHIFT);
switch (cls) {
case IPR_CLASS_PSEUDO_INST:
@@ -70,7 +70,7 @@ Cycles
GenericISA::handleGenericIprWrite(ThreadContext *xc, Packet *pkt)
{
Addr va(pkt->getAddr());
- Addr cls((va & IPR_CLASS_MASK) >> IPR_CLASS_SHIFT);
+ Addr cls(va >> IPR_CLASS_SHIFT);
switch (cls) {
case IPR_CLASS_PSEUDO_INST:
diff --git a/src/arch/generic/mmapped_ipr.hh b/src/arch/generic/mmapped_ipr.hh
index 55ce6e4d5..a371699eb 100644
--- a/src/arch/generic/mmapped_ipr.hh
+++ b/src/arch/generic/mmapped_ipr.hh
@@ -49,23 +49,12 @@ namespace GenericISA
* Memory requests with the MMAPPED_IPR flag are generally mapped
* to registers. There is a class of these registers that are
* internal to gem5, for example gem5 pseudo-ops in virtualized
- * mode.
- *
- * In order to make the IPR space manageable we always set bit 63
- * (IPR_GENERIC) for accesses that should be handled by the
- * generic ISA code. Architectures may use the rest of the IPR
- * space internally.
+ * mode. Such IPRs always have the flag GENERIC_IPR set and are
+ * handled by this code.
*/
- /** Is this a generic IPR access? */
- const Addr IPR_GENERIC = ULL(0x8000000000000000);
-
- /** @{ */
- /** Mask when extracting the class of a generic IPR */
- const Addr IPR_CLASS_MASK = ULL(0x7FFF000000000000);
/** Shift amount when extracting the class of a generic IPR */
const int IPR_CLASS_SHIFT = 48;
- /** @} */
/** Mask to extract the offset in within a generic IPR class */
const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
@@ -94,7 +83,7 @@ namespace GenericISA
inline Addr
iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
{
- return IPR_GENERIC | (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT) |
+ return (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT) |
(func << 8) | subfunc;
}
@@ -113,7 +102,9 @@ namespace GenericISA
inline bool
isGenericIprAccess(const Packet *pkt)
{
- return pkt->getAddr() & IPR_GENERIC;
+ Request::Flags flags(pkt->req->getFlags());
+ return (flags & Request::MMAPPED_IPR) &&
+ (flags & Request::GENERIC_IPR);
}
/**
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index e6ca166b3..458f33069 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -257,7 +257,7 @@ TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
req->setPaddr(x86LocalAPICAddress(tc->contextId(),
paddr - apicRange.start()));
} else if (m5opRange.contains(paddr)) {
- req->setFlags(Request::MMAPPED_IPR);
+ req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
req->setPaddr(GenericISA::iprAddressPseudoInst(
(paddr >> 8) & 0xFF,
paddr & 0xFF));
diff --git a/src/mem/request.hh b/src/mem/request.hh
index ac6e3550b..c3a3f47dc 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -127,6 +127,10 @@ class Request
/** The request should be marked as LRU. */
static const FlagsType EVICT_NEXT = 0x04000000;
+ /** The request should be handled by the generic IPR code (only
+ * valid together with MMAPPED_IPR) */
+ static const FlagsType GENERIC_IPR = 0x08000000;
+
/** These flags are *not* cleared when a Request object is reused
(assigned a new address). */
static const FlagsType STICKY_FLAGS = INST_FETCH;