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-rw-r--r--src/arch/alpha/linux/system.hh3
-rw-r--r--src/arch/arm/isa/insts/neon.isa2
-rw-r--r--src/arch/x86/interrupts.cc2
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa5
-rw-r--r--src/base/statistics.hh2
-rw-r--r--src/cpu/testers/traffic_gen/traffic_gen.hh13
-rw-r--r--src/dev/Ethernet.py2
-rw-r--r--src/dev/alpha/tsunami_io.hh2
-rw-r--r--src/dev/i8254xGBe.cc1
-rw-r--r--src/dev/i8254xGBe.hh3
-rw-r--r--src/dev/x86/intdev.hh6
-rw-r--r--src/mem/ruby/common/Consumer.hh3
-rw-r--r--src/mem/ruby/filters/BlockBloomFilter.hh2
-rw-r--r--src/mem/ruby/filters/BulkBloomFilter.hh2
-rw-r--r--src/mem/ruby/filters/H3BloomFilter.hh3
-rw-r--r--src/mem/ruby/filters/MultiBitSelBloomFilter.hh3
-rw-r--r--src/mem/ruby/filters/MultiGrainBloomFilter.hh3
-rw-r--r--src/mem/ruby/filters/NonCountingBloomFilter.hh3
-rw-r--r--src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh2
-rw-r--r--src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh2
-rw-r--r--src/mem/ruby/system/DMASequencer.hh1
-rw-r--r--src/mem/ruby/system/RubyPort.cc3
-rw-r--r--src/mem/ruby/system/RubyPort.hh2
23 files changed, 17 insertions, 53 deletions
diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh
index 345c17bb7..4f030c99f 100644
--- a/src/arch/alpha/linux/system.hh
+++ b/src/arch/alpha/linux/system.hh
@@ -89,10 +89,13 @@ class LinuxAlphaSystem : public AlphaSystem
/** Event to halt the simulator if the kernel calls panic() */
BreakPCEvent *kernelPanicEvent;
+#if 0
/** Event to halt the simulator if the kernel calls die_if_kernel */
BreakPCEvent *kernelDieEvent;
#endif
+#endif
+
/**
* Event to skip determine_cpu_caches() because we don't support
* the IPRs that the code can access to figure out cache sizes
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index 3296b3b55..876bb3bb7 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -2820,6 +2820,7 @@ let {{
4, vcvts2fpCode, fromInt = True)
vcvts2hCode = '''
+ destElem = 0;
FPSCR fpscr = (FPSCR) FpscrExc;
float srcFp1 = bitsToFp(srcElem1, (float)0.0);
if (flushToZero(srcFp1))
@@ -2836,6 +2837,7 @@ let {{
twoRegNarrowMiscInst("vcvt", "NVcvts2h", "SimdCvtOp", ("uint16_t",), vcvts2hCode)
vcvth2sCode = '''
+ destElem = 0;
FPSCR fpscr = (FPSCR) FpscrExc;
VfpSavedState state = prepFpState(VfpRoundNearest);
__asm__ __volatile__("" : "=m" (srcElem1), "=m" (destElem)
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index c693e6bbd..9983d7305 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -627,7 +627,7 @@ X86ISA::Interrupts::Interrupts(Params * p) :
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
pendingIPIs(0), cpu(NULL),
- intSlavePort(name() + ".int_slave", this, this, latency)
+ intSlavePort(name() + ".int_slave", this, this)
{
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 040f5d04f..a6173831c 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -399,8 +399,9 @@
// Really only the LSB matters, but the decoder
// will sign extend it, and there's no easy way to
// specify only checking the first byte.
- -0x80: SyscallInst::int80('xc->syscall(Rax)',
- IsSyscall, IsNonSpeculative, IsSerializeAfter);
+ 0xffffffffffffff80:
+ SyscallInst::int80('xc->syscall(Rax)',
+ IsSyscall, IsNonSpeculative, IsSerializeAfter);
}
}
0x6: decode MODE_SUBMODE {
diff --git a/src/base/statistics.hh b/src/base/statistics.hh
index 13347b733..3c1a55623 100644
--- a/src/base/statistics.hh
+++ b/src/base/statistics.hh
@@ -1327,8 +1327,6 @@ class DistStor
Counter max_track;
/** The number of entries in each bucket. */
Counter bucket_size;
- /** The number of buckets. Equal to (max-min)/bucket_size. */
- size_type buckets;
/** The smallest value sampled. */
Counter min_val;
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh b/src/cpu/testers/traffic_gen/traffic_gen.hh
index 75db025e5..fa08f4461 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.hh
+++ b/src/cpu/testers/traffic_gen/traffic_gen.hh
@@ -548,13 +548,6 @@ class TrafficGen : public MemObject
* state is complete.
*/
bool traceComplete;
-
- /**
- * Used to store the Tick when the next generate should
- * occur. It is to remove a transaction as soon as we
- * enter the state.
- */
- Tick oldEmitTime;
};
/** Pointer to owner of request handler */
@@ -582,8 +575,7 @@ class TrafficGen : public MemObject
public:
TrafficGenPort(const std::string& name, TrafficGen& _owner)
- : QueuedMasterPort(name, &_owner, queue), queue(_owner, *this),
- owner(_owner)
+ : QueuedMasterPort(name, &_owner, queue), queue(_owner, *this)
{ }
protected:
@@ -594,9 +586,6 @@ class TrafficGen : public MemObject
MasterPacketQueue queue;
- // Owner of the port
- TrafficGen& owner;
-
};
TrafficGenPort port;
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index 191aad3a1..0072b90fa 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -78,8 +78,6 @@ class IGbE(EtherDevice):
cxx_header = "dev/i8254xGBe.hh"
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
- use_flow_control = Param.Bool(False,
- "Should we use xon/xoff flow contorl (UNIMPLEMENTD)")
rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
rx_desc_cache_size = Param.Int(64,
diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh
index 7477fb124..684295551 100644
--- a/src/dev/alpha/tsunami_io.hh
+++ b/src/dev/alpha/tsunami_io.hh
@@ -51,8 +51,6 @@
*/
class TsunamiIO : public BasicPioDevice
{
- private:
- struct tm tm;
protected:
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 9a3ddaeb7..ee24b3922 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -58,7 +58,6 @@ using namespace Net;
IGbE::IGbE(const Params *p)
: EtherDevice(p), etherInt(NULL), drainManager(NULL),
- useFlowControl(p->use_flow_control),
rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size), rxTick(false),
txTick(false), txFifoTick(false), rxDmaPacket(false), pktOffset(0),
fetchDelay(p->fetch_delay), wbDelay(p->wb_delay),
diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh
index b8099fb1c..295712717 100644
--- a/src/dev/i8254xGBe.hh
+++ b/src/dev/i8254xGBe.hh
@@ -70,9 +70,6 @@ class IGbE : public EtherDevice
// The drain event if we have one
DrainManager *drainManager;
- // cached parameters from params struct
- bool useFlowControl;
-
// packet fifos
PacketFifo rxFifo;
PacketFifo txFifo;
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index a94ca47cc..99c361bae 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -66,11 +66,11 @@ class IntDev
class IntSlavePort : public MessageSlavePort
{
IntDev * device;
- Tick latency;
+
public:
IntSlavePort(const std::string& _name, MemObject* _parent,
- IntDev* dev, Tick _latency) :
- MessageSlavePort(_name, _parent), device(dev), latency(_latency)
+ IntDev* dev) :
+ MessageSlavePort(_name, _parent), device(dev)
{
}
diff --git a/src/mem/ruby/common/Consumer.hh b/src/mem/ruby/common/Consumer.hh
index 33c78d780..c1b4d70b1 100644
--- a/src/mem/ruby/common/Consumer.hh
+++ b/src/mem/ruby/common/Consumer.hh
@@ -44,7 +44,7 @@ class Consumer
{
public:
Consumer(ClockedObject *_em)
- : m_last_scheduled_wakeup(0), m_last_wakeup(0), em(_em)
+ : m_last_scheduled_wakeup(0), em(_em)
{
}
@@ -93,7 +93,6 @@ class Consumer
private:
Tick m_last_scheduled_wakeup;
std::set<Tick> m_scheduled_wakeups;
- Tick m_last_wakeup;
ClockedObject *em;
class ConsumerEvent : public Event
diff --git a/src/mem/ruby/filters/BlockBloomFilter.hh b/src/mem/ruby/filters/BlockBloomFilter.hh
index ade599f42..e7958df62 100644
--- a/src/mem/ruby/filters/BlockBloomFilter.hh
+++ b/src/mem/ruby/filters/BlockBloomFilter.hh
@@ -66,8 +66,6 @@ class BlockBloomFilter : public AbstractBloomFilter
int m_filter_size;
int m_filter_size_bits;
- int m_count_bits;
- int m_count;
};
#endif // __MEM_RUBY_FILTERS_BLOCKBLOOMFILTER_HH__
diff --git a/src/mem/ruby/filters/BulkBloomFilter.hh b/src/mem/ruby/filters/BulkBloomFilter.hh
index 50b24732f..1a723c51d 100644
--- a/src/mem/ruby/filters/BulkBloomFilter.hh
+++ b/src/mem/ruby/filters/BulkBloomFilter.hh
@@ -71,8 +71,6 @@ class BulkBloomFilter : public AbstractBloomFilter
int m_sector_bits;
- int m_count_bits;
- int m_count;
};
#endif // __MEM_RUBY_FILTERS_BULKBLOOMFILTER_HH__
diff --git a/src/mem/ruby/filters/H3BloomFilter.hh b/src/mem/ruby/filters/H3BloomFilter.hh
index b040af42f..c1b53c9b5 100644
--- a/src/mem/ruby/filters/H3BloomFilter.hh
+++ b/src/mem/ruby/filters/H3BloomFilter.hh
@@ -80,9 +80,6 @@ class H3BloomFilter : public AbstractBloomFilter
int m_par_filter_size;
int m_par_filter_size_bits;
- int m_count_bits;
- int m_count;
-
int primes_list[6];// = {9323,11279,10247,30637,25717,43711};
int mults_list[6]; //= {255,29,51,3,77,43};
int adds_list[6]; //= {841,627,1555,241,7777,65391};
diff --git a/src/mem/ruby/filters/MultiBitSelBloomFilter.hh b/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
index 5263309a4..f9a423648 100644
--- a/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
+++ b/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
@@ -82,9 +82,6 @@ class MultiBitSelBloomFilter : public AbstractBloomFilter
int m_par_filter_size;
int m_par_filter_size_bits;
- int m_count_bits;
- int m_count;
-
bool isParallel;
};
diff --git a/src/mem/ruby/filters/MultiGrainBloomFilter.hh b/src/mem/ruby/filters/MultiGrainBloomFilter.hh
index dfe9c3e98..d5a6e330c 100644
--- a/src/mem/ruby/filters/MultiGrainBloomFilter.hh
+++ b/src/mem/ruby/filters/MultiGrainBloomFilter.hh
@@ -71,9 +71,6 @@ class MultiGrainBloomFilter : public AbstractBloomFilter
std::vector<int> m_page_filter;
int m_page_filter_size;
int m_page_filter_size_bits;
-
- int m_count_bits;
- int m_count;
};
#endif // __MEM_RUBY_FILTERS_MULTIGRAINBLOOMFILTER_HH__
diff --git a/src/mem/ruby/filters/NonCountingBloomFilter.hh b/src/mem/ruby/filters/NonCountingBloomFilter.hh
index 57274ef87..c940a0805 100644
--- a/src/mem/ruby/filters/NonCountingBloomFilter.hh
+++ b/src/mem/ruby/filters/NonCountingBloomFilter.hh
@@ -73,9 +73,6 @@ class NonCountingBloomFilter : public AbstractBloomFilter
int m_filter_size;
int m_offset;
int m_filter_size_bits;
-
- int m_count_bits;
- int m_count;
};
#endif // __MEM_RUBY_FILTERS_NONCOUNTINGBLOOMFILTER_HH__
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
index 444cfae5c..4c1cae842 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
@@ -75,7 +75,7 @@ class flitBuffer_d
private:
std::vector<flit_d *> m_buffer;
- int size, max_size;
+ int max_size;
};
inline std::ostream&
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
index 4b244a608..609c5a9b6 100644
--- a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
@@ -58,7 +58,7 @@ class flitBuffer
private:
std::vector<flit *> m_buffer;
- int size, max_size;
+ int max_size;
};
inline std::ostream&
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index d8a6ef059..b3ba0be8c 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -73,7 +73,6 @@ class DMASequencer : public RubyPort
bool m_is_busy;
uint64_t m_data_block_mask;
DMARequest active_request;
- int num_active_requests;
};
#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 5e9e8cdd4..4cfc1f252 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -119,8 +119,7 @@ RubyPort::getSlavePort(const std::string &if_name, PortID idx)
RubyPort::PioPort::PioPort(const std::string &_name,
RubyPort *_port)
- : QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
- ruby_port(_port)
+ : QueuedMasterPort(_name, _port, queue), queue(*_port, *this)
{
DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
}
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 3c61eb522..70f74d83b 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -99,8 +99,6 @@ class RubyPort : public MemObject
MasterPacketQueue queue;
- RubyPort *ruby_port;
-
public:
PioPort(const std::string &_name, RubyPort *_port);