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-rw-r--r--src/mem/simple_dram.cc9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/mem/simple_dram.cc b/src/mem/simple_dram.cc
index c537006a1..280ab640d 100644
--- a/src/mem/simple_dram.cc
+++ b/src/mem/simple_dram.cc
@@ -1135,12 +1135,11 @@ SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt)
// The absolute soonest you have to start thinking about the
// next request is the longest access time that can occur before
- // busBusyUntil. Assuming you need to meet tRAS, then precharge,
- // open a new row, and access, it is ~4*tRCD.
+ // busBusyUntil. Assuming you need to precharge,
+ // open a new row, and access, it is tRP + tRCD + tCL
-
- Tick newTime = (busBusyUntil > 4 * tRCD) ?
- std::max(busBusyUntil - 4 * tRCD, curTick()) :
+ Tick newTime = (busBusyUntil > tRP + tRCD + tCL ) ?
+ std::max(busBusyUntil - (tRP + tRCD + tCL) , curTick()) :
curTick();
if (!nextReqEvent.scheduled() && !stopReads){