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-rw-r--r--src/arch/arm/isa/formats/misc.isa3
-rw-r--r--src/arch/arm/miscregs.hh6
2 files changed, 6 insertions, 3 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 897ecf3e3..5498a84b0 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -94,6 +94,9 @@ def format McrMrc15() {{
return new NopInst(machInst);
} else if (miscReg == NUM_MISCREGS) {
return new Unknown(machInst);
+ } else if (miscReg == MISCREG_DCCISW) {
+ return new WarnUnimplemented(isRead ? "mrc dccisw" : "mcr dcisw",
+ machInst);
} else {
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 8fce26b2c..c65b55a52 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -82,6 +82,7 @@ namespace ArmISA
// CP15 registers
MISCREG_CP15_START,
MISCREG_SCTLR = MISCREG_CP15_START,
+ MISCREG_DCCISW,
MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR,
@@ -136,7 +137,6 @@ namespace ArmISA
MISCREG_CP15DMB,
MISCREG_DCCMVAU,
MISCREG_DCCIMVAC,
- MISCREG_DCCISW,
MISCREG_CONTEXTIDR,
MISCREG_TPIDRURW,
MISCREG_TPIDRURO,
@@ -158,7 +158,7 @@ namespace ArmISA
"cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
"spsr_mon", "spsr_und", "spsr_abt",
"fpsr", "fpsid", "fpscr", "fpexc",
- "sctlr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
+ "sctlr", "dccisw", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@@ -167,7 +167,7 @@ namespace ArmISA
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
"cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
- "cp15dsb", "cp15dmb", "dccmvau", "dccimvac", "dccisw",
+ "cp15dsb", "cp15dmb", "dccmvau", "dccimvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"nop", "raz"
};