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-rw-r--r--src/arch/sparc/tlb.cc12
-rw-r--r--src/mem/request.hh28
2 files changed, 27 insertions, 13 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 66e75a98a..72126a928 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -420,7 +420,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
Addr vaddr = req->getVaddr();
TlbEntry *e;
- assert(req->getAsi() == ASI_IMPLICIT);
+ assert(req->getArchFlags() == ASI_IMPLICIT);
DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
vaddr, req->getSize());
@@ -536,7 +536,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
Addr vaddr = req->getVaddr();
Addr size = req->getSize();
ASI asi;
- asi = (ASI)req->getAsi();
+ asi = (ASI)req->getArchFlags();
bool implicit = false;
bool hpriv = bits(tlbdata,0,0);
bool unaligned = vaddr & (size - 1);
@@ -858,11 +858,11 @@ Cycles
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
Addr va = pkt->getAddr();
- ASI asi = (ASI)pkt->req->getAsi();
+ ASI asi = (ASI)pkt->req->getArchFlags();
uint64_t temp;
DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
- (uint32_t)pkt->req->getAsi(), pkt->getAddr());
+ (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
TLB *itb = tc->getITBPtr();
@@ -1044,7 +1044,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
{
uint64_t data = pkt->get<uint64_t>();
Addr va = pkt->getAddr();
- ASI asi = (ASI)pkt->req->getAsi();
+ ASI asi = (ASI)pkt->req->getArchFlags();
Addr ta_insert;
Addr va_insert;
@@ -1286,7 +1286,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
default:
doMmuWriteError:
panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
- (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
+ (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
}
pkt->makeAtomicResponse();
return Cycles(1);
diff --git a/src/mem/request.hh b/src/mem/request.hh
index c3a3f47dc..f37e34dd4 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -86,10 +86,17 @@ class Request
{
public:
typedef uint32_t FlagsType;
+ typedef uint8_t ArchFlagsType;
typedef ::Flags<FlagsType> Flags;
- /** ASI information for this request if it exists. */
- static const FlagsType ASI_BITS = 0x000000FF;
+ /**
+ * Architecture specific flags.
+ *
+ * These bits int the flag field are reserved for
+ * architecture-specific code. For example, SPARC uses them to
+ * represent ASIs.
+ */
+ static const FlagsType ARCH_BITS = 0x000000FF;
/** The request was an instruction fetch. */
static const FlagsType INST_FETCH = 0x00000100;
/** The virtual address is also the physical address. */
@@ -422,6 +429,13 @@ class Request
_flags.set(flags);
}
+ void
+ setArchFlags(Flags flags)
+ {
+ assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
+ _flags.set(flags & ARCH_BITS);
+ }
+
/** Accessor function for vaddr.*/
Addr
getVaddr()
@@ -452,12 +466,12 @@ class Request
_asid = asid;
}
- /** Accessor function for asi.*/
- uint8_t
- getAsi()
+ /** Accessor function for architecture-specific flags.*/
+ ArchFlagsType
+ getArchFlags()
{
- assert(privateFlags.isSet(VALID_VADDR));
- return _flags & ASI_BITS;
+ assert(privateFlags.isSet(VALID_PADDR|VALID_VADDR));
+ return _flags & ARCH_BITS;
}
/** Accessor function to check if sc result is valid. */