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-rw-r--r--src/arch/arm/kvm/gic.cc229
-rw-r--r--src/arch/arm/kvm/gic.hh51
-rw-r--r--src/cpu/kvm/base.hh1
-rw-r--r--src/cpu/kvm/vm.cc12
-rw-r--r--src/cpu/kvm/vm.hh6
-rw-r--r--src/dev/arm/base_gic.hh13
-rw-r--r--src/dev/arm/gic_pl390.hh20
7 files changed, 310 insertions, 22 deletions
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 64fb7c6c6..7cf4d07c6 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -43,6 +43,7 @@
#include <linux/kvm.h>
#include "arch/arm/kvm/base_cpu.hh"
+#include "debug/GIC.hh"
#include "debug/Interrupt.hh"
#include "params/MuxingKvmGic.hh"
@@ -104,6 +105,63 @@ KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
vm.setIRQLine(line, high);
}
+uint32_t
+KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
+{
+ uint64_t reg;
+
+ assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
+ const uint32_t attr(
+ (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
+ (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
+
+ kdev.getAttrPtr(group, attr, &reg);
+ return (uint32_t) reg;
+}
+
+void
+KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
+ unsigned value)
+{
+ uint64_t reg = value;
+
+ assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
+ const uint32_t attr(
+ (vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
+ (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
+
+ kdev.setAttrPtr(group, attr, &reg);
+}
+
+uint32_t
+KvmKernelGicV2::readDistributor(ContextID ctx, Addr daddr)
+{
+ auto vcpu = vm.contextIdToVCpuId(ctx);
+ return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
+}
+
+uint32_t
+KvmKernelGicV2::readCpu(ContextID ctx, Addr daddr)
+{
+ auto vcpu = vm.contextIdToVCpuId(ctx);
+ return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
+}
+
+void
+KvmKernelGicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
+{
+ auto vcpu = vm.contextIdToVCpuId(ctx);
+ setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
+}
+
+void
+KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
+{
+ auto vcpu = vm.contextIdToVCpuId(ctx);
+ setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
+}
+
+
MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
: Pl390(p),
@@ -122,20 +180,38 @@ MuxingKvmGic::~MuxingKvmGic()
}
void
+MuxingKvmGic::loadState(CheckpointIn &cp)
+{
+ Pl390::loadState(cp);
+}
+
+void
MuxingKvmGic::startup()
{
+ Pl390::startup();
usingKvm = (kernelGic != nullptr) && validKvmEnvironment();
+ if (usingKvm)
+ fromPl390ToKvm();
+}
+
+DrainState
+MuxingKvmGic::drain()
+{
+ if (usingKvm)
+ fromKvmToPl390();
+ return Pl390::drain();
}
void
MuxingKvmGic::drainResume()
{
+ Pl390::drainResume();
bool use_kvm = (kernelGic != nullptr) && validKvmEnvironment();
if (use_kvm != usingKvm) {
+ // Should only occur due to CPU switches
if (use_kvm) // from simulation to KVM emulation
fromPl390ToKvm();
- else // from KVM emulation to simulation
- fromKvmToPl390();
+ // otherwise, drain() already sync'd the state back to the Pl390
usingKvm = use_kvm;
}
@@ -144,19 +220,14 @@ MuxingKvmGic::drainResume()
void
MuxingKvmGic::serialize(CheckpointOut &cp) const
{
- if (!usingKvm)
- return Pl390::serialize(cp);
-
- panic("Checkpointing unsupported\n");
+ // drain() already ensured Pl390 updated with KvmGic state if necessary
+ Pl390::serialize(cp);
}
void
MuxingKvmGic::unserialize(CheckpointIn &cp)
{
- if (!usingKvm)
- return Pl390::unserialize(cp);
-
- panic("Checkpointing unsupported\n");
+ Pl390::unserialize(cp);
}
Tick
@@ -231,15 +302,149 @@ MuxingKvmGic::validKvmEnvironment() const
}
void
+MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, Addr daddr)
+{
+ auto val = from->readDistributor(ctx, daddr);
+ DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
+ to->writeDistributor(ctx, daddr, val);
+}
+
+void
+MuxingKvmGic::copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, Addr daddr)
+{
+ auto val = from->readCpu(ctx, daddr);
+ DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
+ to->writeCpu(ctx, daddr, val);
+}
+
+void
+MuxingKvmGic::copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
+ Addr daddr, size_t size)
+{
+ for (int ctx = 0; ctx < system._numContexts; ++ctx)
+ for (auto a = daddr; a < daddr + size; a += 4)
+ copyDistRegister(from, to, ctx, a);
+}
+
+void
+MuxingKvmGic::clearBankedDistRange(BaseGicRegisters* to,
+ Addr daddr, size_t size)
+{
+ for (int ctx = 0; ctx < system._numContexts; ++ctx)
+ for (auto a = daddr; a < daddr + size; a += 4)
+ to->writeDistributor(ctx, a, 0xFFFFFFFF);
+}
+
+void
+MuxingKvmGic::copyDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
+ Addr daddr, size_t size)
+{
+ for (auto a = daddr; a < daddr + size; a += 4)
+ copyDistRegister(from, to, 0, a);
+}
+
+void
+MuxingKvmGic::clearDistRange(BaseGicRegisters* to,
+ Addr daddr, size_t size)
+{
+ for (auto a = daddr; a < daddr + size; a += 4)
+ to->writeDistributor(0, a, 0xFFFFFFFF);
+}
+
+void
+MuxingKvmGic::copyGicState(BaseGicRegisters* from, BaseGicRegisters* to)
+{
+ Addr set, clear;
+ size_t size;
+
+ /// CPU state (GICC_*)
+ // Copy CPU Interface Control Register (CTLR),
+ // Interrupt Priority Mask Register (PMR), and
+ // Binary Point Register (BPR)
+ for (int ctx = 0; ctx < system._numContexts; ++ctx) {
+ copyCpuRegister(from, to, ctx, GICC_CTLR);
+ copyCpuRegister(from, to, ctx, GICC_PMR);
+ copyCpuRegister(from, to, ctx, GICC_BPR);
+ }
+
+
+ /// Distributor state (GICD_*)
+ // Copy Distributor Control Register (CTLR)
+ copyDistRegister(from, to, 0, GICD_CTLR);
+
+ // Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
+ set = Pl390::GICD_ISENABLER.start();
+ clear = Pl390::GICD_ICENABLER.start();
+ size = Pl390::itLines / 8;
+ clearBankedDistRange(to, clear, 4);
+ copyBankedDistRange(from, to, set, 4);
+
+ set += 4, clear += 4, size -= 4;
+ clearDistRange(to, clear, size);
+ copyDistRange(from, to, set, size);
+
+ // Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
+ set = Pl390::GICD_ISPENDR.start();
+ clear = Pl390::GICD_ICPENDR.start();
+ size = Pl390::itLines / 8;
+ clearBankedDistRange(to, clear, 4);
+ copyBankedDistRange(from, to, set, 4);
+
+ set += 4, clear += 4, size -= 4;
+ clearDistRange(to, clear, size);
+ copyDistRange(from, to, set, size);
+
+ // Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
+ set = Pl390::GICD_ISACTIVER.start();
+ clear = Pl390::GICD_ICACTIVER.start();
+ size = Pl390::itLines / 8;
+ clearBankedDistRange(to, clear, 4);
+ copyBankedDistRange(from, to, set, 4);
+
+ set += 4, clear += 4, size -= 4;
+ clearDistRange(to, clear, size);
+ copyDistRange(from, to, set, size);
+
+ // Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
+ set = Pl390::GICD_IPRIORITYR.start();
+ copyBankedDistRange(from, to, set, 32);
+
+ set += 32;
+ size = Pl390::itLines - 32;
+ copyDistRange(from, to, set, size);
+
+ // Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
+ set = Pl390::GICD_ITARGETSR.start() + 32;
+ size = Pl390::itLines - 32;
+ copyDistRange(from, to, set, size);
+
+ // Copy interrupt configuration registers (ICFGRn)
+ set = Pl390::GICD_ICFGR.start();
+ size = Pl390::itLines / 4;
+ copyDistRange(from, to, set, size);
+}
+
+void
MuxingKvmGic::fromPl390ToKvm()
{
- panic("Gic multiplexing not implemented.\n");
+ copyGicState(static_cast<Pl390*>(this), kernelGic);
}
void
MuxingKvmGic::fromKvmToPl390()
{
- panic("Gic multiplexing not implemented.\n");
+ copyGicState(kernelGic, static_cast<Pl390*>(this));
+
+ // the values read for the Interrupt Priority Mask Register (PMR)
+ // have been shifted by three bits due to its having been emulated by
+ // a VGIC with only 5 PMR bits in its VMCR register. Presently the
+ // Linux kernel does not repair this inaccuracy, so we correct it here.
+ for (int cpu = 0; cpu < system._numContexts; ++cpu) {
+ cpuPriority[cpu] <<= 3;
+ assert((cpuPriority[cpu] & ~0xff) == 0);
+ }
}
MuxingKvmGic *
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index 7e2e772b8..b5544486c 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -54,7 +54,7 @@
* model. It exposes an API that is similar to that of
* software-emulated GIC models in gem5.
*/
-class KvmKernelGicV2
+class KvmKernelGicV2 : public BaseGicRegisters
{
public:
/**
@@ -117,6 +117,14 @@ class KvmKernelGicV2
/** Address range for the distributor interface */
const AddrRange distRange;
+ /** BaseGicRegisters interface */
+ uint32_t readDistributor(ContextID ctx, Addr daddr) override;
+ uint32_t readCpu(ContextID ctx, Addr daddr) override;
+
+ void writeDistributor(ContextID ctx, Addr daddr,
+ uint32_t data) override;
+ void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
+
/* @} */
protected:
@@ -130,6 +138,26 @@ class KvmKernelGicV2
*/
void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high);
+ /**
+ * Get value of GIC register "from" a cpu
+ *
+ * @param group Distributor or CPU (KVM_DEV_ARM_VGIC_GRP_{DIST,CPU}_REGS)
+ * @param vcpu CPU id within KVM
+ * @param offset register offset
+ */
+ uint32_t getGicReg(unsigned group, unsigned vcpu, unsigned offset);
+
+ /**
+ * Set value of GIC register "from" a cpu
+ *
+ * @param group Distributor or CPU (KVM_DEV_ARM_VGIC_GRP_{DIST,CPU}_REGS)
+ * @param vcpu CPU id within KVM
+ * @param offset register offset
+ * @param value value to set register to
+ */
+ void setGicReg(unsigned group, unsigned vcpu, unsigned offset,
+ unsigned value);
+
/** KVM VM in the parent system */
KvmVM &vm;
@@ -146,7 +174,10 @@ class MuxingKvmGic : public Pl390
MuxingKvmGic(const MuxingKvmGicParams *p);
~MuxingKvmGic();
+ void loadState(CheckpointIn &cp) override;
+
void startup() override;
+ DrainState drain() override;
void drainResume() override;
void serialize(CheckpointOut &cp) const override;
@@ -176,9 +207,25 @@ class MuxingKvmGic : public Pl390
private:
bool usingKvm;
- /** Multiplexing implementation: state transfer functions */
+ /** Multiplexing implementation */
void fromPl390ToKvm();
void fromKvmToPl390();
+
+ void copyGicState(BaseGicRegisters* from, BaseGicRegisters* to);
+
+ void copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, Addr daddr);
+ void copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
+ ContextID ctx, Addr daddr);
+
+ void copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
+ Addr daddr, size_t size);
+ void clearBankedDistRange(BaseGicRegisters* to,
+ Addr daddr, size_t size);
+ void copyDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
+ Addr daddr, size_t size);
+ void clearDistRange(BaseGicRegisters* to,
+ Addr daddr, size_t size);
};
#endif // __ARCH_ARM_KVM_GIC_HH__
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index ef500974f..6f30c55e4 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -106,6 +106,7 @@ class BaseKvmCPU : public BaseCPU
void deallocateContext(ThreadID thread_num);
void haltContext(ThreadID thread_num) override;
+ long getVCpuID() const { return vcpuID; }
ThreadContext *getContext(int tn) override;
Counter totalInsts() const override;
diff --git a/src/cpu/kvm/vm.cc b/src/cpu/kvm/vm.cc
index 604d182ab..47e749247 100644
--- a/src/cpu/kvm/vm.cc
+++ b/src/cpu/kvm/vm.cc
@@ -50,6 +50,7 @@
#include <cerrno>
#include <memory>
+#include "cpu/kvm/base.hh"
#include "debug/Kvm.hh"
#include "params/KvmVM.hh"
#include "sim/system.hh"
@@ -528,12 +529,21 @@ KvmVM::createDevice(uint32_t type, uint32_t flags)
}
void
-KvmVM::setSystem(System *s) {
+KvmVM::setSystem(System *s)
+{
panic_if(system != nullptr, "setSystem() can only be called once");
panic_if(s == nullptr, "setSystem() called with null System*");
system = s;
}
+long
+KvmVM::contextIdToVCpuId(ContextID ctx) const
+{
+ assert(system != nullptr);
+ return dynamic_cast<BaseKvmCPU*>
+ (system->getThreadContext(ctx)->getCpuPtr())->getVCpuID();
+}
+
int
KvmVM::createVCPU(long vcpuID)
{
diff --git a/src/cpu/kvm/vm.hh b/src/cpu/kvm/vm.hh
index dbd46aa3c..df2e4119a 100644
--- a/src/cpu/kvm/vm.hh
+++ b/src/cpu/kvm/vm.hh
@@ -48,6 +48,7 @@
// forward declarations
struct KvmVMParams;
+class BaseKvmCPU;
class System;
/**
@@ -405,6 +406,11 @@ class KvmVM : public SimObject
*/
void setSystem(System *s);
+ /**
+ * Get the VCPUID for a given context
+ */
+ long contextIdToVCpuId(ContextID ctx) const;
+
#if defined(__aarch64__)
public: // ARM-specific
/**
diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh
index facc99084..cd16c0362 100644
--- a/src/dev/arm/base_gic.hh
+++ b/src/dev/arm/base_gic.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2012-2013, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -92,4 +92,15 @@ class BaseGic : public PioDevice
Platform *platform;
};
+class BaseGicRegisters
+{
+ public:
+ virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
+ virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
+
+ virtual void writeDistributor(ContextID ctx, Addr daddr,
+ uint32_t data) = 0;
+ virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
+};
+
#endif
diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh
index 8beb5e2d5..6f819bf65 100644
--- a/src/dev/arm/gic_pl390.hh
+++ b/src/dev/arm/gic_pl390.hh
@@ -58,7 +58,7 @@
#include "dev/platform.hh"
#include "params/Pl390.hh"
-class Pl390 : public BaseGic
+class Pl390 : public BaseGic, public BaseGicRegisters
{
protected:
// distributor memory addresses
@@ -404,26 +404,34 @@ class Pl390 : public BaseGic
* @param pkt packet to respond to
*/
Tick readDistributor(PacketPtr pkt);
- uint32_t readDistributor(ContextID ctx, Addr daddr, size_t resp_sz);
+ uint32_t readDistributor(ContextID ctx, Addr daddr,
+ size_t resp_sz);
+ uint32_t readDistributor(ContextID ctx, Addr daddr) override {
+ return readDistributor(ctx, daddr, 4);
+ }
/** Handle a read to the cpu portion of the GIC
* @param pkt packet to respond to
*/
Tick readCpu(PacketPtr pkt);
- uint32_t readCpu(ContextID ctx, Addr daddr);
+ uint32_t readCpu(ContextID ctx, Addr daddr) override;
/** Handle a write to the distributor portion of the GIC
* @param pkt packet to respond to
*/
Tick writeDistributor(PacketPtr pkt);
- void writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
- size_t data_sz);
+ void writeDistributor(ContextID ctx, Addr daddr,
+ uint32_t data, size_t data_sz);
+ void writeDistributor(ContextID ctx, Addr daddr,
+ uint32_t data) override {
+ return writeDistributor(ctx, daddr, data, 4);
+ }
/** Handle a write to the cpu portion of the GIC
* @param pkt packet to respond to
*/
Tick writeCpu(PacketPtr pkt);
- void writeCpu(ContextID ctx, Addr daddr, uint32_t data);
+ void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
};
#endif //__DEV_ARM_GIC_H__
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 15:16:58 +0000