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-rw-r--r--src/arch/arm/isa.cc3
-rw-r--r--src/arch/arm/table_walker.cc1
-rw-r--r--src/arch/x86/isa.cc4
-rw-r--r--src/arch/x86/isa/microops/regop.isa3
-rw-r--r--src/base/compiler.hh14
-rw-r--r--src/base/cprintf.cc6
-rw-r--r--src/base/imgwriter.cc2
-rw-r--r--src/cpu/kvm/base.cc2
-rw-r--r--src/cpu/kvm/x86_cpu.cc6
-rw-r--r--src/cpu/minor/dyn_inst.cc1
-rw-r--r--src/dev/arm/generic_timer.cc4
-rw-r--r--src/dev/net/i8254xGBe.cc9
-rw-r--r--src/dev/pci/copy_engine.cc2
-rw-r--r--src/dev/storage/ide_disk.cc1
-rw-r--r--src/dev/x86/i8042.cc2
-rw-r--r--src/kern/linux/printk.cc2
-rw-r--r--src/mem/slicc/symbols/Type.py1
-rw-r--r--src/sim/eventq.hh1
-rw-r--r--src/sim/fd_array.cc3
19 files changed, 50 insertions, 17 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a490e5fb7..44e4ff376 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1653,6 +1653,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
}
}
+ M5_FALLTHROUGH;
case MISCREG_TTBR0:
case MISCREG_TTBR1:
{
@@ -1666,12 +1667,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
}
}
}
+ M5_FALLTHROUGH;
case MISCREG_SCTLR_EL1:
{
tc->getITBPtr()->invalidateMiscReg();
tc->getDTBPtr()->invalidateMiscReg();
setMiscRegNoEffect(misc_reg, newVal);
}
+ M5_FALLTHROUGH;
case MISCREG_CONTEXTIDR:
case MISCREG_PRRR:
case MISCREG_NMRR:
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 2d6664264..63b67f56a 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1398,6 +1398,7 @@ TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient
case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient
warn_if(!attr_hi, "Unpredictable behavior");
+ M5_FALLTHROUGH;
case 0x4: // Device-nGnRE memory or
// Normal memory, Inner Non-cacheable
case 0x8: // Device-nGRE memory or
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 9dd7fbb52..f092f4418 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -316,7 +316,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
break;
case MISCREG_DR4:
miscReg = MISCREG_DR6;
- /* Fall through to have the same effects as DR6. */
+ M5_FALLTHROUGH;
case MISCREG_DR6:
{
DR6 dr6 = regVal[MISCREG_DR6];
@@ -333,7 +333,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
break;
case MISCREG_DR5:
miscReg = MISCREG_DR7;
- /* Fall through to have the same effects as DR7. */
+ M5_FALLTHROUGH;
case MISCREG_DR7:
{
DR7 dr7 = regVal[MISCREG_DR7];
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 4fd3b2aa6..2d5ae048a 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1427,6 +1427,7 @@ let {{
if (bits(newVal, 63, 4))
fault = std::make_shared<GeneralProtection>(0);
}
+ break;
default:
fault = std::make_shared<GenericISA::M5PanicFault>(
"Unrecognized control register %d.\\n", dest);
@@ -1528,7 +1529,7 @@ let {{
fault = std::make_shared<GeneralProtection>(selector);
break;
}
- // Fall through on purpose
+ M5_FALLTHROUGH;
case SegIntGateCheck:
// Make sure the gate's the right type.
if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index 2fdd323b9..6920dad10 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -63,6 +63,20 @@
# define M5_CLASS_VAR_USED
#endif
+// This can be removed once all compilers support C++17
+#if defined __has_cpp_attribute
+ // Note: We must separate this if statement because GCC < 5.0 doesn't
+ // support the function-like syntax in #if statements.
+ #if __has_cpp_attribute(fallthrough)
+ #define M5_FALLTHROUGH [[fallthrough]]
+ #else
+ #define M5_FALLTHROUGH
+ #endif
+#else
+ // Unsupported (and no warning) on GCC < 7.
+ #define M5_FALLTHROUGH
+#endif
+
// std::make_unique redefined for C++11 compilers
namespace m5
{
diff --git a/src/base/cprintf.cc b/src/base/cprintf.cc
index 5daf196f1..caf1bb847 100644
--- a/src/base/cprintf.cc
+++ b/src/base/cprintf.cc
@@ -35,6 +35,8 @@
#include <iostream>
#include <sstream>
+#include "base/compiler.hh"
+
using namespace std;
namespace cp {
@@ -138,6 +140,7 @@ Print::process_flag()
case 'X':
fmt.uppercase = true;
+ M5_FALLTHROUGH;
case 'x':
fmt.base = Format::hex;
fmt.format = Format::integer;
@@ -159,6 +162,7 @@ Print::process_flag()
case 'G':
fmt.uppercase = true;
+ M5_FALLTHROUGH;
case 'g':
fmt.format = Format::floating;
fmt.float_format = Format::best;
@@ -167,6 +171,7 @@ Print::process_flag()
case 'E':
fmt.uppercase = true;
+ M5_FALLTHROUGH;
case 'e':
fmt.format = Format::floating;
fmt.float_format = Format::scientific;
@@ -213,6 +218,7 @@ Print::process_flag()
fmt.fill_zero = true;
break;
}
+ M5_FALLTHROUGH;
case '1':
case '2':
case '3':
diff --git a/src/base/imgwriter.cc b/src/base/imgwriter.cc
index 40de3d7cc..13ff86c30 100644
--- a/src/base/imgwriter.cc
+++ b/src/base/imgwriter.cc
@@ -59,7 +59,7 @@ createImgWriter(Enums::ImageFormat type, const FrameBuffer *fb)
// gem5 will try PNG first, and it will fallback to BMP if not
// available.
- /* FALLTHROUGH */
+ M5_FALLTHROUGH;
#if USE_PNG
case Enums::Png:
return std::unique_ptr<PngWriter>(new PngWriter(fb));
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index ab83e5d2f..3df0fddda 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -383,7 +383,7 @@ BaseKvmCPU::drain()
deschedule(tickEvent);
_status = Idle;
- /** FALLTHROUGH */
+ M5_FALLTHROUGH;
case Idle:
// Idle, no need to drain
assert(!tickEvent.scheduled());
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index 467e1baaf..1a23b6717 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -396,6 +396,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_ES:
if (seg.unusable)
break;
+ M5_FALLTHROUGH;
case MISCREG_CS:
if (seg.base & 0xffffffff00000000ULL)
warn("Illegal %s base: 0x%x\n", name, seg.base);
@@ -433,7 +434,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case 3:
if (sregs.cs.type == 3 && seg.dpl != 0)
warn("CS type is 3, but SS DPL is != 0.\n");
- /* FALLTHROUGH */
+ M5_FALLTHROUGH;
case 7:
if (!(sregs.cr0 & 1) && seg.dpl != 0)
warn("SS DPL is %i, but CR0 PE is 0\n", seg.dpl);
@@ -477,6 +478,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_GS:
if (seg.unusable)
break;
+ M5_FALLTHROUGH;
case MISCREG_CS:
if (!seg.s)
warn("%s: S flag not set\n", name);
@@ -485,6 +487,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_TSL:
if (seg.unusable)
break;
+ M5_FALLTHROUGH;
case MISCREG_TR:
if (seg.s)
warn("%s: S flag is set\n", name);
@@ -500,6 +503,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_TSL:
if (seg.unusable)
break;
+ M5_FALLTHROUGH;
case MISCREG_TR:
case MISCREG_CS:
if (!seg.present)
diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index 756b214bd..353163758 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -169,6 +169,7 @@ printRegName(std::ostream &os, const RegId& reg)
break;
case CCRegClass:
os << 'c' << static_cast<unsigned int>(reg.index());
+ break;
default:
panic("Unknown register class: %d", (int)reg.classValue());
}
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 350867488..f8433bd2d 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -385,7 +385,7 @@ GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
case MISCREG_CNTPS_CVAL_EL1:
case MISCREG_CNTPS_TVAL_EL1:
case MISCREG_CNTPS_CTL_EL1:
- /* FALLTHROUGH */
+ M5_FALLTHROUGH;
// PL2 phys. timer, non-secure
case MISCREG_CNTHCTL:
@@ -466,7 +466,7 @@ GenericTimer::readMiscReg(int reg, unsigned cpu)
case MISCREG_CNTPS_CVAL_EL1:
case MISCREG_CNTPS_TVAL_EL1:
case MISCREG_CNTPS_CTL_EL1:
- /* FALLTHROUGH */
+ M5_FALLTHROUGH;
// PL2 phys. timer, non-secure
case MISCREG_CNTHCTL:
diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 3dde72ac7..3359b0d61 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -2290,14 +2290,13 @@ IGbE::rxStateMachine()
int descLeft = rxDescCache.descLeft();
DPRINTF(EthernetSM, "RXS: descLeft: %d rdmts: %d rdlen: %d\n",
descLeft, regs.rctl.rdmts(), regs.rdlen());
- switch (regs.rctl.rdmts()) {
- case 2: if (descLeft > .125 * regs.rdlen()) break;
- case 1: if (descLeft > .250 * regs.rdlen()) break;
- case 0: if (descLeft > .500 * regs.rdlen()) break;
+
+ // rdmts 2->1/8, 1->1/4, 0->1/2
+ int ratio = (1ULL << (regs.rctl.rdmts() + 1));
+ if (descLeft * ratio <= regs.rdlen()) {
DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) "
"because of descriptors left\n");
postInterrupt(IT_RXDMT);
- break;
}
if (rxFifo.empty())
diff --git a/src/dev/pci/copy_engine.cc b/src/dev/pci/copy_engine.cc
index 3c7df7d3a..7c87da1c0 100644
--- a/src/dev/pci/copy_engine.cc
+++ b/src/dev/pci/copy_engine.cc
@@ -249,7 +249,7 @@ CopyEngine::CopyEngineChannel::channelRead(Packet *pkt, Addr daddr, int size)
break;
case CHAN_STATUS:
assert(size == sizeof(uint64_t));
- pkt->set<uint64_t>(cr.status() | ~busy);
+ pkt->set<uint64_t>(cr.status() | (busy ? 0 : 1));
break;
case CHAN_CHAINADDR:
assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
diff --git a/src/dev/storage/ide_disk.cc b/src/dev/storage/ide_disk.cc
index 08d374fa3..020e4582d 100644
--- a/src/dev/storage/ide_disk.cc
+++ b/src/dev/storage/ide_disk.cc
@@ -705,6 +705,7 @@ IdeDisk::startCommand()
// Supported DMA commands
case WDCC_WRITEDMA:
dmaRead = true; // a write to the disk is a DMA read from memory
+ M5_FALLTHROUGH;
case WDCC_READDMA:
if (!(cmdReg.drive & DRIVE_LBA_BIT))
panic("Attempt to perform CHS access, only supports LBA\n");
diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index 39b02055b..c5fca1b47 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -455,10 +455,12 @@ X86ISA::I8042::write(PacketPtr pkt)
case WriteOutputPort:
warn("i8042 \"Write output port\" command not implemented.\n");
lastCommand = WriteOutputPort;
+ break;
case WriteKeyboardOutputBuff:
warn("i8042 \"Write keyboard output buffer\" "
"command not implemented.\n");
lastCommand = WriteKeyboardOutputBuff;
+ break;
case WriteMouseOutputBuff:
DPRINTF(I8042, "Got command to write to mouse output buffer.\n");
lastCommand = WriteMouseOutputBuff;
diff --git a/src/kern/linux/printk.cc b/src/kern/linux/printk.cc
index adc2009df..788a343b3 100644
--- a/src/kern/linux/printk.cc
+++ b/src/kern/linux/printk.cc
@@ -101,6 +101,7 @@ Printk(stringstream &out, Arguments args)
break;
case 'P':
format = true;
+ M5_FALLTHROUGH;
case 'p':
hexnum = true;
break;
@@ -258,4 +259,3 @@ Printk(stringstream &out, Arguments args)
}
}
-
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 4f4f0585d..188d6dd75 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -734,6 +734,7 @@ ${{self.c_ident}}_base_number(const ${{self.c_ident}}& obj)
code(' base += ${{enum.ident}}_Controller::getNumControllers();')
else:
code(' base += 0;')
+ code(' M5_FALLTHROUGH;')
code(' case ${{self.c_ident}}_${{enum.ident}}:')
code(' break;')
code.dedent()
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 0a0405fef..781bcdbf9 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -41,6 +41,7 @@
#include <algorithm>
#include <cassert>
#include <climits>
+#include <functional>
#include <iosfwd>
#include <memory>
#include <mutex>
diff --git a/src/sim/fd_array.cc b/src/sim/fd_array.cc
index 15cfe11ef..7f3f7dd24 100644
--- a/src/sim/fd_array.cc
+++ b/src/sim/fd_array.cc
@@ -131,8 +131,7 @@ FDArray::restoreFileOffsets()
* possible to guarantee that the simulation will proceed as it should
* have in the same way that it would have proceeded sans checkpoints.
*/
- void (*seek)(std::shared_ptr<FileFDEntry>)
- = [] (std::shared_ptr<FileFDEntry> ffd)
+ auto seek = [] (std::shared_ptr<FileFDEntry> ffd)
{
if (lseek(ffd->getSimFD(), ffd->getFileOffset(), SEEK_SET) < 0)
fatal("Unable to seek to location in %s", ffd->getFileName());
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 17:23:21 +0000