diff options
Diffstat (limited to 'src')
| -rwxr-xr-x | src/arch/isa_parser.py | 25 | ||||
| -rw-r--r-- | src/arch/mips/isa/formats/fp.isa | 6 | ||||
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 12 | ||||
| -rw-r--r-- | src/cpu/checker/cpu.hh | 25 | ||||
| -rw-r--r-- | src/cpu/exec_context.hh | 25 | ||||
| -rw-r--r-- | src/cpu/o3/alpha/dyn_inst.hh | 35 | ||||
| -rwxr-xr-x | src/cpu/o3/mips/dyn_inst.hh | 35 | ||||
| -rw-r--r-- | src/cpu/ozone/dyn_inst.hh | 25 | ||||
| -rw-r--r-- | src/cpu/simple/base.hh | 25 |
9 files changed, 117 insertions, 96 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 6504c7b32..a96622d4a 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1180,15 +1180,16 @@ class IntRegOperand(Operand): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read integer register as FP') if (self.size == self.dflt_size): - return '%s = xc->readIntReg(this, %d);\n' % \ + return '%s = xc->readIntRegOperand(this, %d);\n' % \ (self.base_name, self.src_reg_idx) elif (self.size > self.dflt_size): - int_reg_val = 'xc->readIntReg(this, %d)' % (self.src_reg_idx) + int_reg_val = 'xc->readIntRegOperand(this, %d)' % \ + (self.src_reg_idx) if (self.is_signed): int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val) return '%s = %s;\n' % (self.base_name, int_reg_val) else: - return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \ + return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \ (self.base_name, self.src_reg_idx, self.size-1) def makeWrite(self): @@ -1201,7 +1202,7 @@ class IntRegOperand(Operand): wb = ''' { %s final_val = %s; - xc->setIntReg(this, %d, final_val);\n + xc->setIntRegOperand(this, %d, final_val);\n if (traceData) { traceData->setData(final_val); } }''' % (self.dflt_ctype, final_val, self.dest_reg_idx) return wb @@ -1227,13 +1228,13 @@ class FloatRegOperand(Operand): bit_select = 0 width = 0; if (self.ctype == 'float'): - func = 'readFloatReg' + func = 'readFloatRegOperand' width = 32; elif (self.ctype == 'double'): - func = 'readFloatReg' + func = 'readFloatRegOperand' width = 64; else: - func = 'readFloatRegBits' + func = 'readFloatRegOperandBits' if (self.ctype == 'uint32_t'): width = 32; elif (self.ctype == 'uint64_t'): @@ -1259,18 +1260,18 @@ class FloatRegOperand(Operand): width = 0 if (self.ctype == 'float'): width = 32 - func = 'setFloatReg' + func = 'setFloatRegOperand' elif (self.ctype == 'double'): width = 64 - func = 'setFloatReg' + func = 'setFloatRegOperand' elif (self.ctype == 'uint32_t'): - func = 'setFloatRegBits' + func = 'setFloatRegOperandBits' width = 32 elif (self.ctype == 'uint64_t'): - func = 'setFloatRegBits' + func = 'setFloatRegOperandBits' width = 64 else: - func = 'setFloatRegBits' + func = 'setFloatRegOperandBits' final_ctype = 'uint%d_t' % self.dflt_size if (self.size != self.dflt_size and self.is_signed): final_val = 'sext<%d>(%s)' % (self.size, self.base_name) diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index cdb892b3f..153f3f949 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -99,7 +99,7 @@ output exec {{ int size = sizeof(src_op) * 8; for (int i = 0; i < inst->numSrcRegs(); i++) { - uint64_t src_bits = xc->readFloatRegBits(inst, 0, size); + uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size); if (isNan(&src_bits, size) ) { if (isSnan(&src_bits, size)) { @@ -113,7 +113,7 @@ output exec {{ mips_nan = src_bits; } - xc->setFloatRegBits(inst, 0, mips_nan, size); + xc->setFloatRegOperandBits(inst, 0, mips_nan, size); if (traceData) { traceData->setData(mips_nan); } return true; } @@ -139,7 +139,7 @@ output exec {{ } //Set value to QNAN - cpu->setFloatRegBits(inst, 0, mips_nan, size); + cpu->setFloatRegOperandBits(inst, 0, mips_nan, size); //Read FCSR from FloatRegFile uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 4a4555566..9037c96df 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -406,14 +406,15 @@ class BaseDynInst : public FastAlloc, public RefCounted double readDoubleResult() { return instResult.dbl; } /** Records an integer register being set to a value. */ - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { if (recordResult) instResult.integer = val; } /** Records an fp register being set to a value. */ - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) { if (recordResult) { if (width == 32) @@ -426,21 +427,22 @@ class BaseDynInst : public FastAlloc, public RefCounted } /** Records an fp register being set to a value. */ - void setFloatReg(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { if (recordResult) instResult.dbl = (double)val; } /** Records an fp register being set to an integer value. */ - void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width) + void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, + int width) { if (recordResult) instResult.integer = val; } /** Records an fp register being set to an integer value. */ - void setFloatRegBits(const StaticInst *si, int idx, uint64_t val) + void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) { if (recordResult) instResult.integer = val; diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 9be54529f..3e08193ee 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -216,42 +216,44 @@ class CheckerCPU : public BaseCPU // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntRegOperand(const StaticInst *si, int idx) { return thread->readIntReg(si->srcRegIdx(idx)); } - FloatReg readFloatReg(const StaticInst *si, int idx, int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatReg(reg_idx, width); } - FloatReg readFloatReg(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatReg(reg_idx); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatRegBits(reg_idx, width); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatRegBits(reg_idx); } - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { thread->setIntReg(si->destRegIdx(idx), val); result.integer = val; } - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatReg(reg_idx, val, width); @@ -265,22 +267,23 @@ class CheckerCPU : public BaseCPU }; } - void setFloatReg(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatReg(reg_idx, val); result.dbl = (double)val; } - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val, - int width) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatRegBits(reg_idx, val, width); result.integer = val; } - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatRegBits(reg_idx, val); diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 13f70fa79..edccd747f 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -48,39 +48,42 @@ class ExecContext { // to do). /** Reads an integer register. */ - uint64_t readIntReg(const StaticInst *si, int idx); + uint64_t readIntRegOperand(const StaticInst *si, int idx); /** Reads a floating point register of a specific width. */ - FloatReg readFloatReg(const StaticInst *si, int idx, int width); + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width); /** Reads a floating point register of single register width. */ - FloatReg readFloatReg(const StaticInst *si, int idx); + FloatReg readFloatRegOperand(const StaticInst *si, int idx); /** Reads a floating point register of a specific width in its * binary format, instead of by value. */ - FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width); + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width); /** Reads a floating point register in its binary format, instead * of by value. */ - FloatRegBits readFloatRegBits(const StaticInst *si, int idx); + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); /** Sets an integer register to a value. */ - void setIntReg(const StaticInst *si, int idx, uint64_t val); + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); /** Sets a floating point register of a specific width to a value. */ - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width); + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width); /** Sets a floating point register of single width to a value. */ - void setFloatReg(const StaticInst *si, int idx, FloatReg val); + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); /** Sets the bits of a floating point register of a specific width * to a binary value. */ - void setFloatRegBits(const StaticInst *si, int idx, - FloatRegBits val, int width); + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width); /** Sets the bits of a floating point register of single width * to a binary value. */ - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val); + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val); /** Reads the PC. */ uint64_t readPC(); diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 31df8ff78..49cc5a201 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -163,27 +163,28 @@ class AlphaDynInst : public BaseDynInst<Impl> // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntRegOperand(const StaticInst *si, int idx) { return this->cpu->readIntReg(_srcRegIdx[idx]); } - FloatReg readFloatReg(const StaticInst *si, int idx, int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) { return this->cpu->readFloatReg(_srcRegIdx[idx], width); } - FloatReg readFloatReg(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return this->cpu->readFloatReg(_srcRegIdx[idx]); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width) { return this->cpu->readFloatRegBits(_srcRegIdx[idx], width); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(_srcRegIdx[idx]); } @@ -191,35 +192,37 @@ class AlphaDynInst : public BaseDynInst<Impl> /** @todo: Make results into arrays so they can handle multiple dest * registers. */ - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { this->cpu->setIntReg(_destRegIdx[idx], val); - BaseDynInst<Impl>::setIntReg(si, idx, val); + BaseDynInst<Impl>::setIntRegOperand(si, idx, val); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) { this->cpu->setFloatReg(_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatReg(si, idx, val, width); + BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { this->cpu->setFloatReg(_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatReg(si, idx, val); + BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width) { this->cpu->setFloatRegBits(_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegBits(si, idx, val); + BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val) { this->cpu->setFloatRegBits(_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegBits(si, idx, val); + BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); } /** Returns the physical register index of the i'th destination diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh index 9e95b2bfb..833371e00 100755 --- a/src/cpu/o3/mips/dyn_inst.hh +++ b/src/cpu/o3/mips/dyn_inst.hh @@ -156,27 +156,28 @@ class MipsDynInst : public BaseDynInst<Impl> // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntRegOperand(const StaticInst *si, int idx) { return this->cpu->readIntReg(_srcRegIdx[idx]); } - FloatReg readFloatReg(const StaticInst *si, int idx, int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) { return this->cpu->readFloatReg(_srcRegIdx[idx], width); } - FloatReg readFloatReg(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return this->cpu->readFloatReg(_srcRegIdx[idx]); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width) { return this->cpu->readFloatRegBits(_srcRegIdx[idx], width); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(_srcRegIdx[idx]); } @@ -184,35 +185,37 @@ class MipsDynInst : public BaseDynInst<Impl> /** @todo: Make results into arrays so they can handle multiple dest * registers. */ - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { this->cpu->setIntReg(_destRegIdx[idx], val); - BaseDynInst<Impl>::setIntReg(si, idx, val); + BaseDynInst<Impl>::setIntRegOperand(si, idx, val); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) { this->cpu->setFloatReg(_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatReg(si, idx, val, width); + BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { this->cpu->setFloatReg(_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatReg(si, idx, val); + BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width) { this->cpu->setFloatRegBits(_destRegIdx[idx], val, width); - BaseDynInst<Impl>::setFloatRegBits(si, idx, val); + BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val) { this->cpu->setFloatRegBits(_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegBits(si, idx, val); + BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val); } /** Returns the physical register index of the i'th destination diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index 9445a5309..88f96b14b 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -146,12 +146,12 @@ class OzoneDynInst : public BaseDynInst<Impl> // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntRegOperand(const StaticInst *si, int idx) { return srcInsts[idx]->readIntResult(); } - FloatReg readFloatReg(const StaticInst *si, int idx, int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) { switch(width) { case 32: @@ -164,17 +164,18 @@ class OzoneDynInst : public BaseDynInst<Impl> } } - FloatReg readFloatReg(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return srcInsts[idx]->readFloatResult(); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width) { return srcInsts[idx]->readIntResult(); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return srcInsts[idx]->readIntResult(); } @@ -182,28 +183,30 @@ class OzoneDynInst : public BaseDynInst<Impl> /** @todo: Make results into arrays so they can handle multiple dest * registers. */ - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { BaseDynInst<Impl>::setIntReg(si, idx, val); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) { BaseDynInst<Impl>::setFloatReg(si, idx, val, width); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { BaseDynInst<Impl>::setFloatReg(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width) { BaseDynInst<Impl>::setFloatRegBits(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val) { BaseDynInst<Impl>::setFloatRegBits(si, idx, val); } diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index efb884325..c39bfa9cd 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -213,60 +213,63 @@ class BaseSimpleCPU : public BaseCPU // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntRegOperand(const StaticInst *si, int idx) { return thread->readIntReg(si->srcRegIdx(idx)); } - FloatReg readFloatReg(const StaticInst *si, int idx, int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatReg(reg_idx, width); } - FloatReg readFloatReg(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatReg(reg_idx); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatRegBits(reg_idx, width); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; return thread->readFloatRegBits(reg_idx); } - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { thread->setIntReg(si->destRegIdx(idx), val); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatReg(reg_idx, val, width); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatReg(reg_idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatRegBits(reg_idx, val, width); } - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val) { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; thread->setFloatRegBits(reg_idx, val); |