summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/insts/simd64/integer/exit_media_state.py5
-rw-r--r--src/arch/x86/isa/microasm.isa1
-rw-r--r--src/arch/x86/isa/microops/mediaop.isa6
-rw-r--r--src/arch/x86/isa/operands.isa1
5 files changed, 13 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 711be0bd5..294509df3 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -604,7 +604,7 @@
0x4: Inst::PCMPEQB(Pq,Qq);
0x5: Inst::PCMPEQW(Pq,Qq);
0x6: Inst::PCMPEQD(Pq,Qq);
- 0x7: WarnUnimpl::emms();
+ 0x7: Inst::EMMS();
}
// repe (0xF3)
0x4: decode OPCODE_OP_BOTTOM3 {
diff --git a/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py b/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py
index 3b2252a30..7f666ab7d 100644
--- a/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py
+++ b/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py
@@ -36,6 +36,9 @@
# Authors: Gabe Black
microcode = '''
-# EMMS
+def macroop EMMS {
+ emms
+};
+
# FEMMS
'''
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index b1fdfb54c..3ceaf9b28 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -212,6 +212,7 @@ let {{
assembler.symbols["fsw"] = readFpReg("FSW")
assembler.symbols["fcw"] = readFpReg("FCW")
+ assembler.symbols["ftw"] = readFpReg("FTW")
macroopDict = assembler.assemble(microcode)
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index 7178f1f52..20e09507e 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -1502,4 +1502,10 @@ let {{
else if(arg1 == arg2)
ccFlagBits = ccFlagBits | ZFBit;
'''
+
+ class Emms(MediaOp):
+ def __init__(self):
+ super(Emms, self).__init__('InstRegIndex(MISCREG_FTW)',
+ 'InstRegIndex(0)', 'InstRegIndex(0)', 0)
+ code = 'FTW = 0xFFFF;'
}};
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index bc6d1886c..b3607417b 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -162,6 +162,7 @@ def operands {{
# Registers related to the state of x87 floating point unit.
'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'),
+ 'FTW': controlReg('MISCREG_FTW', 68, ctype='uw'),
# The segment base as used by memory instructions.
'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),