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-rw-r--r--src/cpu/inorder/cpu.cc9
-rw-r--r--src/cpu/inorder/cpu.hh2
-rw-r--r--src/cpu/o3/cpu.hh4
-rw-r--r--src/cpu/simple/atomic.cc3
-rw-r--r--src/cpu/simple/timing.hh5
-rw-r--r--src/dev/dma_device.cc2
-rw-r--r--src/dev/io_device.cc2
-rw-r--r--src/mem/bridge.cc4
-rw-r--r--src/mem/cache/cache_impl.hh4
-rw-r--r--src/mem/coherent_bus.cc6
-rw-r--r--src/mem/noncoherent_bus.cc6
11 files changed, 25 insertions, 22 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 580389564..f67691d0a 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -82,8 +82,9 @@ using namespace std;
using namespace TheISA;
using namespace ThePipeline;
-InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
- CpuPort(_cacheUnit->name() + "-cache-port", _cacheUnit->cpu),
+InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit,
+ const std::string& name) :
+ CpuPort(_cacheUnit->name() + name, _cacheUnit->cpu),
cacheUnit(_cacheUnit)
{ }
@@ -230,8 +231,8 @@ InOrderCPU::InOrderCPU(Params *params)
stageWidth(params->stageWidth),
resPool(new ResourcePool(this, params)),
timeBuffer(2 , 2),
- dataPort(resPool->getDataUnit()),
- instPort(resPool->getInstUnit()),
+ dataPort(resPool->getDataUnit(), ".dcache_port"),
+ instPort(resPool->getInstUnit(), ".icache_port"),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
system(params->system),
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 615d0eb90..3103201dd 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -165,7 +165,7 @@ class InOrderCPU : public BaseCPU
public:
/** Default constructor. */
- CachePort(CacheUnit *_cacheUnit);
+ CachePort(CacheUnit *_cacheUnit, const std::string& name);
protected:
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 41128110b..b1fd12a2e 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -141,7 +141,7 @@ class FullO3CPU : public BaseO3CPU
public:
/** Default constructor. */
IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu)
- : CpuPort(_fetch->name() + "-iport", _cpu), fetch(_fetch)
+ : CpuPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
{ }
protected:
@@ -168,7 +168,7 @@ class FullO3CPU : public BaseO3CPU
public:
/** Default constructor. */
DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu)
- : CpuPort(_lsq->name() + "-dport", _cpu), lsq(_lsq)
+ : CpuPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq)
{ }
protected:
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 0886b276f..fc6724939 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -105,7 +105,8 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
: BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
simulate_data_stalls(p->simulate_data_stalls),
simulate_inst_stalls(p->simulate_inst_stalls),
- icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
+ icachePort(name() + ".icache_port", this),
+ dcachePort(name() + ".dcache_port", this),
fastmem(p->fastmem)
{
_status = Idle;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 95edea0b6..b6b78c5db 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -178,7 +178,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
IcachePort(TimingSimpleCPU *_cpu)
- : TimingCPUPort(_cpu->name() + "-iport", _cpu),
+ : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
tickEvent(_cpu)
{ }
@@ -206,7 +206,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
DcachePort(TimingSimpleCPU *_cpu)
- : TimingCPUPort(_cpu->name() + "-dport", _cpu), tickEvent(_cpu)
+ : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
+ tickEvent(_cpu)
{ }
protected:
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 401f910ac..a50dd933e 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -47,7 +47,7 @@
#include "sim/system.hh"
DmaPort::DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff)
- : MasterPort(dev->name() + "-dma", dev), device(dev), sys(s),
+ : MasterPort(dev->name() + ".dma", dev), device(dev), sys(s),
masterId(s->getMasterId(dev->name())),
pendingCount(0), actionInProgress(0), drainEvent(NULL),
backoffTime(0), minBackoffDelay(min_backoff),
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index b03afc5c6..30779cfb4 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -47,7 +47,7 @@
#include "sim/system.hh"
PioPort::PioPort(PioDevice *dev)
- : SimpleTimingPort(dev->name() + "-pio", dev), device(dev)
+ : SimpleTimingPort(dev->name() + ".pio", dev), device(dev)
{
}
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 3a5313e7b..e9dc68a03 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -79,9 +79,9 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string &_name,
Bridge::Bridge(Params *p)
: MemObject(p),
- slavePort(p->name + "-slave", this, masterPort, p->delay,
+ slavePort(p->name + ".slave", this, masterPort, p->delay,
p->nack_delay, p->resp_size, p->ranges),
- masterPort(p->name + "-master", this, slavePort, p->delay, p->req_size),
+ masterPort(p->name + ".master", this, slavePort, p->delay, p->req_size),
ackWrites(p->write_ack), _params(p)
{
if (ackWrites)
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index f7901261f..7b332e31d 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -72,9 +72,9 @@ Cache<TagStore>::Cache(const Params *p, TagStore *tags)
tempBlock = new BlkType();
tempBlock->data = new uint8_t[blkSize];
- cpuSidePort = new CpuSidePort(p->name + "-cpu_side_port", this,
+ cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this,
"CpuSidePort");
- memSidePort = new MemSidePort(p->name + "-mem_side_port", this,
+ memSidePort = new MemSidePort(p->name + ".mem_side", this,
"MemSidePort");
tags->setCache(this);
diff --git a/src/mem/coherent_bus.cc b/src/mem/coherent_bus.cc
index 5bcb2f14f..b0dedfaf4 100644
--- a/src/mem/coherent_bus.cc
+++ b/src/mem/coherent_bus.cc
@@ -62,7 +62,7 @@ CoherentBus::CoherentBus(const CoherentBusParams *p)
// vector ports, and the presence of the default port, the ports
// are enumerated starting from zero
for (int i = 0; i < p->port_master_connection_count; ++i) {
- std::string portName = csprintf("%s-p%d", name(), i);
+ std::string portName = csprintf("%s.master[%d]", name(), i);
MasterPort* bp = new CoherentBusMasterPort(portName, *this, i);
masterPorts.push_back(bp);
}
@@ -71,7 +71,7 @@ CoherentBus::CoherentBus(const CoherentBusParams *p)
// our corresponding master port
if (p->port_default_connection_count) {
defaultPortID = masterPorts.size();
- std::string portName = csprintf("%s-default", name());
+ std::string portName = name() + ".default";
MasterPort* bp = new CoherentBusMasterPort(portName, *this,
defaultPortID);
masterPorts.push_back(bp);
@@ -79,7 +79,7 @@ CoherentBus::CoherentBus(const CoherentBusParams *p)
// create the slave ports, once again starting at zero
for (int i = 0; i < p->port_slave_connection_count; ++i) {
- std::string portName = csprintf("%s-p%d", name(), i);
+ std::string portName = csprintf("%s.slave[%d]", name(), i);
SlavePort* bp = new CoherentBusSlavePort(portName, *this, i);
slavePorts.push_back(bp);
}
diff --git a/src/mem/noncoherent_bus.cc b/src/mem/noncoherent_bus.cc
index fb306bfeb..237e8726b 100644
--- a/src/mem/noncoherent_bus.cc
+++ b/src/mem/noncoherent_bus.cc
@@ -62,7 +62,7 @@ NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
// vector ports, and the presence of the default port, the ports
// are enumerated starting from zero
for (int i = 0; i < p->port_master_connection_count; ++i) {
- std::string portName = csprintf("%s-p%d", name(), i);
+ std::string portName = csprintf("%s.master[%d]", name(), i);
MasterPort* bp = new NoncoherentBusMasterPort(portName, *this, i);
masterPorts.push_back(bp);
}
@@ -71,7 +71,7 @@ NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
// our corresponding master port
if (p->port_default_connection_count) {
defaultPortID = masterPorts.size();
- std::string portName = csprintf("%s-default", name());
+ std::string portName = name() + ".default";
MasterPort* bp = new NoncoherentBusMasterPort(portName, *this,
defaultPortID);
masterPorts.push_back(bp);
@@ -79,7 +79,7 @@ NoncoherentBus::NoncoherentBus(const NoncoherentBusParams *p)
// create the slave ports, once again starting at zero
for (int i = 0; i < p->port_slave_connection_count; ++i) {
- std::string portName = csprintf("%s-p%d", name(), i);
+ std::string portName = csprintf("%s.slave[%d]", name(), i);
SlavePort* bp = new NoncoherentBusSlavePort(portName, *this, i);
slavePorts.push_back(bp);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-14 07:25:08 +0000