summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/cpu/exetrace.cc2
-rw-r--r--src/cpu/o3/rename_impl.hh2
-rw-r--r--src/sim/process.cc8
3 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index c568b1439..3e2b0f03e 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -652,7 +652,7 @@ Trace::InstRecord::dump()
predecoder.setTC(thread);
predecoder.moreBytes(m5Pc, 0, shared_data->instruction);
- assert(predecoder.extMachInstRead());
+ assert(predecoder.extMachInstReady());
StaticInstPtr legionInst =
StaticInst::decode(predecoder.getExtMachInst());
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 6b7fb1e08..431705e19 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -692,7 +692,7 @@ DefaultRename<Impl>::renameInsts(unsigned tid)
DPRINTF(Rename, "Blocking due to lack of free "
"physical registers to rename to.\n");
blockThisCycle = true;
-
+ insts_to_rename.push_front(inst);
++renameFullRegistersEvents;
break;
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 2b283c9d1..68239fa52 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -157,12 +157,12 @@ Process::registerThreadContext(ThreadContext *tc)
int myIndex = threadContexts.size();
threadContexts.push_back(tc);
- RemoteGDB *rgdb = new RemoteGDB(system, tc);
- GDBListener *gdbl = new GDBListener(rgdb, 7000 + myIndex);
- gdbl->listen();
+// RemoteGDB *rgdb = new RemoteGDB(system, tc);
+// GDBListener *gdbl = new GDBListener(rgdb, 7000 + myIndex);
+// gdbl->listen();
//gdbl->accept();
- remoteGDB.push_back(rgdb);
+// remoteGDB.push_back(rgdb);
// return CPU number to caller
return myIndex;