diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/riscv/insts/SConscript | 1 | ||||
| -rw-r--r-- | src/arch/riscv/insts/compressed.cc | 52 | ||||
| -rw-r--r-- | src/arch/riscv/insts/compressed.hh | 57 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/compressed.isa | 29 | ||||
| -rw-r--r-- | src/arch/riscv/isa/includes.isa | 1 |
5 files changed, 111 insertions, 29 deletions
diff --git a/src/arch/riscv/insts/SConscript b/src/arch/riscv/insts/SConscript index 439219c17..fcfb6273f 100644 --- a/src/arch/riscv/insts/SConscript +++ b/src/arch/riscv/insts/SConscript @@ -31,6 +31,7 @@ Import('*') if env['TARGET_ISA'] == 'riscv': Source('amo.cc') + Source('compressed.cc') Source('mem.cc') Source('standard.cc') Source('static_inst.cc')
\ No newline at end of file diff --git a/src/arch/riscv/insts/compressed.cc b/src/arch/riscv/insts/compressed.cc new file mode 100644 index 000000000..ff9eccc66 --- /dev/null +++ b/src/arch/riscv/insts/compressed.cc @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015 RISC-V Foundation + * Copyright (c) 2017 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#include "arch/riscv/insts/compressed.hh" + +#include <sstream> +#include <string> + +#include "arch/riscv/utility.hh" +#include "cpu/static_inst.hh" + +namespace RiscvISA +{ + +std::string +CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << + registerName(_srcRegIdx[0]); + return ss.str(); +} + +}
\ No newline at end of file diff --git a/src/arch/riscv/insts/compressed.hh b/src/arch/riscv/insts/compressed.hh new file mode 100644 index 000000000..021a4b4b7 --- /dev/null +++ b/src/arch/riscv/insts/compressed.hh @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015 RISC-V Foundation + * Copyright (c) 2017 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__ +#define __ARCH_RISCV_INSTS_COMPRESSED_HH__ + +#include <string> + +#include "arch/riscv/insts/static_inst.hh" +#include "cpu/static_inst.hh" + +namespace RiscvISA +{ + +/** + * Base class for compressed operations that work only on registers + */ +class CompRegOp : public RiscvStaticInst +{ + protected: + using RiscvStaticInst::RiscvStaticInst; + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; +}; + +} + +#endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
\ No newline at end of file diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa index 683795d89..3c47a906f 100644 --- a/src/arch/riscv/isa/formats/compressed.isa +++ b/src/arch/riscv/isa/formats/compressed.isa @@ -28,35 +28,6 @@ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: Alec Roelke - -output header {{ - /** - * Base class for compressed operations that work only on registers - */ - class CompRegOp : public RiscvStaticInst - { - protected: - /// Constructor - CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass) - {} - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string - CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << - registerName(_srcRegIdx[0]); - return ss.str(); - } -}}; - def format CROp(code, *opt_flags) {{ iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags) header_output = BasicDeclare.subst(iop) diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index f4662dacf..9f3d99fb5 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -43,6 +43,7 @@ output header {{ #include <vector> #include "arch/riscv/insts/amo.hh" +#include "arch/riscv/insts/compressed.hh" #include "arch/riscv/insts/mem.hh" #include "arch/riscv/insts/standard.hh" #include "arch/riscv/insts/static_inst.hh" |