diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/mem/ruby/profiler/CacheProfiler.cc | 11 | ||||
-rw-r--r-- | src/mem/ruby/profiler/CacheProfiler.hh | 7 | ||||
-rw-r--r-- | src/mem/ruby/profiler/Profiler.py | 5 | ||||
-rw-r--r-- | src/mem/ruby/system/Cache.py | 1 | ||||
-rw-r--r-- | src/mem/ruby/system/CacheMemory.cc | 3 |
5 files changed, 21 insertions, 6 deletions
diff --git a/src/mem/ruby/profiler/CacheProfiler.cc b/src/mem/ruby/profiler/CacheProfiler.cc index fad8d51b4..a01d68050 100644 --- a/src/mem/ruby/profiler/CacheProfiler.cc +++ b/src/mem/ruby/profiler/CacheProfiler.cc @@ -43,10 +43,10 @@ #include "mem/ruby/profiler/Profiler.hh" #include "mem/gems_common/Vector.hh" -CacheProfiler::CacheProfiler(string description) - : m_requestSize(-1) +CacheProfiler::CacheProfiler(const CacheProfilerParams* params) + : SimObject(params), m_requestSize(-1) { - m_description = description; + m_description = params->description; m_requestTypeVec_ptr = new Vector<int>; m_requestTypeVec_ptr->setSize(int(CacheRequestType_NUM)); @@ -141,3 +141,8 @@ void CacheProfiler::addStatSample(CacheRequestType requestType, AccessModeType t } } +CacheProfiler * +CacheProfilerParams::create() +{ + return new CacheProfiler(this); +} diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh index 6d7c163cb..eeed1153b 100644 --- a/src/mem/ruby/profiler/CacheProfiler.hh +++ b/src/mem/ruby/profiler/CacheProfiler.hh @@ -46,12 +46,15 @@ #include "mem/protocol/PrefetchBit.hh" #include "mem/protocol/CacheRequestType.hh" +#include "params/CacheProfiler.hh" + template <class TYPE> class Vector; -class CacheProfiler { +class CacheProfiler : public SimObject { public: // Constructors - CacheProfiler(string description); + typedef CacheProfilerParams Params; + CacheProfiler(const Params *); // Destructor ~CacheProfiler(); diff --git a/src/mem/ruby/profiler/Profiler.py b/src/mem/ruby/profiler/Profiler.py index 7923f28f1..7585d4978 100644 --- a/src/mem/ruby/profiler/Profiler.py +++ b/src/mem/ruby/profiler/Profiler.py @@ -6,3 +6,8 @@ class RubyProfiler(SimObject): cxx_class = 'Profiler' hot_lines = Param.Bool(False, "") all_instructions = Param.Bool(False, "") + +class CacheProfiler(SimObject): + type = 'CacheProfiler' + cxx_class = 'CacheProfiler' + description = Param.String("") diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py index 209d6f6e2..5cec5d6e6 100644 --- a/src/mem/ruby/system/Cache.py +++ b/src/mem/ruby/system/Cache.py @@ -9,3 +9,4 @@ class RubyCache(SimObject): latency = Param.Int(""); assoc = Param.Int(""); replacement_policy = Param.String("PSEUDO_LRU", ""); + cache_profiler = Param.CacheProfiler(""); diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index 11dd8ca96..60783c433 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -57,6 +57,7 @@ CacheMemory::CacheMemory(const Params *p) m_latency = p->latency; m_cache_assoc = p->assoc; m_policy = p->replacement_policy; + m_profiler_ptr = p->cache_profiler; } @@ -360,7 +361,7 @@ void CacheMemory::setMRU(const Address& address) void CacheMemory::profileMiss(const CacheMsg & msg) { m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(), - msg.getSize(), msg.getPrefetch()); + msg.getSize(), msg.getPrefetch()); } void CacheMemory::recordCacheContents(CacheRecorder& tr) const |