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-rw-r--r--src/arch/x86/floatregs.hh2
-rw-r--r--src/arch/x86/insts/static_inst.cc11
-rw-r--r--src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py4
-rw-r--r--src/arch/x86/isa/microasm.isa2
-rw-r--r--src/arch/x86/isa_traits.hh4
-rw-r--r--src/arch/x86/regfile.cc2
6 files changed, 16 insertions, 9 deletions
diff --git a/src/arch/x86/floatregs.hh b/src/arch/x86/floatregs.hh
index 30846ec00..dc9867c42 100644
--- a/src/arch/x86/floatregs.hh
+++ b/src/arch/x86/floatregs.hh
@@ -166,7 +166,7 @@ namespace X86ISA
static inline FloatRegIndex
FLOATREG_STACK(int index, int top)
{
- return (FloatRegIndex)(NUM_FLOATREGS + ((top - index + 8) % 8));
+ return (FloatRegIndex)(NUM_FLOATREGS + ((top + index + 8) % 8));
}
};
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index 4f6ec5390..510295157 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -198,13 +198,18 @@ namespace X86ISA
return;
}
fpindex -= NumMMXRegs;
- if(fpindex < NumXMMRegs) {
+ if(fpindex < NumXMMRegs * 2) {
ccprintf(os, "%%xmm%d_%s", fpindex / 2,
(fpindex % 2) ? "high": "low");
return;
}
- fpindex -= NumXMMRegs;
- ccprintf(os, "%%ufp%d", fpindex);
+ fpindex -= NumXMMRegs * 2;
+ if(fpindex < NumMicroFpRegs) {
+ ccprintf(os, "%%ufp%d", fpindex);
+ return;
+ }
+ fpindex -= NumMicroFpRegs;
+ ccprintf(os, "%%st(%d)", fpindex);
} else {
switch (reg - Ctrl_Base_DepTag) {
default:
diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
index 6d56ac3bd..2a4c3f0ed 100644
--- a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
+++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py
@@ -56,13 +56,13 @@
microcode = '''
def macroop FLD_M {
ldfp ufp1, seg, sib, disp
- movfp st(1), ufp1, spm=-1
+ movfp st(-1), ufp1, spm=-1
};
def macroop FLD_P {
rdip t7
ldfp ufp1, seg, riprel, disp
- movfp st(1), ufp1, spm=-1
+ movfp st(-1), ufp1, spm=-1
};
def macroop FST_M {
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index e961cc63c..c8bc36b69 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -137,7 +137,7 @@ let {{
assembler.symbols["label"] = labeler
def stack_index(index):
- return "(NUM_FLOATREGS + (%s))" % index
+ return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index
assembler.symbols["st"] = stack_index
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index e69813836..6e8cac94a 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -90,7 +90,9 @@ namespace X86ISA
//mmx/x87 registers
8 +
//xmm registers
- 16 +
+ 16 * 2 +
+ //The microcode fp registers
+ 8 +
//The indices that are mapped over the fp stack
8
};
diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc
index 889f2f5cd..c27ab08ba 100644
--- a/src/arch/x86/regfile.cc
+++ b/src/arch/x86/regfile.cc
@@ -221,7 +221,7 @@ int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg)
{
- if (reg > NUM_FLOATREGS) {
+ if (reg >= NUM_FLOATREGS) {
int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP);
reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
}