diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 474e4fab0..13eb70b39 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -53,7 +53,7 @@ let {{ let {{ microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 'MicroMemOp', - {'memacc_code': 'Ra = Mem;', + {'memacc_code': 'IWRa = Mem;', 'ea_code': 'EA = Rb + (up ? imm : -imm);', 'predicate_test': predicateTest}, ['IsMicroop']) diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index c507864b6..c845acc94 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -129,6 +129,8 @@ def operands {{ #Register fields for microops 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), + 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, + maybePCRead, maybeIWPCWrite), 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), |