diff options
Diffstat (limited to 'src')
225 files changed, 8474 insertions, 1767 deletions
diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py new file mode 100644 index 000000000..a19aeb763 --- /dev/null +++ b/src/arch/alpha/AlphaSystem.py @@ -0,0 +1,52 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from System import System + +class AlphaSystem(System): + type = 'AlphaSystem' + console = Param.String("file that contains the console code") + pal = Param.String("file that contains palcode") + system_type = Param.UInt64("Type of system we are emulating") + system_rev = Param.UInt64("Revision of system we are emulating") + +class LinuxAlphaSystem(AlphaSystem): + type = 'LinuxAlphaSystem' + system_type = 34 + system_rev = 1 << 10 + +class FreebsdAlphaSystem(AlphaSystem): + type = 'FreebsdAlphaSystem' + system_type = 34 + system_rev = 1 << 10 + +class Tru64AlphaSystem(AlphaSystem): + type = 'Tru64AlphaSystem' + system_type = 12 + system_rev = 2<<1 diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py new file mode 100644 index 000000000..559516725 --- /dev/null +++ b/src/arch/alpha/AlphaTLB.py @@ -0,0 +1,42 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +class AlphaTLB(SimObject): + type = 'AlphaTLB' + abstract = True + size = Param.Int("TLB size") + +class AlphaDTB(AlphaTLB): + type = 'AlphaDTB' + size = 64 + +class AlphaITB(AlphaTLB): + type = 'AlphaITB' + size = 48 diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 61611e9f6..2d59180c4 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -40,6 +40,9 @@ if env['TARGET_ISA'] == 'alpha': Source('remote_gdb.cc') if env['FULL_SYSTEM']: + SimObject('AlphaSystem.py') + SimObject('AlphaTLB.py') + Source('arguments.cc') Source('ev5.cc') Source('idle_event.cc') diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh index 650f2bfa2..0407ce99b 100644 --- a/src/arch/alpha/predecoder.hh +++ b/src/arch/alpha/predecoder.hh @@ -69,9 +69,9 @@ namespace AlphaISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst) { - fetchPC = pc; + fetchPC = _fetchPC; assert(off == 0); ext_inst = inst; #if FULL_SYSTEM @@ -80,13 +80,6 @@ namespace AlphaISA #endif } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(fetchPC + sizeof(machInst), 0, machInst); - } - bool needMoreBytes() { return true; diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index a68e5218e..ea5db36f4 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -284,7 +284,7 @@ RemoteGDB::setSingleStep() // User was stopped at pc, e.g. the instruction at pc was not // executed. MachInst inst = read<MachInst>(pc); - StaticInstPtr si(inst); + StaticInstPtr si(inst, pc); if (si->hasBranchTarget(pc, context, bpc)) { // Don't bother setting a breakpoint on the taken branch if it // is the same as the next pc diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 2dfff8c5f..714bca22a 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -292,6 +292,10 @@ ITB::regStats() Fault ITB::translate(RequestPtr &req, ThreadContext *tc) const { + //If this is a pal pc, then set PHYSICAL + if(FULL_SYSTEM && PcPAL(req->getPC())) + req->setFlags(req->getFlags() | PHYSICAL); + if (PcPAL(req->getPC())) { // strip off PAL PC marker (lsb is 1) req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 4c8d0706d..7edb9f3d7 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -40,8 +40,8 @@ from types import * # of 'build' in the current tree. sys.path[0:0] = [os.environ['M5_PLY']] -import lex -import yacc +from ply import lex +from ply import yacc ##################################################################### # @@ -194,7 +194,7 @@ def t_error(t): t.skip(1) # Build the lexer -lex.lex() +lexer = lex.lex() ##################################################################### # @@ -729,7 +729,7 @@ def p_error(t): # END OF GRAMMAR RULES # # Now build the parser. -yacc.yacc() +parser = yacc.yacc() ##################################################################### @@ -1881,7 +1881,8 @@ def parse_isa_desc(isa_desc_file, output_dir): fileNameStack.push((isa_desc_file, 0)) # Parse it. - (isa_name, namespace, global_code, namespace_code) = yacc.parse(isa_desc) + (isa_name, namespace, global_code, namespace_code) = \ + parser.parse(isa_desc, lexer=lexer) # grab the last three path components of isa_desc_file to put in # the output diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py new file mode 100644 index 000000000..a8a63e1f8 --- /dev/null +++ b/src/arch/micro_asm.py @@ -0,0 +1,491 @@ +# Copyright (c) 2003-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +import os +import sys +import re +import string +import traceback +# get type names +from types import * + +# Prepend the directory where the PLY lex & yacc modules are found +# to the search path. +sys.path[0:0] = [os.environ['M5_PLY']] + +from ply import lex +from ply import yacc + +########################################################################## +# +# Base classes for use outside of the assembler +# +########################################################################## + +class Micro_Container(object): + def __init__(self, name): + self.microops = [] + self.name = name + self.directives = {} + self.micro_classes = {} + self.labels = {} + + def add_microop(self, microop): + self.microops.append(microop) + + def __str__(self): + string = "%s:\n" % self.name + for microop in self.microops: + string += " %s\n" % microop + return string + +class Combinational_Macroop(Micro_Container): + pass + +class Rom_Macroop(object): + def __init__(self, name, target): + self.name = name + self.target = target + + def __str__(self): + return "%s: %s\n" % (self.name, self.target) + +class Rom(Micro_Container): + def __init__(self, name): + super(Rom, self).__init__(name) + self.externs = {} + +########################################################################## +# +# Support classes +# +########################################################################## + +class Label(object): + def __init__(self): + self.extern = False + self.name = "" + +class Block(object): + def __init__(self): + self.statements = [] + +class Statement(object): + def __init__(self): + self.is_microop = False + self.is_directive = False + self.params = "" + +class Microop(Statement): + def __init__(self): + super(Microop, self).__init__() + self.mnemonic = "" + self.labels = [] + self.is_microop = True + +class Directive(Statement): + def __init__(self): + super(Directive, self).__init__() + self.name = "" + self.is_directive = True + +########################################################################## +# +# Functions that handle common tasks +# +########################################################################## + +def print_error(message): + print + print "*** %s" % message + print + +def handle_statement(parser, container, statement): + if statement.is_microop: + try: + microop = eval('parser.microops[statement.mnemonic](%s)' % + statement.params) + except: + print_error("Error creating microop object.") + raise + try: + for label in statement.labels: + container.labels[label.name] = microop + if label.extern: + container.externs[label.name] = microop + container.add_microop(microop) + except: + print_error("Error adding microop.") + raise + elif statement.is_directive: + try: + eval('container.directives[statement.name](%s)' % statement.params) + except: + print_error("Error executing directive.") + print container.directives + raise + else: + raise Exception, "Didn't recognize the type of statement", statement + +########################################################################## +# +# Lexer specification +# +########################################################################## + +# Error handler. Just call exit. Output formatted to work under +# Emacs compile-mode. Optional 'print_traceback' arg, if set to True, +# prints a Python stack backtrace too (can be handy when trying to +# debug the parser itself). +def error(lineno, string, print_traceback = False): + # Print a Python stack backtrace if requested. + if (print_traceback): + traceback.print_exc() + if lineno != 0: + line_str = "%d:" % lineno + else: + line_str = "" + sys.exit("%s %s" % (line_str, string)) + +reserved = ('DEF', 'MACROOP', 'ROM', 'EXTERN') + +tokens = reserved + ( + # identifier + 'ID', + # arguments for microops and directives + 'PARAMS', + + 'LPAREN', 'RPAREN', + 'LBRACE', 'RBRACE', + 'COLON', 'SEMI', 'DOT', + 'NEWLINE' + ) + +# New lines are ignored at the top level, but they end statements in the +# assembler +states = ( + ('asm', 'exclusive'), + ('params', 'exclusive'), +) + +reserved_map = { } +for r in reserved: + reserved_map[r.lower()] = r + +# Ignore comments +def t_ANY_COMMENT(t): + r'\#[^\n]*(?=\n)' + +def t_ANY_MULTILINECOMMENT(t): + r'/\*([^/]|((?<!\*)/))*\*/' + +# A colon marks the end of a label. It should follow an ID which will +# put the lexer in the "params" state. Seeing the colon will put it back +# in the "asm" state since it knows it saw a label and not a mnemonic. +def t_params_COLON(t): + r':' + t.lexer.begin('asm') + return t + +# An "ID" in the micro assembler is either a label, directive, or mnemonic +# If it's either a directive or a mnemonic, it will be optionally followed by +# parameters. If it's a label, the following colon will make the lexer stop +# looking for parameters. +def t_asm_ID(t): + r'[A-Za-z_]\w*' + t.type = reserved_map.get(t.value, 'ID') + t.lexer.begin('params') + return t + +# If there is a label and you're -not- in the assember (which would be caught +# above), don't start looking for parameters. +def t_ANY_ID(t): + r'[A-Za-z_]\w*' + t.type = reserved_map.get(t.value, 'ID') + return t + +# Parameters are a string of text which don't contain an unescaped statement +# statement terminator, ie a newline or semi colon. +def t_params_PARAMS(t): + r'([^\n;\\]|(\\[\n;\\]))+' + t.lineno += t.value.count('\n') + unescapeParamsRE = re.compile(r'(\\[\n;\\])') + def unescapeParams(mo): + val = mo.group(0) + print "About to sub %s for %s" % (val[1], val) + return val[1] + print "Looking for matches in %s" % t.value + t.value = unescapeParamsRE.sub(unescapeParams, t.value) + t.lexer.begin('asm') + return t + +# Braces enter and exit micro assembly +def t_INITIAL_LBRACE(t): + r'\{' + t.lexer.begin('asm') + return t + +def t_asm_RBRACE(t): + r'\}' + t.lexer.begin('INITIAL') + return t + +# At the top level, keep track of newlines only for line counting. +def t_INITIAL_NEWLINE(t): + r'\n+' + t.lineno += t.value.count('\n') + +# In the micro assembler, do line counting but also return a token. The +# token is needed by the parser to detect the end of a statement. +def t_asm_NEWLINE(t): + r'\n+' + t.lineno += t.value.count('\n') + return t + +# A newline or semi colon when looking for params signals that the statement +# is over and the lexer should go back to looking for regular assembly. +def t_params_NEWLINE(t): + r'\n+' + t.lineno += t.value.count('\n') + t.lexer.begin('asm') + return t + +def t_params_SEMI(t): + r';' + t.lexer.begin('asm') + return t + +# Basic regular expressions to pick out simple tokens +t_ANY_LPAREN = r'\(' +t_ANY_RPAREN = r'\)' +t_ANY_SEMI = r';' +t_ANY_DOT = r'\.' + +t_ANY_ignore = ' \t\x0c' + +def t_ANY_error(t): + error(t.lineno, "illegal character '%s'" % t.value[0]) + t.skip(1) + +########################################################################## +# +# Parser specification +# +########################################################################## + +# Start symbol for a file which may have more than one macroop or rom +# specification. +def p_file(t): + 'file : opt_rom_or_macros' + +def p_opt_rom_or_macros_0(t): + 'opt_rom_or_macros : ' + +def p_opt_rom_or_macros_1(t): + 'opt_rom_or_macros : rom_or_macros' + +def p_rom_or_macros_0(t): + 'rom_or_macros : rom_or_macro' + +def p_rom_or_macros_1(t): + 'rom_or_macros : rom_or_macros rom_or_macro' + +def p_rom_or_macro_0(t): + '''rom_or_macro : rom_block + | macroop_def''' + +# Defines a section of microcode that should go in the current ROM +def p_rom_block(t): + 'rom_block : DEF ROM block SEMI' + if not t.parser.rom: + print_error("Rom block found, but no Rom object specified.") + raise TypeError, "Rom block found, but no Rom object was specified." + for statement in t[3].statements: + handle_statement(t.parser, t.parser.rom, statement) + t[0] = t.parser.rom + +# Defines a macroop that jumps to an external label in the ROM +def p_macroop_def_0(t): + 'macroop_def : DEF MACROOP ID LPAREN ID RPAREN SEMI' + if not t.parser.rom_macroop_type: + print_error("ROM based macroop found, but no ROM macroop class was specified.") + raise TypeError, "ROM based macroop found, but no ROM macroop class was specified." + macroop = t.parser.rom_macroop_type(t[3], t[5]) + t.parser.macroops[t[3]] = macroop + + +# Defines a macroop that is combinationally generated +def p_macroop_def_1(t): + 'macroop_def : DEF MACROOP ID block SEMI' + try: + curop = t.parser.macro_type(t[3]) + except TypeError: + print_error("Error creating macroop object.") + raise + for statement in t[4].statements: + handle_statement(t.parser, curop, statement) + t.parser.macroops[t[3]] = curop + +# A block of statements +def p_block(t): + 'block : LBRACE statements RBRACE' + block = Block() + block.statements = t[2] + t[0] = block + +def p_statements_0(t): + 'statements : statement' + if t[1]: + t[0] = [t[1]] + else: + t[0] = [] + +def p_statements_1(t): + 'statements : statements statement' + if t[2]: + t[1].append(t[2]) + t[0] = t[1] + +def p_statement(t): + 'statement : content_of_statement end_of_statement' + t[0] = t[1] + +# A statement can be a microop or an assembler directive +def p_content_of_statement_0(t): + '''content_of_statement : microop + | directive''' + t[0] = t[1] + +# Ignore empty statements +def p_content_of_statement_1(t): + 'content_of_statement : ' + pass + +# Statements are ended by newlines or a semi colon +def p_end_of_statement(t): + '''end_of_statement : NEWLINE + | SEMI''' + pass + +# Different flavors of microop to avoid shift/reduce errors +def p_microop_0(t): + 'microop : labels ID' + microop = Microop() + microop.labels = t[1] + microop.mnemonic = t[2] + t[0] = microop + +def p_microop_1(t): + 'microop : ID' + microop = Microop() + microop.mnemonic = t[1] + t[0] = microop + +def p_microop_2(t): + 'microop : labels ID PARAMS' + microop = Microop() + microop.labels = t[1] + microop.mnemonic = t[2] + microop.params = t[3] + t[0] = microop + +def p_microop_3(t): + 'microop : ID PARAMS' + microop = Microop() + microop.mnemonic = t[1] + microop.params = t[2] + t[0] = microop + +# Labels in the microcode +def p_labels_0(t): + 'labels : label' + t[0] = [t[1]] + +def p_labels_1(t): + 'labels : labels label' + t[1].append(t[2]) + t[0] = t[1] + +def p_label_0(t): + 'label : ID COLON' + label = Label() + label.is_extern = False + label.text = t[1] + t[0] = label + +def p_label_1(t): + 'label : EXTERN ID COLON' + label = Label() + label.is_extern = True + label.text = t[2] + t[0] = label + +# Directives for the macroop +def p_directive_0(t): + 'directive : DOT ID' + directive = Directive() + directive.name = t[2] + t[0] = directive + +def p_directive_1(t): + 'directive : DOT ID PARAMS' + directive = Directive() + directive.name = t[2] + directive.params = t[3] + t[0] = directive + +# Parse error handler. Note that the argument here is the offending +# *token*, not a grammar symbol (hence the need to use t.value) +def p_error(t): + if t: + error(t.lineno, "syntax error at '%s'" % t.value) + else: + error(0, "unknown syntax error", True) + +class MicroAssembler(object): + + def __init__(self, macro_type, microops, + rom = None, rom_macroop_type = None): + self.lexer = lex.lex() + self.parser = yacc.yacc() + self.parser.macro_type = macro_type + self.parser.macroops = {} + self.parser.microops = microops + self.parser.rom = rom + self.parser.rom_macroop_type = rom_macroop_type + + def assemble(self, asm): + self.parser.parse(asm, lexer=self.lexer) + # Begin debug printing + for macroop in self.parser.macroops.values(): + print macroop + print self.parser.rom + # End debug printing + macroops = self.parser.macroops + self.parser.macroops = {} + return macroops diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py new file mode 100755 index 000000000..b074ecb58 --- /dev/null +++ b/src/arch/micro_asm_test.py @@ -0,0 +1,107 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop, Rom + +class Bah(object): + def __init__(self): + self.mnemonic = "bah" + +class Bah_Tweaked(object): + def __init__(self): + self.mnemonic = "bah_tweaked" + +class Hoop(object): + def __init__(self, first_param, second_param): + self.mnemonic = "hoop_%s_%s" % (first_param, second_param) + def __str__(self): + return "%s" % self.mnemonic + +class Dah(object): + def __init__(self): + self.mnemonic = "dah" + +microops = { + "bah": Bah, + "hoop": Hoop, + "dah": Dah +} + +class TestMacroop(Combinational_Macroop): + def tweak(self): + microops["bah"] = Bah_Tweaked + def untweak(self): + microops["bah"] = Bah + def print_debug(self, message): + print message + + def __init__(self, name): + super(TestMacroop, self).__init__(name) + self.directives = { + "tweak": self.tweak, + "untweak": self.untweak, + "print": self.print_debug + } + +assembler = MicroAssembler(TestMacroop, microops, Rom('main ROM'), Rom_Macroop) + +testAssembly = ''' +# Single line comment + +def rom { + goo: bah + extern la: hoop 4*8, "a" +}; /* multiline comment on one line */ + +/* multi line comment across lines + to make sure they work */ + +def macroop squishy { + .tweak + bah + .untweak + .print "In the midst" + bah + dah # single line comment after something + .tweak +}; + +#Extending the rom... +def rom +{ + #Here's more stuff for the rom + bah +}; + +def macroop squashy { + bah +}; + +def macroop jumper (bar); +''' +assembler.assemble(testAssembly) diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh index a25cce8a7..90f768d73 100644 --- a/src/arch/mips/predecoder.hh +++ b/src/arch/mips/predecoder.hh @@ -66,19 +66,12 @@ namespace MipsISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr currPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) { assert(off == 0); emi = inst; } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(0, 0, machInst); - } - bool needMoreBytes() { return true; diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index e342c79cf..c9dbb8cf2 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -41,6 +41,9 @@ if env['TARGET_ISA'] == 'sparc': Source('remote_gdb.cc') if env['FULL_SYSTEM']: + SimObject('SparcSystem.py') + SimObject('SparcTLB.py') + Source('arguments.cc') Source('pagetable.cc') Source('stacktrace.cc') diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py new file mode 100644 index 000000000..2e65f640d --- /dev/null +++ b/src/arch/sparc/SparcSystem.py @@ -0,0 +1,74 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * + +from PhysicalMemory import * +from System import System + +class SparcSystem(System): + type = 'SparcSystem' + _rom_base = 0xfff0000000 + _nvram_base = 0x1f11000000 + _hypervisor_desc_base = 0x1f12080000 + _partition_desc_base = 0x1f12000000 + # ROM for OBP/Reset/Hypervisor + rom = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_rom_base, size='8MB')), + "Memory to hold the ROM data") + # nvram + nvram = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_nvram_base, size='8kB')), + "Memory to hold the nvram data") + # hypervisor description + hypervisor_desc = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_hypervisor_desc_base, size='8kB')), + "Memory to hold the hypervisor description") + # partition description + partition_desc = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_partition_desc_base, size='8kB')), + "Memory to hold the partition description") + + reset_addr = Param.Addr(_rom_base, "Address to load ROM at") + hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base, + "Address to load hypervisor at") + openboot_addr = Param.Addr(Addr('512kB') + _rom_base, + "Address to load openboot at") + nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram") + hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base, + "Address for the hypervisor description") + partition_desc_addr = Param.Addr(_partition_desc_base, + "Address for the partition description") + + reset_bin = Param.String("file that contains the reset code") + hypervisor_bin = Param.String("file that contains the hypervisor code") + openboot_bin = Param.String("file that contains the openboot code") + nvram_bin = Param.String("file that contains the contents of nvram") + hypervisor_desc_bin = Param.String("file that contains the hypervisor description") + partition_desc_bin = Param.String("file that contains the partition description") + diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py new file mode 100644 index 000000000..30e5ebb08 --- /dev/null +++ b/src/arch/sparc/SparcTLB.py @@ -0,0 +1,42 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +from m5.SimObject import SimObject +from m5.params import * +class SparcTLB(SimObject): + type = 'SparcTLB' + abstract = True + size = Param.Int("TLB size") + +class SparcDTB(SparcTLB): + type = 'SparcDTB' + size = 64 + +class SparcITB(SparcTLB): + type = 'SparcITB' + size = 64 diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index ea74ef179..5d36e5e41 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -248,14 +248,14 @@ def template BlockMemConstructor {{ : %(base_class)s("%(mnemonic)s", machInst) { %(constructor)s; - microOps[0] = new %(class_name)s_0(machInst); - microOps[1] = new %(class_name)s_1(machInst); - microOps[2] = new %(class_name)s_2(machInst); - microOps[3] = new %(class_name)s_3(machInst); - microOps[4] = new %(class_name)s_4(machInst); - microOps[5] = new %(class_name)s_5(machInst); - microOps[6] = new %(class_name)s_6(machInst); - microOps[7] = new %(class_name)s_7(machInst); + microops[0] = new %(class_name)s_0(machInst); + microops[1] = new %(class_name)s_1(machInst); + microops[2] = new %(class_name)s_2(machInst); + microops[3] = new %(class_name)s_3(machInst); + microops[4] = new %(class_name)s_4(machInst); + microops[5] = new %(class_name)s_5(machInst); + microops[6] = new %(class_name)s_6(machInst); + microops[7] = new %(class_name)s_7(machInst); } }}; @@ -289,9 +289,9 @@ let {{ for microPc in range(8): flag_code = '' if (microPc == 7): - flag_code = "flags[IsLastMicroOp] = true;" + flag_code = "flags[IsLastMicroop] = true;" elif (microPc == 0): - flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa index da0f97d1b..c1d0c4f36 100644 --- a/src/arch/sparc/isa/formats/micro.isa +++ b/src/arch/sparc/isa/formats/micro.isa @@ -58,33 +58,33 @@ output header {{ class SparcMacroInst : public SparcStaticInst { protected: - const uint32_t numMicroOps; + const uint32_t numMicroops; //Constructor. SparcMacroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, uint32_t _numMicroOps) + OpClass __opClass, uint32_t _numMicroops) : SparcStaticInst(mnem, _machInst, __opClass), - numMicroOps(_numMicroOps) + numMicroops(_numMicroops) { - assert(numMicroOps); - microOps = new StaticInstPtr[numMicroOps]; - flags[IsMacroOp] = true; + assert(numMicroops); + microops = new StaticInstPtr[numMicroops]; + flags[IsMacroop] = true; } ~SparcMacroInst() { - delete [] microOps; + delete [] microops; } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - StaticInstPtr * microOps; + StaticInstPtr * microops; - StaticInstPtr fetchMicroOp(MicroPC microPC) + StaticInstPtr fetchMicroop(MicroPC microPC) { - assert(microPC < numMicroOps); - return microOps[microPC]; + assert(microPC < numMicroops); + return microops[microPC]; } %(MacroExecute)s @@ -100,7 +100,7 @@ output header {{ ExtMachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) { - flags[IsMicroOp] = true; + flags[IsMicroop] = true; } }; diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index f511ef454..0300694cc 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -142,27 +142,38 @@ void MiscRegFile::clear() MiscReg MiscRegFile::readRegNoEffect(int miscReg) { - switch (miscReg) { - case MISCREG_TLB_DATA: - /* Package up all the data for the tlb: - * 6666555555555544444444443333333333222222222211111111110000000000 - * 3210987654321098765432109876543210987654321098765432109876543210 - * secContext | priContext | |tl|partid| |||||^hpriv - * ||||^red - * |||^priv - * ||^am - * |^lsuim - * ^lsudm - */ - return bits((uint64_t)hpstate,2,2) | - bits((uint64_t)hpstate,5,5) << 1 | - bits((uint64_t)pstate,3,2) << 2 | - bits((uint64_t)lsuCtrlReg,3,2) << 4 | - bits((uint64_t)partId,7,0) << 8 | - bits((uint64_t)tl,2,0) << 16 | - (uint64_t)priContext << 32 | - (uint64_t)secContext << 48; + // The three miscRegs are moved up from the switch statement + // due to more frequent calls. + + if (miscReg == MISCREG_GL) + return gl; + if (miscReg == MISCREG_CWP) + return cwp; + if (miscReg == MISCREG_TLB_DATA) { + /* Package up all the data for the tlb: + * 6666555555555544444444443333333333222222222211111111110000000000 + * 3210987654321098765432109876543210987654321098765432109876543210 + * secContext | priContext | |tl|partid| |||||^hpriv + * ||||^red + * |||^priv + * ||^am + * |^lsuim + * ^lsudm + */ + return bits((uint64_t)hpstate,2,2) | + bits((uint64_t)hpstate,5,5) << 1 | + bits((uint64_t)pstate,3,2) << 2 | + bits((uint64_t)lsuCtrlReg,3,2) << 4 | + bits((uint64_t)partId,7,0) << 8 | + bits((uint64_t)tl,2,0) << 16 | + (uint64_t)priContext << 32 | + (uint64_t)secContext << 48; + } + + switch (miscReg) { + //case MISCREG_TLB_DATA: + // [original contents see above] //case MISCREG_Y: // return y; //case MISCREG_CCR: @@ -207,8 +218,9 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) return tl; case MISCREG_PIL: return pil; - case MISCREG_CWP: - return cwp; + //CWP, GL moved + //case MISCREG_CWP: + // return cwp; //case MISCREG_CANSAVE: // return cansave; //case MISCREG_CANRESTORE: @@ -219,8 +231,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) // return otherwin; //case MISCREG_WSTATE: // return wstate; - case MISCREG_GL: - return gl; + //case MISCREG_GL: + // return gl; /** Hyper privileged registers */ case MISCREG_HPSTATE: diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 4a8c9dc4a..38d8fd1a2 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -67,7 +67,7 @@ namespace SparcISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr currPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) { assert(off == 0); @@ -85,13 +85,6 @@ namespace SparcISA << (sizeof(MachInst) * 8)); } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(0, 0, machInst); - } - bool needMoreBytes() { return true; diff --git a/src/arch/x86/intregfile.cc b/src/arch/x86/intregfile.cc index 15e86d88b..9c9ea134e 100644 --- a/src/arch/x86/intregfile.cc +++ b/src/arch/x86/intregfile.cc @@ -87,6 +87,7 @@ #include "arch/x86/intregfile.hh" #include "base/misc.hh" +#include "base/trace.hh" #include "sim/serialize.hh" #include <string.h> @@ -119,11 +120,13 @@ void IntRegFile::clear() IntReg IntRegFile::readReg(int intReg) { + DPRINTF(X86, "Read int reg %d and got value %#x\n", intReg, regs[intReg]); return regs[intReg]; } void IntRegFile::setReg(int intReg, const IntReg &val) { + DPRINTF(X86, "Setting int reg %d to value %#x\n", intReg, val); regs[intReg] = val; } diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh index 562539de9..fc2098716 100644 --- a/src/arch/x86/intregs.hh +++ b/src/arch/x86/intregs.hh @@ -66,45 +66,45 @@ namespace X86ISA INTREG_EAX = INTREG_RAX, INTREG_AX = INTREG_RAX, INTREG_AL = INTREG_RAX, - INTREG_AH = INTREG_RAX, INTREG_RCX, INTREG_ECX = INTREG_RCX, INTREG_CX = INTREG_RCX, INTREG_CL = INTREG_RCX, - INTREG_CH = INTREG_RCX, INTREG_RDX, INTREG_EDX = INTREG_RDX, INTREG_DX = INTREG_RDX, INTREG_DL = INTREG_RDX, - INTREG_DH = INTREG_RDX, INTREG_RBX, INTREG_EBX = INTREG_RBX, INTREG_BX = INTREG_RBX, INTREG_BL = INTREG_RBX, - INTREG_BH = INTREG_RBX, INTREG_RSP, INTREG_ESP = INTREG_RSP, INTREG_SP = INTREG_RSP, INTREG_SPL = INTREG_RSP, + INTREG_AH = INTREG_RSP, INTREG_RBP, INTREG_EBP = INTREG_RBP, INTREG_BP = INTREG_RBP, INTREG_BPL = INTREG_RBP, + INTREG_CH = INTREG_RBP, INTREG_RSI, INTREG_ESI = INTREG_RSI, INTREG_SI = INTREG_RSI, INTREG_SIL = INTREG_RSI, + INTREG_DH = INTREG_RSI, INTREG_RDI, INTREG_EDI = INTREG_RDI, INTREG_DI = INTREG_RDI, INTREG_DIL = INTREG_RDI, + INTREG_BH = INTREG_RDI, INTREG_R8, INTREG_R8D = INTREG_R8, diff --git a/src/arch/x86/isa/base.isa b/src/arch/x86/isa/base.isa index eba24f709..eed969b47 100644 --- a/src/arch/x86/isa/base.isa +++ b/src/arch/x86/isa/base.isa @@ -95,6 +95,14 @@ output header {{ /** * Base class for all X86 static instructions. */ + BitUnion64(X86IntReg) + Bitfield<63,0> R; + Bitfield<31,0> E; + Bitfield<15,0> X; + Bitfield<15,8> H; + Bitfield<7, 0> L; + EndBitUnion(X86IntReg) + class X86StaticInst : public StaticInst { protected: @@ -114,10 +122,50 @@ output header {{ inline uint64_t merge(uint64_t into, uint64_t val, int size) const { - //FIXME This needs to be significantly more sophisticated + X86IntReg reg; + reg = into; + //FIXME This needs to be handle high bytes as well + switch(size) + { + case 1: + reg.L = val; + break; + case 2: + reg.X = val; + break; + case 4: + //XXX Check if this should be zeroed or sign extended + reg = 0; + reg.E = val; + break; + case 8: + reg.R = val; + break; + default: + panic("Tried to merge with unrecognized size %d.\n", size); + } return val; } + inline uint64_t pick(uint64_t from, int size) + { + X86IntReg reg; + reg = from; + switch(size) + { + case 1: + return reg.L; + case 2: + return reg.E; + case 4: + return reg.X; + case 8: + return reg.R; + default: + panic("Tried to pick with unrecognized size %d.\n", size); + } + } + }; }}; @@ -128,6 +176,39 @@ output decoder {{ ccprintf(os, "\t%s ", mnemonic); } + inline void printMnemonic(std::ostream &os, + const char * instMnemonic, const char * mnemonic) + { + ccprintf(os, "\t%s : %s ", instMnemonic, mnemonic); + } + + void printSegment(std::ostream &os, int segment) + { + switch (segment) + { + case 0: + ccprintf(os, "ES"); + break; + case 1: + ccprintf(os, "CS"); + break; + case 2: + ccprintf(os, "SS"); + break; + case 3: + ccprintf(os, "DS"); + break; + case 4: + ccprintf(os, "FS"); + break; + case 5: + ccprintf(os, "GS"); + break; + default: + panic("Unrecognized segment %d\n", segment); + } + } + void X86StaticInst::printSrcReg(std::ostream &os, int reg) const { @@ -197,6 +278,8 @@ output decoder {{ case INTREG_R15W: ccprintf(os, "r15"); break; + default: + ccprintf(os, "t%d", reg - NUM_INTREGS); } } else if (reg < Ctrl_Base_DepTag) { ccprintf(os, "%%f%d", reg - FP_Base_DepTag); diff --git a/src/arch/x86/isa/bitfields.isa b/src/arch/x86/isa/bitfields.isa index fff324caa..8707bbb4c 100644 --- a/src/arch/x86/isa/bitfields.isa +++ b/src/arch/x86/isa/bitfields.isa @@ -58,9 +58,21 @@ // Bitfield definitions. // -//Prefixes +//REX prefix def bitfield REX rex; +def bitfield REX_W rex.w; +def bitfield REX_R rex.r; +def bitfield REX_X rex.x; +def bitfield REX_B rex.b; + +//Legacy prefixes def bitfield LEGACY legacy; +def bitfield LEGACY_REPNE legacy.repne; +def bitfield LEGACY_REP legacy.rep; +def bitfield LEGACY_LOCK legacy.lock; +def bitfield LEGACY_ADDR legacy.addr; +def bitfield LEGACY_OP legacy.op; +def bitfield LEGACY_SEG legacy.seg; // Pieces of the opcode def bitfield OPCODE_NUM opcode.num; @@ -85,3 +97,11 @@ def bitfield SIB sib; def bitfield SIB_SCALE sib.scale; def bitfield SIB_INDEX sib.index; def bitfield SIB_BASE sib.base; + +def bitfield OPSIZE opSize; +def bitfield ADDRSIZE addrSize; +def bitfield STACKSIZE stackSize; + +def bitfield MODE mode; +def bitfield MODE_MODE mode.mode; +def bitfield MODE_SUBMODE mode.submode; diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index 4e044363b..b72b2b16a 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -61,12 +61,11 @@ 0x1: decode OPCODE_OP_TOP5 { format WarnUnimpl { 0x00: decode OPCODE_OP_BOTTOM3 { - 0x4: Inst::ADD(rAl,Ib); - 0x5: Inst::ADD(rAx,Iz); + 0x4: ADD(); + 0x5: ADD(); 0x6: push_ES(); 0x7: pop_ES(); - default: MultiInst::ADD(OPCODE_OP_BOTTOM3, - [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); + default: ADD(); } 0x01: decode OPCODE_OP_BOTTOM3 { 0x0: or_Eb_Gb(); @@ -129,7 +128,8 @@ {{"Tried to execute the SS segment override prefix!"}}); 0x7: aaa(); default: MultiInst::XOR(OPCODE_OP_BOTTOM3, - [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); + [Eb,Gb], [Ev,Gv], + [Gb,Eb], [Gv,Ev]); } 0x07: decode OPCODE_OP_BOTTOM3 { 0x0: cmp_Eb_Gb(); @@ -163,11 +163,11 @@ 0x7: dec_eDI(); } 0x0A: decode OPCODE_OP_BOTTOM3 { - 0x0: push_rAX(); + 0x0: Inst::PUSH(rAx); 0x1: push_rCX(); 0x2: push_rDX(); 0x3: push_rBX(); - 0x4: push_rSP(); + 0x4: Inst::PUSH(rSP); 0x5: push_rBP(); 0x6: push_rSI(); 0x7: push_rDI(); @@ -179,7 +179,7 @@ 0x3: pop_rBX(); 0x4: pop_rSP(); 0x5: pop_rBP(); - 0x6: pop_rSI(); + 0x6: Inst::POP(rSI); 0x7: pop_rDI(); } 0x0C: decode OPCODE_OP_BOTTOM3 { @@ -230,18 +230,28 @@ 0x0: group1_Eb_Ib(); 0x1: group1_Ev_Iz(); 0x2: group1_Eb_Ib(); - 0x3: group1_Ev_Ib(); + //0x3: group1_Ev_Ib(); + 0x3: decode MODRM_REG { + 0x0: add_Eb_Ib(); + 0x1: or_Eb_Ib(); + 0x2: adc_Eb_Ib(); + 0x3: sbb_Eb_Ib(); + 0x4: Inst::AND(Eb,Ib); + 0x5: sub_Eb_Ib(); + 0x6: xor_Eb_Ib(); + 0x7: cmp_Eb_Ib(); + } 0x4: test_Eb_Gb(); 0x5: test_Ev_Gv(); 0x6: xchg_Eb_Gb(); 0x7: xchg_Ev_Gv(); } 0x11: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::MOV(); //mov_Eb_Gb(); - 0x1: Inst::MOV(); //mov_Ev_Gv(); - 0x2: Inst::MOV(); //mov_Gb_Eb(); - 0x3: Inst::MOV(); //mov_Gv_Ev(); - 0x4: Inst::MOV(); //mov_MwRv_Sw(); + 0x0: Inst::MOV(Eb,Gb); + 0x1: Inst::MOV(Ev,Gv); + 0x2: Inst::MOV(Gb,Eb); + 0x3: Inst::MOV(Gv,Eb); + 0x4: mov_MwRv_Sw(); //What to do with this one? 0x5: lea_Gv_M(); 0x6: mov_Sw_MwRv(); 0x7: group10_Ev(); //Make sure this is Ev @@ -313,8 +323,14 @@ 0x3: ret_near(); 0x4: les_Gz_Mp(); 0x5: lds_Gz_Mp(); - 0x6: group12_Eb_Ib(); - 0x7: group12_Ev_Iz(); + //0x6: group12_Eb_Ib(); + 0x6: decode MODRM_REG { + 0x0: Inst::MOV(Eb,Ib); + } + //0x7: group12_Ev_Iz(); + 0x7: decode MODRM_REG { + 0x0: Inst::MOV(Ev,Iz); + } } 0x19: decode OPCODE_OP_BOTTOM3 { 0x0: enter_Iw_Ib(); diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa index 8f91c249c..37b28fe64 100644 --- a/src/arch/x86/isa/formats/multi.isa +++ b/src/arch/x86/isa/formats/multi.isa @@ -55,32 +55,23 @@ // // Authors: Gabe Black -//////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// // -// Instructions that do the same thing to multiple sets of arguments. +// Instructions operate on one or multiple types of sets of arguments. // - -let {{ - def doInst(name, Name, opTypeSet): - if not instDict.has_key(Name): - raise Exception, "Unrecognized instruction: %s" % Name - inst = instDict[Name]() - return inst.emit(opTypeSet) -}}; +////////////////////////////////////////////////////////////////////////// def format Inst(*opTypeSet) {{ - (header_output, - decoder_output, - decode_block, - exce_output) = doInst(name, Name, list(opTypeSet)).makeList() + blocks = specializeInst(Name, list(opTypeSet), EmulEnv()) + (header_output, decoder_output, + decode_block, exec_output) = blocks.makeList() }}; def format MultiInst(switchVal, *opTypeSets) {{ switcher = {} for (count, opTypeSet) in zip(xrange(len(opTypeSets)), opTypeSets): - switcher[count] = (opTypeSet,) - (header_output, - decoder_output, - decode_block, - exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher).makeList() + switcher[count] = (Name, opTypeSet, EmulEnv()) + blocks = doSplitDecode(specializeInst, switchVal, switcher) + (header_output, decoder_output, + decode_block, exec_output) = blocks.makeList() }}; diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 3440ec5da..8bb282150 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -99,6 +99,7 @@ output header {{ #include "arch/x86/faults.hh" #include "arch/x86/isa_traits.hh" #include "arch/x86/regfile.hh" +#include "arch/x86/types.hh" #include "base/misc.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" @@ -106,6 +107,7 @@ output header {{ }}; output decoder {{ + #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" // for Jump::branchTarget() diff --git a/src/arch/x86/isa/insts/__init__.py b/src/arch/x86/isa/insts/__init__.py new file mode 100644 index 000000000..717690926 --- /dev/null +++ b/src/arch/x86/isa/insts/__init__.py @@ -0,0 +1,79 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["arithmetic", + "cache_and_memory_management", + "compare_and_test", + "control_transfer", + "data_conversion", + "data_transfer", + "flags", + "input_output", + "load_effective_address", + "load_segment_registers", + "logical", + "no_operation", + "processor_information", + "rotate_and_shift", + "semaphores", + "string", + "system_calls"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/arithmetic/__init__.py b/src/arch/x86/isa/insts/arithmetic/__init__.py new file mode 100644 index 000000000..c7e6b8c5f --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["add_and_subtract", + "increment_and_decrement", + "multiply_and_divide"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode + diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py new file mode 100644 index 000000000..283152f30 --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class ADC(Inst): +# "Adc ^0 ^0 ^1" +# class ADD(Inst): +# "Add ^0 ^0 ^1" +# class SBB(Inst): +# "Sbb ^0 ^0 ^1" +# class SUB(Inst): +# "Sub ^0 ^0 ^1" +# class NEG(Inst): +# "Sub ^0 $0 ^0" +#}}; diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py new file mode 100644 index 000000000..c504d47ce --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class DEC(Inst): +# "GenFault ${new UnimpInstFault}" +# class INC(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py new file mode 100644 index 000000000..662022e6a --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class MUL(Inst): +# "GenFault ${new UnimpInstFault}" +# class IMUL(Inst): +# "GenFault ${new UnimpInstFault}" +# class DIV(Inst): +# "GenFault ${new UnimpInstFault}" +# class IDIV(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/cache_and_memory_management.py b/src/arch/x86/isa/insts/cache_and_memory_management.py new file mode 100644 index 000000000..b5fc43fcd --- /dev/null +++ b/src/arch/x86/isa/insts/cache_and_memory_management.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LFENCE(Inst): +# "GenFault ${new UnimpInstFault}" +# class SFENCE(Inst): +# "GenFault ${new UnimpInstFault}" +# class MFENCE(Inst): +# "GenFault ${new UnimpInstFault}" +# class PREFETCHlevel(Inst): +# "GenFault ${new UnimpInstFault}" +# class PREFETCH(Inst): +# "GenFault ${new UnimpInstFault}" +# class PREFETCHW(Inst): +# "GenFault ${new UnimpInstFault}" +# class CLFLUSH(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/__init__.py b/src/arch/x86/isa/insts/compare_and_test/__init__.py new file mode 100644 index 000000000..56f33585a --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["bit_scan", + "bit_test", + "bounds", + "compare", + "set_byte_on_condition", + "test"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/compare_and_test/bit_scan.py b/src/arch/x86/isa/insts/compare_and_test/bit_scan.py new file mode 100644 index 000000000..f04520296 --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/bit_scan.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BSF(Inst): +# "GenFault ${new UnimpInstFault}" +# class BSR(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/compare_and_test/bit_test.py new file mode 100644 index 000000000..e950f008a --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/bit_test.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BT(Inst): +# "GenFault ${new UnimpInstFault}" +# class BTC(Inst): +# "GenFault ${new UnimpInstFault}" +# class BTR(Inst): +# "GenFault ${new UnimpInstFault}" +# class BTS(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/bounds.py b/src/arch/x86/isa/insts/compare_and_test/bounds.py new file mode 100644 index 000000000..4b6cc8f71 --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/bounds.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BOUND(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/compare.py b/src/arch/x86/isa/insts/compare_and_test/compare.py new file mode 100644 index 000000000..12b5b859f --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/compare.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py new file mode 100644 index 000000000..3d9250c2d --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SETcc(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py new file mode 100644 index 000000000..b4d1cf9b8 --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/test.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class TEST(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/__init__.py b/src/arch/x86/isa/insts/control_transfer/__init__.py new file mode 100644 index 000000000..6694b857c --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["call", + "conditional_jump", + "interrupts_and_exceptions", + "jump", + "loop", + "xreturn"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py new file mode 100644 index 000000000..231db6e40 --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/call.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CALL(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/conditional_jump.py b/src/arch/x86/isa/insts/control_transfer/conditional_jump.py new file mode 100644 index 000000000..7ca426be6 --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/conditional_jump.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class JCC(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py new file mode 100644 index 000000000..7039b4b5c --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class INT(Inst): +# "GenFault ${new UnimpInstFault}" +# class INTO(Inst): +# "GenFault ${new UnimpInstFault}" +# class IRET(Inst): +# "GenFault ${new UnimpInstFault}" +# class IRETD(Inst): +# "GenFault ${new UnimpInstFault}" +# class IRETQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/jump.py b/src/arch/x86/isa/insts/control_transfer/jump.py new file mode 100644 index 000000000..e90e5b12b --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/jump.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class JMP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/loop.py b/src/arch/x86/isa/insts/control_transfer/loop.py new file mode 100644 index 000000000..d742f217f --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/loop.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LOOPcc(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/xreturn.py b/src/arch/x86/isa/insts/control_transfer/xreturn.py new file mode 100644 index 000000000..aaffa2b92 --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/xreturn.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class RET(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/__init__.py b/src/arch/x86/isa/insts/data_conversion/__init__.py new file mode 100644 index 000000000..b3a40b8a0 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["ascii_adjust", + "bcd_adjust", + "endian_conversion", + "extract_sign_mask", + "sign_extension", + "translate"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py b/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py new file mode 100644 index 000000000..a1e322e56 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class AAA(Inst): +# "GenFault ${new UnimpInstFault}" +# class AAD(Inst): +# "GenFault ${new UnimpInstFault}" +# class AAM(Inst): +# "GenFault ${new UnimpInstFault}" +# class AAS(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py b/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py new file mode 100644 index 000000000..213724768 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class DAA(Inst): +# "GenFault ${new UnimpInstFault}" +# class DAS(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/endian_conversion.py b/src/arch/x86/isa/insts/data_conversion/endian_conversion.py new file mode 100644 index 000000000..b98d09816 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/endian_conversion.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BSWAP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py b/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py new file mode 100644 index 000000000..1e0810594 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class MOVMSKPS(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVMSKPD(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/data_conversion/sign_extension.py new file mode 100644 index 000000000..e96eee694 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/sign_extension.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CBW(Inst): +# "GenFault ${new UnimpInstFault}" +# class CWDE(Inst): +# "GenFault ${new UnimpInstFault}" +# class CDQE(Inst): +# "GenFault ${new UnimpInstFault}" +# class CWD(Inst): +# "GenFault ${new UnimpInstFault}" +# class CDQ(Inst): +# "GenFault ${new UnimpInstFault}" +# class CQO(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/translate.py b/src/arch/x86/isa/insts/data_conversion/translate.py new file mode 100644 index 000000000..bb286b976 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/translate.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class XLAT(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/__init__.py b/src/arch/x86/isa/insts/data_transfer/__init__.py new file mode 100644 index 000000000..eda173b34 --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/__init__.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["conditional_move", + "move", + "stack_operations"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/data_transfer/conditional_move.py new file mode 100644 index 000000000..513e90c4e --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/conditional_move.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMOVcc(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py new file mode 100644 index 000000000..ff4af0af4 --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/move.py @@ -0,0 +1,89 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop MOV_R_R { + mov "env.reg", "env.reg", "env.regm" +}; + +def macroop MOV_M_R { + #Do a store to put the register operand into memory +}; + +def macroop MOV_R_M { + #Do a load to fill the register operand from memory +}; + +def macroop MOV_R_I { + limm "env.reg", "IMMEDIATE" +}; + +def macroop MOV_M_I { + limm "env.reg", "IMMEDIATE" + #Do a store to put the register operand into memory +}; +''' +#let {{ +# class MOV(Inst): +# "Mov ^0 ^0 ^1" +# class MOVSX(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVZX(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVD(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVNTI(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py new file mode 100644 index 000000000..50b690354 --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py @@ -0,0 +1,94 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop POP_R { + + # Make the default data size of pops 64 bits in 64 bit mode + .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + + ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] + addi "INTREG_RSP", "INTREG_RSP", "env.dataSize" +}; + +def macroop PUSH_R { + + # Make the default data size of pops 64 bits in 64 bit mode + .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + + subi "INTREG_RSP", "INTREG_RSP", "env.dataSize" + st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] +}; +''' +#let {{ +# class POP(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPA(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPA(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPAD(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSH(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHA(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHAD(Inst): +# "GenFault ${new UnimpInstFault}" +# class ENTER(Inst): +# "GenFault ${new UnimpInstFault}" +# class LEAVE(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/flags/__init__.py b/src/arch/x86/isa/insts/flags/__init__.py new file mode 100644 index 000000000..92a8e6a2d --- /dev/null +++ b/src/arch/x86/isa/insts/flags/__init__.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["load_and_store", + "push_and_pop", + "set_and_clear"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/flags/load_and_store.py b/src/arch/x86/isa/insts/flags/load_and_store.py new file mode 100644 index 000000000..c6f279a25 --- /dev/null +++ b/src/arch/x86/isa/insts/flags/load_and_store.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LAHF(Inst): +# "GenFault ${new UnimpInstFault}" +# class SAHF(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/flags/push_and_pop.py b/src/arch/x86/isa/insts/flags/push_and_pop.py new file mode 100644 index 000000000..dbb6c34c4 --- /dev/null +++ b/src/arch/x86/isa/insts/flags/push_and_pop.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class POPF(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPFD(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPFQ(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHF(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHFD(Inst): +# "GenFault ${new UnimpInstFault}" +# class pushfq(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/flags/set_and_clear.py b/src/arch/x86/isa/insts/flags/set_and_clear.py new file mode 100644 index 000000000..d70b95382 --- /dev/null +++ b/src/arch/x86/isa/insts/flags/set_and_clear.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CLC(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMC(Inst): +# "GenFault ${new UnimpInstFault}" +# class STC(Inst): +# "GenFault ${new UnimpInstFault}" +# class CLD(Inst): +# "GenFault ${new UnimpInstFault}" +# class STD(Inst): +# "GenFault ${new UnimpInstFault}" +# class CLI(Inst): +# "GenFault ${new UnimpInstFault}" +# class STI(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/input_output/__init__.py b/src/arch/x86/isa/insts/input_output/__init__.py new file mode 100644 index 000000000..54fb3d9b0 --- /dev/null +++ b/src/arch/x86/isa/insts/input_output/__init__.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["general_io", + "string_io"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/input_output/general_io.py b/src/arch/x86/isa/insts/input_output/general_io.py new file mode 100644 index 000000000..f9aa9d6e4 --- /dev/null +++ b/src/arch/x86/isa/insts/input_output/general_io.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class IN(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUT(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/input_output/string_io.py b/src/arch/x86/isa/insts/input_output/string_io.py new file mode 100644 index 000000000..a35ba772f --- /dev/null +++ b/src/arch/x86/isa/insts/input_output/string_io.py @@ -0,0 +1,78 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class INS(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSQ(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTS(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py new file mode 100644 index 000000000..dab6960b1 --- /dev/null +++ b/src/arch/x86/isa/insts/load_effective_address.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LEA(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/load_segment_registers.py b/src/arch/x86/isa/insts/load_segment_registers.py new file mode 100644 index 000000000..8aec4b99e --- /dev/null +++ b/src/arch/x86/isa/insts/load_segment_registers.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LDS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LES(Inst): +# "GenFault ${new UnimpInstFault}" +# class LFS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LGS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LSS(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOV_SEG(Inst): +# "GenFault ${new UnimpInstFault}" +# class POP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py new file mode 100644 index 000000000..824c75053 --- /dev/null +++ b/src/arch/x86/isa/insts/logical.py @@ -0,0 +1,114 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop XOR_R_R +{ + xor "env.reg", "env.reg", "env.regm" +}; + +def macroop XOR_R_I +{ + limm "NUM_INTREGS+1", "IMMEDIATE" + xor "env.reg", "env.reg", "NUM_INTREGS+1" +}; + +def macroop XOR_M_R +{ + #Do a load to get one of the sources + xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg" + #Do a store to write the destination +}; + +def macroop XOR_R_M +{ + #Do a load to get one of the sources + xor "env.reg", "env.reg", "NUM_INTREGS+1" +}; + +def macroop AND_R_I +{ + limm "NUM_INTREGS+1", "IMMEDIATE" + and "env.reg", "env.reg", "NUM_INTREGS+1" +}; + +def macroop AND_M_I +{ + #Do a load to get one of the sources + limm "NUM_INTREGS+1", "IMMEDIATE" + and "NUM_INTREGS+1", "NUM_INTREGS+1", "NUM_INTREGS+2" + #Do a store to write the destination +}; +''' +#let {{ +#microcodeString = ''' +# def macroop AND +# { +# And reg reg regm +# }; +# def macroop OR +# { +# Or reg reg regm +# }; +# def macroop XOR +# { +# Xor reg reg regm +# }; +# def macroop NOT +# { +# Xor reg reg "0xFFFFFFFFFFFFFFFFULL" +# }; +#''' +#}}; diff --git a/src/arch/x86/isa/insts/no_operation.py b/src/arch/x86/isa/insts/no_operation.py new file mode 100644 index 000000000..1a287aea7 --- /dev/null +++ b/src/arch/x86/isa/insts/no_operation.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class NOP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/processor_information.py b/src/arch/x86/isa/insts/processor_information.py new file mode 100644 index 000000000..b9c8a407e --- /dev/null +++ b/src/arch/x86/isa/insts/processor_information.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CPUID(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/rotate_and_shift/__init__.py b/src/arch/x86/isa/insts/rotate_and_shift/__init__.py new file mode 100644 index 000000000..c6c019f0d --- /dev/null +++ b/src/arch/x86/isa/insts/rotate_and_shift/__init__.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["rotate", + "shift"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py new file mode 100644 index 000000000..e3aaf0043 --- /dev/null +++ b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class RCL(Inst): +# "GenFault ${new UnimpInstFault}" +# class RCR(Inst): +# "GenFault ${new UnimpInstFault}" +# class ROL(Inst): +# "GenFault ${new UnimpInstFault}" +# class ROR(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py new file mode 100644 index 000000000..f72794657 --- /dev/null +++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SAL(Inst): +# "GenFault ${new UnimpInstFault}" +# class SAR(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHL(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHR(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHLD(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHRD(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/semaphores.py b/src/arch/x86/isa/insts/semaphores.py new file mode 100644 index 000000000..32f28cf82 --- /dev/null +++ b/src/arch/x86/isa/insts/semaphores.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMPXCHG(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPXCHG8B(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPXCHG16B(Inst): +# "GenFault ${new UnimpInstFault}" +# class XADD(Inst): +# "GenFault ${new UnimpInstFault}" +# class XCHG(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/__init__.py b/src/arch/x86/isa/insts/string/__init__.py new file mode 100644 index 000000000..f43a8d3e5 --- /dev/null +++ b/src/arch/x86/isa/insts/string/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["compare_strings", + "load_string", + "move_string", + "scan_string", + "store_string"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/string/compare_strings.py b/src/arch/x86/isa/insts/string/compare_strings.py new file mode 100644 index 000000000..1484c4706 --- /dev/null +++ b/src/arch/x86/isa/insts/string/compare_strings.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMPS(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/load_string.py b/src/arch/x86/isa/insts/string/load_string.py new file mode 100644 index 000000000..0f749a273 --- /dev/null +++ b/src/arch/x86/isa/insts/string/load_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LODS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/move_string.py b/src/arch/x86/isa/insts/string/move_string.py new file mode 100644 index 000000000..0a855b384 --- /dev/null +++ b/src/arch/x86/isa/insts/string/move_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class MOVS(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/scan_string.py b/src/arch/x86/isa/insts/string/scan_string.py new file mode 100644 index 000000000..cd3d5b549 --- /dev/null +++ b/src/arch/x86/isa/insts/string/scan_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SCAS(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASB(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASW(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASD(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/store_string.py b/src/arch/x86/isa/insts/string/store_string.py new file mode 100644 index 000000000..08a126c1f --- /dev/null +++ b/src/arch/x86/isa/insts/string/store_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class STOS(Inst): +# "Add 0 0 0" +# class STOSB(Inst): +# "Add 0 0 0" +# class STOSW(Inst): +# "Add 0 0 0" +# class STOSD(Inst): +# "Add 0 0 0" +# class STOSQ(Inst): +# "Add 0 0 0" +#}}; diff --git a/src/arch/x86/isa/insts/system_calls.py b/src/arch/x86/isa/insts/system_calls.py new file mode 100644 index 000000000..e056bea84 --- /dev/null +++ b/src/arch/x86/isa/insts/system_calls.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SYSENTER(Inst): +# "GenFault ${new UnimpInstFault}" +# class SYSEXIT(Inst): +# "GenFault ${new UnimpInstFault}" +# class SYSCALL(Inst): +# "GenFault ${new UnimpInstFault}" +# class SYSRET(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 663ec7aee..0cc818409 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -71,34 +71,34 @@ def template MacroExecPanic {{ output header {{ - // Base class for macroops - class MacroOp : public StaticInst + // Base class for combinationally generated macroops + class Macroop : public StaticInst { protected: - const uint32_t numMicroOps; + const uint32_t numMicroops; //Constructor. - MacroOp(const char *mnem, ExtMachInst _machInst, - uint32_t _numMicroOps) + Macroop(const char *mnem, ExtMachInst _machInst, + uint32_t _numMicroops) : StaticInst(mnem, _machInst, No_OpClass), - numMicroOps(_numMicroOps) + numMicroops(_numMicroops) { - assert(numMicroOps); - microOps = new StaticInstPtr[numMicroOps]; - flags[IsMacroOp] = true; + assert(numMicroops); + microops = new StaticInstPtr[numMicroops]; + flags[IsMacroop] = true; } - ~MacroOp() + ~Macroop() { - delete [] microOps; + delete [] microops; } - StaticInstPtr * microOps; + StaticInstPtr * microops; - StaticInstPtr fetchMicroOp(MicroPC microPC) + StaticInstPtr fetchMicroop(MicroPC microPC) { - assert(microPC < numMicroOps); - return microOps[microPC]; + assert(microPC < numMicroops); + return microops[microPC]; } std::string generateDisassembly(Addr pc, @@ -113,26 +113,30 @@ output header {{ // Basic instruction class declaration template. def template MacroDeclare {{ - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s + namespace X86Macroop { - public: - // Constructor. - %(class_name)s(ExtMachInst machInst); + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + // Constructor. + %(class_name)s(ExtMachInst machInst, EmulEnv env); + }; }; }}; // Basic instruction class constructor template. def template MacroConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst, %(num_micro_ops)s) + inline X86Macroop::%(class_name)s::%(class_name)s(ExtMachInst machInst, EmulEnv env) + : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s) { - %(constructor)s; - //alloc_micro_ops is the code that sets up the microOps - //array in the parent class. - %(alloc_micro_ops)s; + %(adjust_env)s; + %(constructor)s; + //alloc_microops is the code that sets up the microops + //array in the parent class. + %(alloc_microops)s; } }}; @@ -142,23 +146,103 @@ def template MacroConstructor {{ // let {{ - def genMacroOp(name, Name, opSeq): - numMicroOps = len(opSeq) - allocMicroOps = '' - micropc = 0 - for op in opSeq: - allocMicroOps += \ - "microOps[%d] = %s;\n" % \ - (micropc, op.getAllocator('"' + name + '"', True, False, #op.delayed, - micropc == 0, - micropc == numMicroOps - 1)) - micropc += 1 - iop = InstObjParams(name, Name, 'MacroOp', - {'code' : '', 'num_micro_ops' : numMicroOps, - 'alloc_micro_ops' : allocMicroOps}) - header_output = MacroDeclare.subst(iop) - decoder_output = MacroConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = '' - return (header_output, decoder_output, decode_block, exec_output) + from micro_asm import Combinational_Macroop, Rom_Macroop + class X86Macroop(Combinational_Macroop): + def setAdjustEnv(self, val): + self.adjust_env = val + def __init__(self, name): + super(X86Macroop, self).__init__(name) + self.directives = { + "adjust_env" : self.setAdjustEnv + } + self.declared = False + self.adjust_env = "" + def getAllocator(self, env): + return "new X86Macroop::%s(machInst, %s)" % (self.name, env.getAllocator()) + def getDeclaration(self): + #FIXME This first parameter should be the mnemonic. I need to + #write some code which pulls that out + iop = InstObjParams(self.name, self.name, "Macroop", {"code" : ""}) + return MacroDeclare.subst(iop); + def getDefinition(self): + #FIXME This first parameter should be the mnemonic. I need to + #write some code which pulls that out + numMicroops = len(self.microops) + allocMicroops = '' + micropc = 0 + for op in self.microops: + allocMicroops += \ + "microops[%d] = %s;\n" % \ + (micropc, op.getAllocator(True, False, + micropc == 0, + micropc == numMicroops - 1)) + micropc += 1 + iop = InstObjParams(self.name, self.name, "Macroop", + {"code" : "", "num_microops" : numMicroops, + "alloc_microops" : allocMicroops, + "adjust_env" : self.adjust_env}) + return MacroConstructor.subst(iop); +}}; + +output header {{ + struct EmulEnv + { + X86ISA::RegIndex reg; + X86ISA::RegIndex regm; + uint8_t scale; + X86ISA::RegIndex index; + X86ISA::RegIndex base; + int dataSize; + int addressSize; + int stackSize; + + EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm, + int _dataSize, int _addressSize, int _stackSize) : + reg(_reg), regm(_regm), + dataSize(_dataSize), addressSize(_addressSize), + stackSize(_stackSize) + {;} + }; +}}; + +let {{ + class EmulEnv(object): + def __init__(self): + self.reg = "0" + self.regUsed = False + self.regm = "0" + self.regmUsed = False + self.addressSize = "ADDRSIZE" + self.dataSize = "OPSIZE" + self.stackSize = "STACKSIZE" + def getAllocator(self): + return '''EmulEnv(%(reg)s, + %(regm)s, + %(dataSize)s, + %(addressSize)s, + %(stackSize)s)''' % \ + self.__dict__ + def addReg(self, reg): + if not self.regUsed: + self.reg = reg + self.regUsed = True + elif not self.regmUsed: + self.regm = reg + self.regmUsed = True + else: + raise Exception, "EmulEnv is out of register specialization spots." +}}; + +let {{ + def genMacroop(Name, env): + blocks = OutputBlocks() + if not macroopDict.has_key(Name): + raise Exception, "Unrecognized instruction: %s" % Name + macroop = macroopDict[Name] + if not macroop.declared: + blocks.header_output = macroop.getDeclaration() + blocks.decoder_output = macroop.getDefinition() + macroop.declared = True + blocks.decode_block = "return %s;\n" % macroop.getAllocator(env) + return blocks }}; diff --git a/src/arch/x86/isa/main.isa b/src/arch/x86/isa/main.isa index 063d7125d..fed8903c0 100644 --- a/src/arch/x86/isa/main.isa +++ b/src/arch/x86/isa/main.isa @@ -67,60 +67,32 @@ //////////////////////////////////////////////////////////////////// // // Namespace statement. Everything below this line will be in the -// SparcISAInst namespace. +// X86ISAInst namespace. // namespace X86ISA; -//////////////////////////////////////////////////////////////////// -// -// General infrastructure code. These files provide infrastructure -// which was developed to support x86 but isn't specific to it. -// - -//Include code to build macroops. -##include "macroop.isa" - -//Include the simple microcode assembler. This will hopefully stay -//unspecialized for x86 and can later be made available to other ISAs. -##include "microasm.isa" +//Include the operand_types and operand definitions. These are needed by +//the microop definitions. +##include "operands.isa" -//////////////////////////////////////////////////////////////////// -// -// X86 only infrastructure code. -// +//Include the bitfield definitions +##include "bitfields.isa" //Include the base class for x86 instructions, and some support code. ##include "base.isa" -//Include code to specialize an instruction template to operate on -//a particular set of operands. This is specific to x86 and the x86 -//microcode ISA. -##include "specialize.isa" - -//////////////////////////////////////////////////////////////////// -// -// Code which directly specifies isa components like instructions -// microops, and the decoder. -// - //Include the definitions for the instruction formats ##include "formats/formats.isa" -//Include the operand_types and operand definitions. These are needed by -//the microop definitions. -##include "operands.isa" - -//Include the definitions of the micro ops. -//These are StaticInst classes which stand on their own and make up an -//internal instruction set. -##include "microops/microops.isa" - -//Include the instruction definitions which are microop assembler programs. -##include "insts/insts.isa" +//This file brings in the microcode, microop classes, macroop classes, +//and supporting components and assembles everything into macroops. +##include "microasm.isa" -//Include the bitfield definitions -##include "bitfields.isa" +//Include code to specialize an instruction template to operate on +//a particular set of operands. This is specific to x86 and the x86 +//microcode ISA. +##include "specialize.isa" //Include the decoder definition ##include "decoder/decoder.isa" diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 9d21b6bcc..fde430691 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -55,177 +55,22 @@ // // Authors: Gabe Black -//////////////////////////////////////////////////////////////////// -// -// The microcode assembler -// +//Include the definitions of the micro ops. +//These are StaticInst classes which stand on their own and make up an +//internal instruction set, and also python representations which are passed +//into the microcode assembler. +##include "microops/microops.isa" -let {{ - # These are used when setting up microops so that they can specialize their - # base class template properly. - RegOpType = "RegisterOperand" - ImmOpType = "ImmediateOperand" -}}; +//Include code to build macroops in both C++ and python. +##include "macroop.isa" let {{ - class MicroOpStatement(object): - def __init__(self): - self.className = '' - self.label = '' - self.args = [] - - # This converts a list of python bools into - # a comma seperated list of C++ bools. - def microFlagsText(self, vals): - text = "" - for val in vals: - if val: - text += ", true" - else: - text += ", false" - return text - - def getAllocator(self, mnemonic, *microFlags): - args = '' - signature = "<" - emptySig = True - for arg in self.args: - if not emptySig: - signature += ", " - emptySig = False - if arg.has_key("operandImm"): - args += ", %s" % arg["operandImm"] - signature += ImmOpType - elif arg.has_key("operandReg"): - args += ", %s" % arg["operandReg"] - signature += RegOpType - elif arg.has_key("operandLabel"): - raise Exception, "Found a label while creating allocator string." - else: - raise Exception, "Unrecognized operand type." - signature += ">" - return 'new %s%s(machInst, %s%s%s)' % (self.className, signature, mnemonic, self.microFlagsText(microFlags), args) -}}; - -let{{ - def assembleMicro(name, Name, code): - - # This function takes in a block of microcode assembly and returns - # a python list of objects which describe it. - - # Keep this around in case we need it later - orig_code = code - # A list of the statements we've found thus far - statements = [] - - # Regular expressions to pull each piece of the statement out at a - # time. Each expression expects the thing it's looking for to be at - # the beginning of the line, so the previous component is stripped - # before continuing. - labelRe = re.compile(r'^[ \t]*(?P<label>\w\w*)[ \t]:') - lineRe = re.compile(r'^(?P<line>..*)(\n|$)') - classRe = re.compile(r'^[ \t]*(?P<className>[a-zA-Z_]\w*)') - # This recognizes three different flavors of operands: - # 1. Raw decimal numbers composed of digits between 0 and 9 - # 2. Code beginning with "{" and continuing until the first "}" - # ^ This one might need revising - # 3. A label, which starts with a capital or small letter, or - # underscore, which is optionally followed by a sequence of - # capital or small letters, underscores, or digts between 0 and 9 - opRe = re.compile( \ - r'^[ \t]*((\@(?P<operandLabel0>\w\w*))|' + - r'(\@\{(?P<operandLabel1>[^}]*)\})|' + - r'(\%(?P<operandReg0>\w\w*))|' + - r'(\%\{(?P<operandReg1>[^}]*)\})|' + - r'(\$(?P<operandImm0>\w\w*))|' + - r'(\$\{(?P<operandImm1>[^}]*)\}))') - lineMatch = lineRe.search(code) - while lineMatch != None: - statement = MicroOpStatement() - # Get a line and seperate it from the rest of the code - line = lineMatch.group("line") - orig_line = line - #print "Parsing line %s" % line - code = lineRe.sub('', code, 1) - - # Find the label, if any - labelMatch = labelRe.search(line) - if labelMatch != None: - statement.label = labelMatch.group("label") - #print "Found label %s." % statement.label - # Clear the label from the statement - line = labelRe.sub('', line, 1) - - # Find the class name which is roughly equivalent to the op name - classMatch = classRe.search(line) - if classMatch == None: - raise Exception, "Couldn't find class name in statement: %s" \ - % orig_line - else: - statement.className = classMatch.group("className") - #print "Found class name %s." % statement.className - - # Clear the class name from the statement - line = classRe.sub('', line, 1) - - #Find as many arguments as you can - statement.args = [] - opMatch = opRe.search(line) - while opMatch is not None: - statement.args.append({}) - # args is a list of dicts which collect different - # representations of operand values. Different forms might be - # needed in different places, for instance to replace a label - # with an offset. - for opType in ("operandLabel0", "operandReg0", "operandImm0", - "operandLabel1", "operandReg1", "operandImm1"): - if opMatch.group(opType): - statement.args[-1][opType[:-1]] = opMatch.group(opType) - if len(statement.args[-1]) == 0: - print "Problem parsing operand in statement: %s" \ - % orig_line - line = opRe.sub('', line, 1) - #print "Found operand %s." % statement.args[-1] - opMatch = opRe.search(line) - #print "Found operands", statement.args - - # Add this statement to our collection - statements.append(statement) - - # Get the next line - lineMatch = lineRe.search(code) - - # Decode the labels into displacements - - labels = {} - micropc = 0 - for statement in statements: - if statement.label: - labels[statement.label] = count - micropc += 1 - micropc = 0 - for statement in statements: - for arg in statement.args: - if arg.has_key("operandLabel"): - if not labels.has_key(arg["operandLabel"]): - raise Exception, "Unrecognized label: %s." % arg["operandLabel"] - # This is assuming that intra microcode branches go to - # the next micropc + displacement, or - # micropc + 1 + displacement. - arg["operandImm"] = labels[arg["operandLabel"]] - micropc - 1 - micropc += 1 - - if len(statements) == 0: - raise Exception, "Didn't find any microops in microcode: \n%s" % orig_code - - # If we can implement this instruction with exactly one microop, just - # use that directly. - if len(statements) == 1: - decode_block = "return %s;" % \ - statements[0].getAllocator('"' + name + '"') - return ('', '', decode_block, '') - else: - # Build a macroop to contain the sequence of microops we've - # been given. - return genMacroOp(name, Name, statements) + import sys + sys.path[0:0] = ["src/arch/x86/isa/"] + from insts import microcode + print microcode + from micro_asm import MicroAssembler, Rom_Macroop, Rom + mainRom = Rom('main ROM') + assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop) + macroopDict = assembler.assemble(microcode) }}; diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index f0aab7872..79ac4493a 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -55,25 +55,23 @@ // // Authors: Gabe Black -//The operand types a microop template can be specialized with -output header {{ - enum OperandType { - RegisterOperand, - ImmediateOperand - }; +let {{ + # This will be populated with mappings between microop mnemonics and + # the classes that represent them. + microopClasses = {} }}; //A class which is the base of all x86 micro ops. It provides a function to //set necessary flags appropriately. output header {{ - class X86MicroOpBase : public X86StaticInst + class X86MicroopBase : public X86StaticInst { protected: const char * instMnem; uint8_t opSize; uint8_t addrSize; - X86MicroOpBase(ExtMachInst _machInst, + X86MicroopBase(ExtMachInst _machInst, const char *mnem, const char *_instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, @@ -81,10 +79,10 @@ output header {{ X86StaticInst(mnem, _machInst, __opClass), instMnem(_instMnem) { - flags[IsMicroOp] = isMicro; + flags[IsMicroop] = isMicro; flags[IsDelayedCommit] = isDelayed; - flags[IsFirstMicroOp] = isFirst; - flags[IsLastMicroOp] = isLast; + flags[IsFirstMicroop] = isFirst; + flags[IsLastMicroop] = isLast; } std::string generateDisassembly(Addr pc, @@ -99,96 +97,40 @@ output header {{ }; }}; -// This sets up a class which is templated on the type of -// arguments a particular flavor of a microcode instruction -// can accept. It's parameters are specialized to create polymorphic -// behavior in microops. -def template BaseMicroOpTemplateDeclare {{ - template%(signature)s - class %(class_name)s; -}}; - -let {{ - def buildBaseMicroOpTemplate(Name, numParams): - assert(numParams > 0) - signature = "<" - signature += "int SignatureOperandTypeSpecifier0" - for count in xrange(1,numParams): - signature += \ - ", int SingatureOperandTypeSpecifier%d" % count - signature += ">" - subs = {"signature" : signature, "class_name" : Name} - return BaseMicroOpTemplateDeclare.subst(subs) -}}; +////////////////////////////////////////////////////////////////////////// +// +// Base class for the python representation of x86 microops +// +////////////////////////////////////////////////////////////////////////// let {{ - def buildMicroOpTemplateDict(*params): - signature = "<" - if len(params): - signature += params[0] - if len(params) > 1: - for param in params[1:]: - signature += ", %s" % param - signature += ">" - subs = {"param_dec" : "", "param_arg_dec" : "", - "param_init" : "", "signature" : signature} - for count in xrange(len(params)): - subs["param_dec"] += "uint64_t param%d;\n" % count - subs["param_arg_dec"] += ", uint64_t _param%d" % count - subs["param_init"] += ", param%d(_param%d)" % (count, count) - return subs -}}; - -// A tmeplate for building a specialized version of the microcode -// instruction which specifies which arguments it wants -def template MicroOpDeclare {{ - template<> - class %(class_name)s%(signature)s : public X86MicroOpBase - { - protected: - %(param_dec)s - void buildMe(); - - public: - %(class_name)s(ExtMachInst _machInst, - const char * instMnem, - bool isMicro, bool isDelayed, - bool isFirst, bool isLast - %(param_arg_dec)s); - - %(class_name)s(ExtMachInst _machInst, - const char * instMnem - %(param_arg_dec)s); - - %(BasicExecDeclare)s - }; + class X86Microop(object): + def __init__(self, name): + self.name = name + + # This converts a python bool into a C++ bool + def cppBool(self, val): + if val: + return "true" + else: + return "false" + + # This converts a list of python bools into + # a comma seperated list of C++ bools. + def microFlagsText(self, vals): + text = "" + for val in vals: + text += ", %s" % self.cppBool(val) + return text + + def getAllocator(self, mnemonic, *microFlags): + return 'new %s(machInst, %s)' % (self.className, mnemonic, self.microFlagsText(microFlags)) }}; -def template MicroOpConstructor {{ - - inline void %(class_name)s%(signature)s::buildMe() - { - %(constructor)s; - } - - inline %(class_name)s%(signature)s::%(class_name)s( - ExtMachInst machInst, const char * instMnem - %(param_arg_dec)s) : - %(base_class)s(machInst, "%(mnemonic)s", instMnem, - false, false, false, false, %(op_class)s) - %(param_init)s - { - buildMe(); - } +////////////////////////////////////////////////////////////////////////// +// +// FpOp Microop templates +// +////////////////////////////////////////////////////////////////////////// - inline %(class_name)s%(signature)s::%(class_name)s( - ExtMachInst machInst, const char * instMnem, - bool isMicro, bool isDelayed, bool isFirst, bool isLast - %(param_arg_dec)s) - : %(base_class)s(machInst, "%(mnemonic)s", instMnem, - isMicro, isDelayed, isFirst, isLast, %(op_class)s) - %(param_init)s - { - buildMe(); - } -}}; +//TODO Actually write an fp microop base class. diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa new file mode 100644 index 000000000..38b690e6a --- /dev/null +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -0,0 +1,423 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// LdStOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + + +// Load templates + +output header {{ + /** + * Base class for load and store ops + */ + class LdStOp : public X86MicroopBase + { + protected: + const uint8_t scale; + const RegIndex index; + const RegIndex base; + const uint64_t disp; + const uint8_t segment; + const RegIndex data; + const uint8_t dataSize; + const uint8_t addressSize; + + //Constructor + LdStOp(ExtMachInst _machInst, + const char * mnem, const char * _instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize, + OpClass __opClass) : + X86MicroopBase(machInst, mnem, _instMnem, + isMicro, isDelayed, isFirst, isLast, __opClass), + scale(_scale), index(_index), base(_base), + disp(_disp), segment(_segment), + data(_data), + dataSize(_dataSize), addressSize(_addressSize) + {} + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string LdStOp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + printReg(response, data); + response << ", "; + printSegment(response, segment); + ccprintf(response, ":[%d*", scale); + printReg(response, index); + response << " + "; + printReg(response, base); + ccprintf(response, " + %#x]", disp); + return response.str(); + } +}}; + +def template MicroLoadExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + Addr EA; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, 0); + if(fault == NoFault) + { + %(code)s; + } + if(fault == NoFault) + { + %(op_wb)s; + } + + return fault; + } +}}; + +def template MicroLoadInitiateAcc {{ + Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, + Trace::InstRecord * traceData) const + { + Fault fault = NoFault; + Addr EA; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, 0); + + return fault; + } +}}; + +def template MicroLoadCompleteAcc {{ + Fault %(class_name)s::completeAcc(PacketPtr pkt, + %(CPU_exec_context)s * xc, + Trace::InstRecord * traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + + Mem = pkt->get<typeof(Mem)>(); + %(code)s; + + if(fault == NoFault) + { + %(op_wb)s; + } + + return fault; + } +}}; + +// Store templates + +def template MicroStoreExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s * xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + Addr EA; + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + %(code)s; + + if(fault == NoFault) + { + fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, + EA, 0, 0); + } + if(fault == NoFault) + { + %(op_wb)s; + } + + return fault; + } +}}; + +def template MicroStoreInitiateAcc {{ + Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, + Trace::InstRecord * traceData) const + { + Fault fault = NoFault; + + Addr EA; + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + %(code)s; + + if(fault == NoFault) + { + fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, + EA, 0, 0); + } + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +def template MicroStoreCompleteAcc {{ + Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, + Trace::InstRecord * traceData) const + { + return NoFault; + } +}}; + +// Common templates + +//This delcares the initiateAcc function in memory operations +def template InitiateAccDeclare {{ + Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; +}}; + +//This declares the completeAcc function in memory operations +def template CompleteAccDeclare {{ + Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; +}}; + +def template MicroLdStOpDeclare {{ + class %(class_name)s : public %(base_class)s + { + protected: + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(BasicExecDeclare)s + + %(InitiateAccDeclare)s + + %(CompleteAccDeclare)s + }; +}}; + +def template MicroLdStOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, + _scale, _index, _base, + _disp, _segment, _data, + _dataSize, _addressSize, %(op_class)s) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, + _scale, _index, _base, + _disp, _segment, _data, + _dataSize, _addressSize, %(op_class)s) + { + buildMe(); + } +}}; + +let {{ + class LdStOp(X86Microop): + def __init__(self, data, segment, addr, disp): + self.data = data + [self.scale, self.index, self.base] = addr + self.disp = disp + self.segment = segment + self.dataSize = "env.dataSize" + self.addressSize = "env.addressSize" + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(scale)s, %(index)s, %(base)s, + %(disp)s, %(segment)s, %(data)s, + %(dataSize)s, %(addressSize)s)''' % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "scale" : self.scale, "index" : self.index, + "base" : self.base, + "disp" : self.disp, + "segment" : self.segment, "data" : self.data, + "dataSize" : self.dataSize, "addressSize" : self.addressSize} + return allocator +}}; + +let {{ + + # Make these empty strings so that concatenating onto + # them will always work. + header_output = "" + decoder_output = "" + exec_output = "" + + calculateEA = "EA = scale * Index + Base + disp;" + + def defineMicroLoadOp(mnemonic, code): + global header_output + global decoder_output + global exec_output + global microopClasses + Name = mnemonic + name = mnemonic.lower() + + # Build up the all register version of this micro op + iop = InstObjParams(name, Name, 'LdStOp', + {"code": code, "ea_code": calculateEA}) + header_output += MicroLdStOpDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroLoadExecute.subst(iop) + exec_output += MicroLoadInitiateAcc.subst(iop) + exec_output += MicroLoadCompleteAcc.subst(iop) + + class LoadOp(LdStOp): + def __init__(self, data, segment, addr, disp = 0): + super(LoadOp, self).__init__(data, segment, addr, disp) + self.className = Name + self.mnemonic = name + + microopClasses[name] = LoadOp + + defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') + + def defineMicroStoreOp(mnemonic, code): + global header_output + global decoder_output + global exec_output + global microopClasses + Name = mnemonic + name = mnemonic.lower() + + # Build up the all register version of this micro op + iop = InstObjParams(name, Name, 'LdStOp', + {"code": code, "ea_code": calculateEA}) + header_output += MicroLdStOpDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroStoreExecute.subst(iop) + exec_output += MicroStoreInitiateAcc.subst(iop) + exec_output += MicroStoreCompleteAcc.subst(iop) + + class StoreOp(LdStOp): + def __init__(self, data, addr, segment): + super(LoadOp, self).__init__(data, addr, segment) + self.className = Name + self.mnemonic = name + + microopClasses[name] = StoreOp + + defineMicroLoadOp('St', 'Mem = Data;') +}}; + diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa new file mode 100644 index 000000000..141d7523f --- /dev/null +++ b/src/arch/x86/isa/microops/limmop.isa @@ -0,0 +1,170 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// LIMMOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + +def template MicroLimmOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + %(op_decl)s; + %(op_rd)s; + %(code)s; + %(op_wb)s; + return NoFault; + } +}}; + +def template MicroLimmOpDeclare {{ + class %(class_name)s : public X86MicroopBase + { + protected: + const RegIndex dest; + const uint64_t imm; + void buildMe(); + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _dest, uint64_t _imm); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + RegIndex _dest, uint64_t _imm); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroLimmOpDisassembly {{ + std::string %(class_name)s::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + printReg(response, dest); + response << ", "; + ccprintf(response, "%#x", imm); + return response.str(); + } +}}; + +def template MicroLimmOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + RegIndex _dest, uint64_t _imm) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s), + dest(_dest), imm(_imm) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _dest, uint64_t _imm) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s), + dest(_dest), imm(_imm) + { + buildMe(); + } +}}; + +let {{ + class LimmOp(X86Microop): + def __init__(self, dest, imm): + self.className = "Limm" + self.mnemonic = "limm" + self.dest = dest + self.imm = imm + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(dest)s, %(imm)s)''' % { + "class_name" : self.className, + "mnemonic" : self.mnemonic, + "flags" : self.microFlagsText(microFlags), + "dest" : self.dest, "imm" : self.imm } + return allocator + + microopClasses["limm"] = LimmOp +}}; + +let {{ + # Build up the all register version of this micro op + iop = InstObjParams("limm", "Limm", 'X86MicroopBase', + {"code" : "DestReg = imm;"}) + header_output += MicroLimmOpDeclare.subst(iop) + decoder_output += MicroLimmOpConstructor.subst(iop) + decoder_output += MicroLimmOpDisassembly.subst(iop) + exec_output += MicroLimmOpExecute.subst(iop) +}}; diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa index d877152eb..50c9ac498 100644 --- a/src/arch/x86/isa/microops/microops.isa +++ b/src/arch/x86/isa/microops/microops.isa @@ -56,8 +56,14 @@ //Common microop stuff ##include "base.isa" -//A microop that generates a specified fault -##include "fault.isa" +//Register microop definitions +##include "regop.isa" -//Integer microop definitions -##include "int.isa" +//Load immediate microop definition +##include "limmop.isa" + +//Load/store microop definitions +##include "ldstop.isa" + +//Miscellaneous microop definitions +##include "specop.isa" diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa new file mode 100644 index 000000000..d5fb25cb5 --- /dev/null +++ b/src/arch/x86/isa/microops/regop.isa @@ -0,0 +1,413 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// RegOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + +output header {{ + /** + * Base classes for RegOps which provides a generateDisassembly method. + */ + class RegOp : public X86MicroopBase + { + protected: + const RegIndex src1; + const RegIndex src2; + const RegIndex dest; + const bool setStatus; + const uint8_t dataSize; + const uint8_t ext; + + // Constructor + RegOp(ExtMachInst _machInst, + const char *mnem, const char *_instMnem, + bool isMicro, bool isDelayed, + bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext, + OpClass __opClass) : + X86MicroopBase(_machInst, mnem, _instMnem, + isMicro, isDelayed, isFirst, isLast, + __opClass), + src1(_src1), src2(_src2), dest(_dest), + setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + }; + + class RegOpImm : public X86MicroopBase + { + protected: + const RegIndex src1; + const uint8_t imm8; + const RegIndex dest; + const bool setStatus; + const uint8_t dataSize; + const uint8_t ext; + + // Constructor + RegOpImm(ExtMachInst _machInst, + const char * mnem, const char *_instMnem, + bool isMicro, bool isDelayed, + bool isFirst, bool isLast, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext, + OpClass __opClass) : + X86MicroopBase(_machInst, mnem, _instMnem, + isMicro, isDelayed, isFirst, isLast, + __opClass), + src1(_src1), imm8(_imm8), dest(_dest), + setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string RegOp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + printReg(response, dest); + response << ", "; + printReg(response, src1); + response << ", "; + printReg(response, src2); + return response.str(); + } + + std::string RegOpImm::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + printReg(response, dest); + response << ", "; + printReg(response, src1); + ccprintf(response, ", %#x", imm8); + return response.str(); + } +}}; + +def template MicroRegOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + + //Write the resulting state to the execution context + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +def template MicroRegOpImmExecute {{ + Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + + //Write the resulting state to the execution context + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +def template MicroRegOpDeclare {{ + class %(class_name)s : public %(base_class)s + { + protected: + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroRegOpImmDeclare {{ + + class %(class_name)sImm : public %(base_class)s + { + protected: + void buildMe(); + + public: + %(class_name)sImm(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(class_name)sImm(ExtMachInst _machInst, + const char * instMnem, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroRegOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, + _src1, _src2, _dest, _setStatus, _dataSize, _ext, + %(op_class)s) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, + _src1, _src2, _dest, _setStatus, _dataSize, _ext, + %(op_class)s) + { + buildMe(); + } +}}; + +def template MicroRegOpImmConstructor {{ + + inline void %(class_name)sImm::buildMe() + { + %(constructor)s; + } + + inline %(class_name)sImm::%(class_name)sImm( + ExtMachInst machInst, const char * instMnem, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, + _src1, _imm8, _dest, _setStatus, _dataSize, _ext, + %(op_class)s) + { + buildMe(); + } + + inline %(class_name)sImm::%(class_name)sImm( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, + _src1, _imm8, _dest, _setStatus, _dataSize, _ext, + %(op_class)s) + { + buildMe(); + } +}}; + +let {{ + class RegOp(X86Microop): + def __init__(self, dest, src1, src2): + self.dest = dest + self.src1 = src1 + self.src2 = src2 + self.setStatus = False + self.dataSize = "env.dataSize" + self.ext = 0 + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(src1)s, %(src2)s, %(dest)s, + %(setStatus)s, %(dataSize)s, %(ext)s)''' % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "src2" : self.src2, + "dest" : self.dest, + "setStatus" : self.cppBool(self.setStatus), + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator + + class RegOpImm(X86Microop): + def __init__(self, dest, src1, imm8): + self.dest = dest + self.src1 = src1 + self.imm8 = imm8 + self.setStatus = False + self.dataSize = "env.dataSize" + self.ext = 0 + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(src1)s, %(imm8)s, %(dest)s, + %(setStatus)s, %(dataSize)s, %(ext)s)''' % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "imm8" : self.imm8, + "dest" : self.dest, + "setStatus" : self.cppBool(self.setStatus), + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator +}}; + +let {{ + + # Make these empty strings so that concatenating onto + # them will always work. + header_output = "" + decoder_output = "" + exec_output = "" + + def defineMicroRegOp(mnemonic, code): + global header_output + global decoder_output + global exec_output + global microopClasses + Name = mnemonic + name = mnemonic.lower() + + # Find op2 in each of the instruction definitions. Create two versions + # of the code, one with an integer operand, and one with an immediate + # operand. + matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") + regCode = matcher.sub("SrcReg2", code) + immCode = matcher.sub("imm8", code) + + # Build up the all register version of this micro op + iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode}) + header_output += MicroRegOpDeclare.subst(iop) + decoder_output += MicroRegOpConstructor.subst(iop) + exec_output += MicroRegOpExecute.subst(iop) + + class RegOpChild(RegOp): + def __init__(self, dest, src1, src2): + super(RegOpChild, self).__init__(dest, src1, src2) + self.className = Name + self.mnemonic = name + + microopClasses[name] = RegOpChild + + # Build up the immediate version of this micro op + iop = InstObjParams(name + "i", Name, + 'RegOpImm', {"code" : immCode}) + header_output += MicroRegOpImmDeclare.subst(iop) + decoder_output += MicroRegOpImmConstructor.subst(iop) + exec_output += MicroRegOpImmExecute.subst(iop) + + class RegOpImmChild(RegOpImm): + def __init__(self, dest, src1, imm): + super(RegOpImmChild, self).__init__(dest, src1, imm) + self.className = Name + "Imm" + self.mnemonic = name + "i" + + microopClasses[name + "i"] = RegOpImmChild + + defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF + defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') + defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF + defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF + defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') + defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF + defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') + defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg + defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') + +}}; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa new file mode 100644 index 000000000..96fdf1c5e --- /dev/null +++ b/src/arch/x86/isa/microops/specop.isa @@ -0,0 +1,125 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// Fault Microop +// +////////////////////////////////////////////////////////////////////////// + +def template MicroFaultExecute {{ + Fault %(class_name)s ::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + //Return the fault we were constructed with + return fault; + } +}}; + +def template MicroFaultDeclare {{ + class %(class_name)s : public X86MicroopBase + { + protected: + Fault fault; + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + Fault _fault); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + Fault _fault); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroFaultConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, Fault _fault) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s), fault(_fault) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + Fault _fault) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s), + fault(_fault) + { + buildMe(); + } +}}; + +let {{ + # This microop takes in a single parameter, a fault to return. + iop = InstObjParams("fault", "GenFault", 'X86MicroopBase', {"code" : ""}) + header_output += MicroFaultDeclare.subst(iop) + decoder_output += MicroFaultConstructor.subst(iop) + exec_output += MicroFaultExecute.subst(iop) +}}; diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index af469ab3d..b2ac17d66 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -96,7 +96,12 @@ def operand_types {{ }}; def operands {{ - 'IntRegOp0': ('IntReg', 'udw', 'param0', 'IsInteger', 1), - 'IntRegOp1': ('IntReg', 'udw', 'param1', 'IsInteger', 2), - 'IntRegOp2': ('IntReg', 'udw', 'param2', 'IsInteger', 2), + 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1), + 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2), + 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3), + 'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4), + 'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5), + 'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6), + 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), + 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index ff92c3551..bb2be47d9 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -66,24 +66,26 @@ let {{ # vals is a dict which matches case values with what should be decoded to. # builder is called on the exploded contents of "vals" values to generate # whatever code should be used. - def doSplitDecode(name, Name, builder, switchVal, vals, default = None): + def doSplitDecode(builder, switchVal, vals, default = None): blocks = OutputBlocks() - blocks.decode_block += 'switch(%s) {\n' % switchVal + blocks.decode_block = 'switch(%s) {\n' % switchVal for (val, todo) in vals.items(): - built = builder(name, Name, *todo) - built.decode_block = '\tcase %s: %s\n' % (val, built.decode_block) - blocks.append(built) + new_blocks = builder(*todo) + new_blocks.decode_block = \ + '\tcase %s: %s\n' % (val, new_blocks.decode_block) + blocks.append(new_blocks) if default: - built = builder(name, Name, *default) - built.decode_block = '\tdefault: %s\n' % built.decode_block - blocks.append(built) + new_blocks = builder(*default) + new_blocks.decode_block = \ + '\tdefault: %s\n' % new_blocks.decode_block + blocks.append(new_blocks) blocks.decode_block += '}\n' return blocks }}; let {{ class OpType(object): - parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Za-z0-9][A-Za-z0-9]*))") + parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Z0-9]*)(?P<rsize>[a-z]*))") def __init__(self, opTypeString): match = OpType.parser.search(opTypeString) if match == None: @@ -91,74 +93,78 @@ let {{ self.reg = match.group("reg") self.tag = match.group("tag") self.size = match.group("size") + self.rsize = match.group("rsize") + + ModRMRegIndex = "(MODRM_REG | (REX_R << 3))" + ModRMRMIndex = "(MODRM_RM | (REX_B << 3))" # This function specializes the given piece of code to use a particular - # set of argument types described by "opTypes". These are "implemented" - # in reverse order. - def specializeInst(name, Name, code, opTypes): - opNum = len(opTypes) - 1 + # set of argument types described by "opTypes". + def specializeInst(Name, opTypes, env): + # print "Specializing %s with opTypes %s" % (Name, opTypes) while len(opTypes): - # print "Building a composite op with tags", opTypes - # print "And code", code - opNum = len(opTypes) - 1 - # A regular expression to find the operand placeholders we're - # interested in. - opRe = re.compile("\\^(?P<operandNum>%d)(?=[^0-9]|$)" % opNum) - - # Parse the operand type strign we're working with - opType = OpType(opTypes[opNum]) + # Parse the operand type string we're working with + opType = OpType(opTypes[0]) if opType.reg: #Figure out what to do with fixed register operands - if opType.reg in ("Ax", "Bx", "Cx", "Dx"): - code = opRe.sub("%%{INTREG_R%s}" % opType.reg.upper(), code) - elif opType.reg == "Al": - # We need a way to specify register width - code = opRe.sub("%{INTREG_RAX}", code) + #This is the index to use, so we should stick it some place. + if opType.reg in ("A", "B", "C", "D"): + env.addReg("INTREG_R%sX" % opType.reg) else: - print "Didn't know how to encode fixed register %s!" % opType.reg + env.addReg("INTREG_R%s" % opType.reg) + if opType.size: + if opType.rsize in ("l", "h", "b"): + print "byte" + elif opType.rsize == "x": + print "word" + else: + print "Didn't recognize fixed register size %s!" % opType.rsize + Name += "_R" elif opType.tag == None or opType.size == None: raise Exception, "Problem parsing operand tag: %s" % opType.tag elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"): # Use the "reg" field of the ModRM byte to select the register - code = opRe.sub("%{(uint8_t)MODRM_REG}", code) + env.addReg(ModRMRegIndex) + Name += "_R" elif opType.tag in ("E", "Q", "W"): # This might refer to memory or to a register. We need to # divide it up farther. - regCode = opRe.sub("%{(uint8_t)MODRM_RM}", code) regTypes = copy.copy(opTypes) - regTypes.pop(-1) + regTypes.pop(0) + regEnv = copy.copy(env) + regEnv.addReg(ModRMRMIndex) + regName = Name + "_R" # This needs to refer to memory, but we'll fill in the details # later. It needs to take into account unaligned memory # addresses. - code = "GenFault ${new UnimpInstFault}\n" + code - memCode = opRe.sub("%0", code) memTypes = copy.copy(opTypes) - memTypes.pop(-1) - return doSplitDecode(name, Name, specializeInst, "MODRM_MOD", - {"3" : (regCode, regTypes)}, (memCode, memTypes)) + memTypes.pop(0) + memEnv = copy.copy(env) + memName = Name + "_M" + print "%0" + return doSplitDecode(specializeInst, "MODRM_MOD", + {"3" : (regName, regTypes, regEnv)}, + (memName, memTypes, memEnv)) elif opType.tag in ("I", "J"): - # Immediates are already in the instruction, so don't leave in - # those parameters - code = opRe.sub("${IMMEDIATE}", code) + # Immediates + Name += "_I" elif opType.tag == "M": # This needs to refer to memory, but we'll fill in the details # later. It needs to take into account unaligned memory # addresses. - code = "GenFault ${new UnimpInstFault}\n" + code - code = opRe.sub("%0", code) + print "%0" + Name += "_M" elif opType.tag in ("PR", "R", "VR"): # There should probably be a check here to verify that mod # is equal to 11b - code = opRe.sub("%{(uint8_t)MODRM_RM}", code) + env.addReg(ModRMRMIndex) + Name += "_R" else: raise Exception, "Unrecognized tag %s." % opType.tag - opTypes.pop(-1) + opTypes.pop(0) - # At this point, we've built up "code" to have all the necessary extra - # instructions needed to implement whatever types of operands were - # specified. Now we'll assemble it it into a StaticInst. - blocks = OutputBlocks() - blocks.append(assembleMicro(name, Name, code)) - return blocks + # Generate code to return a macroop of the given name which will + # operate in the "emulation environment" env + return genMacroop(Name, env) }}; diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 5a625f741..4c02ee35e 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -81,8 +81,8 @@ namespace X86ISA // These enumerate all the registers for dependence tracking. enum DependenceTags { - //The number of microcode registers needs to be added to this - FP_Base_DepTag = 16, + //There are 16 microcode registers at the moment + FP_Base_DepTag = 32, Ctrl_Base_DepTag = FP_Base_DepTag + //mmx/x87 registers @@ -93,7 +93,7 @@ namespace X86ISA // semantically meaningful register indices //There is no such register in X86 - const int ZeroReg = 0; + const int ZeroReg = NUM_INTREGS; const int StackPointerReg = INTREG_RSP; //X86 doesn't seem to have a link register const int ReturnAddressReg = 0; diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc index 573012ee6..3ed18aeb2 100644 --- a/src/arch/x86/predecoder.cc +++ b/src/arch/x86/predecoder.cc @@ -62,6 +62,24 @@ namespace X86ISA { + void Predecoder::reset() + { + origPC = basePC + offset; + DPRINTF(Predecoder, "Setting origPC to %#x\n", origPC); + emi.rex = 0; + emi.legacy = 0; + emi.opcode.num = 0; + + immediateCollected = 0; + emi.immediate = 0; + displacementCollected = 0; + emi.displacement = 0; + + emi.modRM = 0; + emi.sib = 0; + emi.mode = 0; + } + void Predecoder::process() { //This function drives the predecoder state machine. @@ -78,6 +96,9 @@ namespace X86ISA uint8_t nextByte = getNextByte(); switch(state) { + case ResetState: + reset(); + state = PrefixState; case PrefixState: state = doPrefixState(nextByte); break; @@ -150,7 +171,6 @@ namespace X86ISA emi.rex = nextByte; break; case 0: - emi.opcode.num = 0; nextState = OpcodeState; break; default: @@ -188,55 +208,50 @@ namespace X86ISA DPRINTF(Predecoder, "Found opcode %#x.\n", nextByte); emi.opcode.op = nextByte; - //Prepare for any immediate/displacement we might need - immediateCollected = 0; - emi.immediate = 0; - displacementCollected = 0; - emi.displacement = 0; - //Figure out the effective operand size. This can be overriden to //a fixed value at the decoder level. + int logOpSize; if(/*FIXME long mode*/1) { - if(emi.rex && emi.rex.w) - emi.opSize = 3; // 64 bit operand size + if(emi.rex.w) + logOpSize = 3; // 64 bit operand size else if(emi.legacy.op) - emi.opSize = 1; // 16 bit operand size + logOpSize = 1; // 16 bit operand size else - emi.opSize = 2; // 32 bit operand size + logOpSize = 2; // 32 bit operand size } else if(/*FIXME default 32*/1) { if(emi.legacy.op) - emi.opSize = 1; // 16 bit operand size + logOpSize = 1; // 16 bit operand size else - emi.opSize = 2; // 32 bit operand size + logOpSize = 2; // 32 bit operand size } else // 16 bit default operand size { if(emi.legacy.op) - emi.opSize = 2; // 32 bit operand size + logOpSize = 2; // 32 bit operand size else - emi.opSize = 1; // 16 bit operand size + logOpSize = 1; // 16 bit operand size } //Figure out how big of an immediate we'll retreive based //on the opcode. int immType = ImmediateType[emi.opcode.num - 1][nextByte]; - immediateSize = SizeTypeToSize[emi.opSize - 1][immType]; + immediateSize = SizeTypeToSize[logOpSize - 1][immType]; + + //Set the actual op size + emi.opSize = 1 << logOpSize; //Determine what to expect next if (UsesModRM[emi.opcode.num - 1][nextByte]) { nextState = ModRMState; } else { - //If there's no modRM byte, set it to 0 so we can detect - //that later. - emi.modRM = 0; if(immediateSize) { nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } } } @@ -282,7 +297,7 @@ namespace X86ISA nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } //The ModRM byte is consumed no matter what consumeByte(); @@ -304,7 +319,7 @@ namespace X86ISA nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } return nextState; } @@ -344,7 +359,7 @@ namespace X86ISA nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } } else @@ -375,12 +390,19 @@ namespace X86ISA //Instructions which use true 64 bit immediates won't be //affected, and instructions that use true 32 bit immediates //won't notice. - if(immediateSize == 4) + switch(immediateSize) + { + case 4: emi.immediate = sext<32>(emi.immediate); + break; + case 1: + emi.immediate = sext<8>(emi.immediate); + } + DPRINTF(Predecoder, "Collected immediate %#x.\n", emi.immediate); emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } else nextState = ImmediateState; diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index 6562ab9f5..3c858f061 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -60,6 +60,8 @@ #include "arch/x86/types.hh" #include "base/bitfield.hh" +#include "base/misc.hh" +#include "base/trace.hh" #include "sim/host.hh" class ThreadContext; @@ -81,6 +83,8 @@ namespace X86ISA MachInst fetchChunk; //The pc of the start of fetchChunk Addr basePC; + //The pc the current instruction started at + Addr origPC; //The offset into fetchChunk of current processing int offset; //The extended machine instruction being generated @@ -130,6 +134,8 @@ namespace X86ISA outOfBytes = true; } + void reset(); + //State machine state protected: //Whether or not we're out of bytes @@ -144,6 +150,7 @@ namespace X86ISA int immediateCollected; enum State { + ResetState, PrefixState, OpcodeState, ModRMState, @@ -166,10 +173,13 @@ namespace X86ISA public: Predecoder(ThreadContext * _tc) : - tc(_tc), basePC(0), offset(0), + tc(_tc), basePC(0), origPC(0), offset(0), outOfBytes(true), emiIsReady(false), - state(PrefixState) - {} + state(ResetState) + { + emi.mode.mode = LongMode; + emi.mode.submode = SixtyFourBitMode; + } ThreadContext * getTC() { @@ -185,9 +195,9 @@ namespace X86ISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr currPC, Addr off, MachInst data) + void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data) { - basePC = currPC; + basePC = fetchPC; offset = off; fetchChunk = data; assert(off < sizeof(MachInst)); @@ -195,13 +205,6 @@ namespace X86ISA process(); } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(basePC + sizeof(machInst), 0, machInst); - } - bool needMoreBytes() { return outOfBytes; @@ -219,6 +222,15 @@ namespace X86ISA emiIsReady = false; return emi; } + + int getInstSize() + { + DPRINTF(Predecoder, + "Calculating the instruction size: " + "basePC: %#x offset: %#x origPC: %#x\n", + basePC, offset, origPC); + return basePC + offset - origPC; + } }; }; diff --git a/src/arch/x86/predecoder_tables.cc b/src/arch/x86/predecoder_tables.cc index 38b9c57a3..6fe54b719 100644 --- a/src/arch/x86/predecoder_tables.cc +++ b/src/arch/x86/predecoder_tables.cc @@ -170,7 +170,7 @@ namespace X86ISA // noimm byte word dword qword oword vword zword enter pointer {0, 1, 2, 4, 8, 16, 2, 2, 3, 4 }, //16 bit {0, 1, 2, 4, 8, 16, 4, 4, 3, 6 }, //32 bit - {0, 1, 2, 4, 8, 16, 4, 8, 3, 0 } //64 bit + {0, 1, 2, 4, 8, 16, 8, 4, 3, 0 } //64 bit }; //This table determines the immediate type. The first index is the diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc index 568eb1d94..f54f531e2 100644 --- a/src/arch/x86/regfile.cc +++ b/src/arch/x86/regfile.cc @@ -117,7 +117,8 @@ void RegFile::setNextPC(Addr val) Addr RegFile::readNextNPC() { - return nextRip + sizeof(MachInst); + //There's no way to know how big the -next- instruction will be. + return nextRip + 1; } void RegFile::setNextNPC(Addr val) diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 022f20ee5..298dff80b 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -120,6 +120,24 @@ namespace X86ISA Bitfield<2,0> bottom3; EndBitUnion(Opcode) + BitUnion8(OperatingMode) + Bitfield<3> mode; + Bitfield<2,0> submode; + EndBitUnion(OperatingMode) + + enum X86Mode { + LongMode, + LegacyMode + }; + + enum X86SubMode { + SixtyFourBitMode, + CompatabilityMode, + ProtectedMode, + Virtual8086Mode, + RealMode + }; + //The intermediate structure the x86 predecoder returns. struct ExtMachInst { @@ -149,7 +167,13 @@ namespace X86ISA //The effective operand size. uint8_t opSize; - //The + //The effective address size. + uint8_t addrSize; + //The effective stack size. + uint8_t stackSize; + + //Mode information + OperatingMode mode; }; inline static std::ostream & @@ -191,6 +215,14 @@ namespace X86ISA return false; if(emi1.displacement != emi2.displacement) return false; + if(emi1.mode != emi2.mode) + return false; + if(emi1.opSize != emi2.opSize) + return false; + if(emi1.addrSize != emi2.addrSize) + return false; + if(emi1.stackSize != emi2.stackSize) + return false; return true; } diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 1c98e7fbc..3f3f1cca3 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -79,7 +79,8 @@ namespace __hash_namespace { ((uint64_t)emi.opcode.prefixB << 8) | ((uint64_t)emi.opcode.op)) ^ emi.immediate ^ emi.displacement ^ - emi.opSize; + emi.mode ^ + emi.opSize ^ emi.addrSize ^ emi.stackSize; }; }; } diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index fa54c24e9..e45d62f8f 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -60,8 +60,7 @@ namespace X86ISA { - //XXX This will definitely need to be something larger in the future. - const int NumMicroIntRegs = 0; + const int NumMicroIntRegs = 16; const int NumMMXRegs = 8; const int NumXMMRegs = 16; diff --git a/src/base/SConscript b/src/base/SConscript index cc9d06a0e..ca68bfb60 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -57,7 +57,8 @@ Source('circlebuf.cc') Source('cprintf.cc') Source('crc.cc') Source('fast_alloc.cc') -Source('fenv.c') +if env['USE_FENV']: + Source('fenv.c') Source('fifo_buffer.cc') Source('hostinfo.cc') Source('hybrid_pred.cc') diff --git a/src/base/fenv.c b/src/base/fenv.c index 269913a60..2ec2f796f 100644 --- a/src/base/fenv.c +++ b/src/base/fenv.c @@ -39,7 +39,7 @@ static const int m5_round_ops[] = {FE_DOWNWARD, FE_TONEAREST, FE_TOWARDZERO, FE void m5_fesetround(int rm) { - assert(rm > 0 && rm < 4); + assert(rm >= 0 && rm < 4); fesetround(m5_round_ops[rm]); } diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index 8f157da28..f76ea593b 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -31,23 +31,14 @@ #include <string> -// Because of the -Wundef flag we have to do this -#define __LIBELF_INTERNAL__ 0 -#define __LIBELF_NEED_LINK_H 0 -#define __LIBELF_SYMBOL_VERSIONS 0 - #include "gelf.h" #include "base/loader/elf_object.hh" -#include "base/misc.hh" - #include "base/loader/symtab.hh" - +#include "base/misc.hh" #include "base/trace.hh" // for DPRINTF - #include "sim/byteswap.hh" - using namespace std; ObjectFile * diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 761b30c2b..8d3f53d4c 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -2094,9 +2094,13 @@ class UnaryNode : public Node return vresult; } - Result total() const { - Op op; - return op(l->total()); + Result total() const + { + const VResult &vec = this->result(); + Result total = 0; + for (int i = 0; i < size(); i++) + total += vec[i]; + return total; } virtual size_t size() const { return l->size(); } @@ -2149,9 +2153,13 @@ class BinaryNode : public Node return vresult; } - Result total() const { - Op op; - return op(l->total(), r->total()); + Result total() const + { + const VResult &vec = this->result(); + Result total = 0; + for (int i = 0; i < size(); i++) + total += vec[i]; + return total; } virtual size_t size() const { diff --git a/src/python/m5/objects/BaseCPU.py b/src/cpu/BaseCPU.py index 986220c3f..6c2aace51 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -1,12 +1,45 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.SimObject import SimObject from m5.params import * from m5.proxy import * from m5 import build_env -from AlphaTLB import AlphaDTB, AlphaITB -from SparcTLB import SparcDTB, SparcITB from Bus import Bus import sys +if build_env['FULL_SYSTEM']: + if build_env['TARGET_ISA'] == 'alpha': + from AlphaTLB import AlphaDTB, AlphaITB + + if build_env['TARGET_ISA'] == 'sparc': + from SparcTLB import SparcDTB, SparcITB + class BaseCPU(SimObject): type = 'BaseCPU' abstract = True diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py new file mode 100644 index 000000000..ad2d1b87b --- /dev/null +++ b/src/cpu/FuncUnit.py @@ -0,0 +1,46 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.SimObject import SimObject +from m5.params import * + +class OpClass(Enum): + vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', + 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', + 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] + +class OpDesc(SimObject): + type = 'OpDesc' + issueLat = Param.Int(1, "cycles until another can be issued") + opClass = Param.OpClass("type of operation") + opLat = Param.Int(1, "cycles until result is available") + +class FUDesc(SimObject): + type = 'FUDesc' + count = Param.Int("number of these FU's available") + opList = VectorParam.OpDesc("operation classes for this FU type") diff --git a/src/cpu/IntrControl.py b/src/cpu/IntrControl.py new file mode 100644 index 000000000..eb4b1696b --- /dev/null +++ b/src/cpu/IntrControl.py @@ -0,0 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +class IntrControl(SimObject): + type = 'IntrControl' + sys = Param.System(Parent.any, "the system we are part of") diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 1c2278f6f..cce13a072 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -103,6 +103,9 @@ env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) # and one of these are not being used. CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] +SimObject('BaseCPU.py') +SimObject('FuncUnit.py') + Source('activity.cc') Source('base.cc') Source('cpuevent.cc') @@ -116,6 +119,8 @@ Source('simple_thread.cc') Source('thread_state.cc') if env['FULL_SYSTEM']: + SimObject('IntrControl.py') + Source('intr_control.cc') Source('profile.cc') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 4dccee0d3..078ae1283 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -179,10 +179,9 @@ BaseCPU::BaseCPU(Params *p) if (p->functionTraceStart == 0) { functionTracingEnabled = true; } else { - Event *e = - new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, - true); - e->schedule(p->functionTraceStart); + new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, + p->functionTraceStart, + true); } } #if FULL_SYSTEM diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 3e2b0f03e..9b87f2e8a 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -162,7 +162,7 @@ Trace::InstRecord::dump() static int fd = 0; //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { if(!cosim_listener) { @@ -245,7 +245,7 @@ Trace::InstRecord::dump() #if 0 //THE_ISA == SPARC_ISA //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { static uint64_t regs[32] = { 0, 0, 0, 0, 0, 0, 0, 0, @@ -432,7 +432,7 @@ Trace::InstRecord::dump() setupSharedData(); // We took a trap on a micro-op... - if (wasMicro && !staticInst->isMicroOp()) + if (wasMicro && !staticInst->isMicroop()) { // let's skip comparing this tick while (!compared) @@ -444,13 +444,13 @@ Trace::InstRecord::dump() wasMicro = false; } - if (staticInst->isLastMicroOp()) + if (staticInst->isLastMicroop()) wasMicro = false; - else if (staticInst->isMicroOp()) + else if (staticInst->isMicroop()) wasMicro = true; - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { while (!compared) { if (shared_data->flags == OWN_M5) { m5Pc = PC & TheISA::PAddrImplMask; @@ -650,12 +650,13 @@ Trace::InstRecord::dump() << endl; predecoder.setTC(thread); - predecoder.moreBytes(m5Pc, 0, shared_data->instruction); + predecoder.moreBytes(m5Pc, m5Pc, 0, + shared_data->instruction); assert(predecoder.extMachInstReady()); StaticInstPtr legionInst = - StaticInst::decode(predecoder.getExtMachInst()); + StaticInst::decode(predecoder.getExtMachInst(), lgnPc); outs << setfill(' ') << setw(15) << " Legion Inst: " << "0x" << setw(8) << setfill('0') << hex diff --git a/src/cpu/memtest/MemTest.py b/src/cpu/memtest/MemTest.py new file mode 100644 index 000000000..381519972 --- /dev/null +++ b/src/cpu/memtest/MemTest.py @@ -0,0 +1,52 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +from m5 import build_env + +class MemTest(SimObject): + type = 'MemTest' + max_loads = Param.Counter("number of loads to execute") + atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n") + memory_size = Param.Int(65536, "memory size") + percent_dest_unaligned = Param.Percent(50, + "percent of copy dest address that are unaligned") + percent_reads = Param.Percent(65, "target read percentage") + percent_source_unaligned = Param.Percent(50, + "percent of copy source address that are unaligned") + percent_functional = Param.Percent(50, "percent of access that are functional") + percent_uncacheable = Param.Percent(10, + "target uncacheable percentage") + progress_interval = Param.Counter(1000000, + "progress report interval (in accesses)") + trace_addr = Param.Addr(0, "address to trace") + + test = Port("Port to the memory system to test") + functional = Port("Port to the functional memory used for verification") diff --git a/src/cpu/memtest/SConscript b/src/cpu/memtest/SConscript index 7b4d6d2c5..1f6621a4c 100644 --- a/src/cpu/memtest/SConscript +++ b/src/cpu/memtest/SConscript @@ -31,4 +31,6 @@ Import('*') if 'O3CPU' in env['CPU_MODELS']: + SimObject('MemTest.py') + Source('memtest.cc') diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index 607cf1066..15774904a 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -190,14 +190,8 @@ MemTest::init() blockAddrMask = blockSize - 1; traceBlockAddr = blockAddr(traceBlockAddr); - // set up intial memory contents here - - cachePort.memsetBlob(baseAddr1, 1, size); - funcPort.memsetBlob(baseAddr1, 1, size); - cachePort.memsetBlob(baseAddr2, 2, size); - funcPort.memsetBlob(baseAddr2, 2, size); - cachePort.memsetBlob(uncacheAddr, 3, size); - funcPort.memsetBlob(uncacheAddr, 3, size); + // initial memory contents for both physical memory and functional + // memory should be 0; no need to initialize them. } static void @@ -267,7 +261,7 @@ MemTest::completeRequest(PacketPtr pkt) break; */ default: - panic("invalid command"); + panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt()); } if (blockAddr(req->getPaddr()) == traceBlockAddr) { diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh index 264309fd7..123ee2a6c 100644 --- a/src/cpu/memtest/memtest.hh +++ b/src/cpu/memtest/memtest.hh @@ -115,8 +115,8 @@ class MemTest : public MemObject virtual void recvRetry(); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } }; CpuPort cachePort; diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py new file mode 100644 index 000000000..4f07f9867 --- /dev/null +++ b/src/cpu/o3/FUPool.py @@ -0,0 +1,40 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.SimObject import SimObject +from m5.params import * +from FuncUnit import * +from FuncUnitConfig import * + +class FUPool(SimObject): + type = 'FUPool' + FUList = VectorParam.FUDesc("list of FU's for this pool") + +class DefaultFUPool(FUPool): + FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), + WritePort(), RdWrPort(), IprPort() ] diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py new file mode 100644 index 000000000..954381f86 --- /dev/null +++ b/src/cpu/o3/FuncUnitConfig.py @@ -0,0 +1,69 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.SimObject import SimObject +from m5.params import * +from FuncUnit import * + +class IntALU(FUDesc): + opList = [ OpDesc(opClass='IntAlu') ] + count = 6 + +class IntMultDiv(FUDesc): + opList = [ OpDesc(opClass='IntMult', opLat=3), + OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ] + count=2 + +class FP_ALU(FUDesc): + opList = [ OpDesc(opClass='FloatAdd', opLat=2), + OpDesc(opClass='FloatCmp', opLat=2), + OpDesc(opClass='FloatCvt', opLat=2) ] + count = 4 + +class FP_MultDiv(FUDesc): + opList = [ OpDesc(opClass='FloatMult', opLat=4), + OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), + OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] + count = 2 + +class ReadPort(FUDesc): + opList = [ OpDesc(opClass='MemRead') ] + count = 0 + +class WritePort(FUDesc): + opList = [ OpDesc(opClass='MemWrite') ] + count = 0 + +class RdWrPort(FUDesc): + opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] + count = 4 + +class IprPort(FUDesc): + opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ] + count = 1 + diff --git a/src/python/m5/objects/O3CPU.py b/src/cpu/o3/O3CPU.py index 5fba4e96f..e031faefa 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -1,10 +1,40 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + from m5.params import * from m5.proxy import * from m5 import build_env from BaseCPU import BaseCPU -from Checker import O3Checker from FUPool import * +if build_env['USE_CHECKER']: + from O3Checker import O3Checker + class DerivO3CPU(BaseCPU): type = 'DerivO3CPU' activity = Param.Unsigned(0, "Initial count") diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py new file mode 100644 index 000000000..43a71d67b --- /dev/null +++ b/src/cpu/o3/O3Checker.py @@ -0,0 +1,43 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class O3Checker(BaseCPU): + type = 'O3Checker' + exitOnError = Param.Bool(False, "Exit on an error") + updateOnError = Param.Bool(False, + "Update the checker with the main CPU's state on an error") + warnOnlyOnLoadError = Param.Bool(False, + "If a load result is incorrect, only print a warning and do not exit") + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index bb1dfb613..ad61ad228 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -33,6 +33,10 @@ import sys Import('*') if 'O3CPU' in env['CPU_MODELS']: + SimObject('FUPool.py') + SimObject('FuncUnitConfig.py') + SimObject('O3CPU.py') + Source('base_dyn_inst.cc') Source('bpred_unit.cc') Source('commit.cc') @@ -71,6 +75,7 @@ if 'O3CPU' in env['CPU_MODELS']: sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) if env['USE_CHECKER']: + SimObject('O3Checker.py') Source('checker_builder.cc') if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 7645a226c..d954bd1e7 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -100,8 +100,8 @@ class DefaultFetch /** Returns the address ranges of this device. */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } /** Timing version of receive. Handles setting fetch to the * proper status to start fetching. */ diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 3ae7bc402..0fd1e7bac 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -29,6 +29,9 @@ * Korey Sewell */ +#include <algorithm> +#include <cstring> + #include "config/use_checker.hh" #include "arch/isa_traits.hh" @@ -48,8 +51,6 @@ #include "sim/system.hh" #endif // FULL_SYSTEM -#include <algorithm> - template<class Impl> void DefaultFetch<Impl>::IcachePort::setPeer(Port *port) @@ -374,7 +375,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) return; } - memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize); + memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); cacheDataValid[tid] = true; if (!drainPending) { @@ -1116,7 +1117,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) (&cacheData[tid][offset])); predecoder.setTC(cpu->thread[tid]->getTC()); - predecoder.moreBytes(fetch_PC, 0, inst); + predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst); ext_inst = predecoder.getExtMachInst(); staticInst = StaticInstPtr(ext_inst); @@ -1153,10 +1154,14 @@ DefaultFetch<Impl>::fetch(bool &status_change) DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, instruction->staticInst->disassemble(fetch_PC)); +#if TRACING_ON instruction->traceData = Trace::getInstRecord(curTick, cpu->tcBase(tid), instruction->staticInst, instruction->readPC()); +#else + instruction->traceData = NULL; +#endif ///FIXME This needs to be more robust in dealing with delay slots predicted_branch |= diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index fd8f878a7..06de608e0 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -316,8 +316,8 @@ class LSQ { /** Returns the address ranges of this device. */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } /** Timing version of receive. Handles writing back and * completing the load or store that has returned from diff --git a/src/cpu/op_class.cc b/src/cpu/op_class.cc index f7ef49c0f..02cb4a08a 100644 --- a/src/cpu/op_class.cc +++ b/src/cpu/op_class.cc @@ -34,7 +34,7 @@ const char * opClassStrings[Num_OpClasses] = { - "(null)", + "No_OpClass", "IntAlu", "IntMult", "IntDiv", diff --git a/src/python/m5/objects/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py index 0913e044c..b9cfb448f 100644 --- a/src/python/m5/objects/OzoneCPU.py +++ b/src/cpu/ozone/OzoneCPU.py @@ -1,13 +1,45 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + from m5.params import * from m5 import build_env from BaseCPU import BaseCPU +if build_env['USE_CHECKER']: + from OzoneChecker import OzoneChecker + class DerivOzoneCPU(BaseCPU): type = 'DerivOzoneCPU' numThreads = Param.Unsigned("number of HW thread contexts") - checker = Param.BaseCPU("Checker CPU") + if build_env['USE_CHECKER']: + checker = Param.BaseCPU("Checker CPU") if build_env['FULL_SYSTEM']: profile = Param.Latency('0ns', "trace the kernel stack") diff --git a/src/cpu/ozone/OzoneChecker.py b/src/cpu/ozone/OzoneChecker.py new file mode 100644 index 000000000..f20b8770e --- /dev/null +++ b/src/cpu/ozone/OzoneChecker.py @@ -0,0 +1,43 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class OzoneChecker(BaseCPU): + type = 'OzoneChecker' + exitOnError = Param.Bool(False, "Exit on an error") + updateOnError = Param.Bool(False, + "Update the checker with the main CPU's state on an error") + warnOnlyOnLoadError = Param.Bool(False, + "If a load result is incorrect, only print a warning and do not exit") + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript index 4a040684a..cb2006456 100644 --- a/src/cpu/ozone/SConscript +++ b/src/cpu/ozone/SConscript @@ -31,6 +31,9 @@ Import('*') if 'OzoneCPU' in env['CPU_MODELS']: + SimObject('OzoneCPU.py') + SimObject('SimpleOzoneCPU.py') + need_bp_unit = True Source('base_dyn_inst.cc') Source('bpred_unit.cc') @@ -42,4 +45,5 @@ if 'OzoneCPU' in env['CPU_MODELS']: Source('lw_lsq.cc') Source('rename_table.cc') if env['USE_CHECKER']: + SimObject('OzoneChecker.py') Source('checker_builder.cc') diff --git a/src/python/m5/objects/SimpleOzoneCPU.py b/src/cpu/ozone/SimpleOzoneCPU.py index 193f31b0f..93603092b 100644 --- a/src/python/m5/objects/SimpleOzoneCPU.py +++ b/src/cpu/ozone/SimpleOzoneCPU.py @@ -1,3 +1,31 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + from m5.params import * from m5 import build_env from BaseCPU import BaseCPU diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index d78162243..d1214223b 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -53,7 +53,6 @@ #include "arch/vtophys.hh" #include "base/callback.hh" #include "cpu/profile.hh" -#include "mem/physical.hh" #include "sim/faults.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh index 0acf99ead..667392c06 100644 --- a/src/cpu/ozone/front_end.hh +++ b/src/cpu/ozone/front_end.hh @@ -91,8 +91,8 @@ class FrontEnd /** Returns the address ranges of this device. */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } /** Timing version of receive. Handles setting fetch to the * proper status to start fetching. */ diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index c981b8e63..2048ad6bb 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -257,8 +257,8 @@ class OzoneLWLSQ { virtual void recvStatusChange(Status status); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } virtual bool recvTiming(PacketPtr pkt); diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py new file mode 100644 index 000000000..e97f059c1 --- /dev/null +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -0,0 +1,43 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class AtomicSimpleCPU(BaseCPU): + type = 'AtomicSimpleCPU' + width = Param.Int(1, "CPU width") + simulate_stalls = Param.Bool(False, "Simulate cache stall cycles") + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + _mem_ports = ['icache_port', 'dcache_port'] diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript index 9a6a80473..ccccab2b5 100644 --- a/src/cpu/simple/SConscript +++ b/src/cpu/simple/SConscript @@ -33,10 +33,12 @@ Import('*') need_simple_base = False if 'AtomicSimpleCPU' in env['CPU_MODELS']: need_simple_base = True + SimObject('AtomicSimpleCPU.py') Source('atomic.cc') if 'TimingSimpleCPU' in env['CPU_MODELS']: need_simple_base = True + SimObject('TimingSimpleCPU.py') Source('timing.cc') if need_simple_base: diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py new file mode 100644 index 000000000..2fcde175c --- /dev/null +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -0,0 +1,41 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class TimingSimpleCPU(BaseCPU): + type = 'TimingSimpleCPU' + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + _mem_ports = ['icache_port', 'dcache_port'] diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index b0a01c3a3..ea1c7d87f 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -540,8 +540,8 @@ AtomicSimpleCPU::tick() } // @todo remove me after debugging with legion done - if (curStaticInst && (!curStaticInst->isMicroOp() || - curStaticInst->isFirstMicroOp())) + if (curStaticInst && (!curStaticInst->isMicroop() || + curStaticInst->isFirstMicroop())) instCnt++; if (simulate_stalls) { @@ -557,7 +557,7 @@ AtomicSimpleCPU::tick() } } - if(predecoder.needMoreBytes() || fault != NoFault) + if(fault != NoFault || !stayAtPC) advancePC(fault); } diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index ad4aa4708..b127e3791 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -104,8 +104,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU virtual void recvRetry(); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } }; CpuPort icachePort; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 4fed2059b..b7f60522f 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -70,7 +70,7 @@ using namespace std; using namespace TheISA; BaseSimpleCPU::BaseSimpleCPU(Params *p) - : BaseCPU(p), thread(NULL), predecoder(NULL) + : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) { #if FULL_SYSTEM thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); @@ -91,6 +91,9 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p) lastDcacheStall = 0; threadContexts.push_back(tc); + + fetchOffset = 0; + stayAtPC = false; } BaseSimpleCPU::~BaseSimpleCPU() @@ -326,18 +329,19 @@ BaseSimpleCPU::checkForInterrupts() Fault BaseSimpleCPU::setupFetchRequest(Request *req) { + Addr threadPC = thread->readPC(); + // set up memory request for instruction fetch #if ISA_HAS_DELAY_SLOT - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, thread->readNextPC(),thread->readNextNPC()); #else - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, thread->readNextPC()); #endif - req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), - (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0, - thread->readPC()); + Addr fetchPC = (threadPC & PCMask) + fetchOffset; + req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC); Fault fault = thread->translateInstReq(req); @@ -365,8 +369,10 @@ BaseSimpleCPU::preExecute() // decode the instruction inst = gtoh(inst); + //If we're not in the middle of a macro instruction if (!curMacroStaticInst) { + StaticInstPtr instPtr = NULL; //Predecode, ie bundle up an ExtMachInst @@ -374,36 +380,50 @@ BaseSimpleCPU::preExecute() predecoder.setTC(thread->getTC()); //If more fetch data is needed, pass it in. if(predecoder.needMoreBytes()) - predecoder.moreBytes(thread->readPC(), 0, inst); + predecoder.moreBytes(thread->readPC(), + (thread->readPC() & PCMask) + fetchOffset, 0, inst); else predecoder.process(); - //If an instruction is ready, decode it - if (predecoder.extMachInstReady()) - instPtr = StaticInst::decode(predecoder.getExtMachInst()); + + //If an instruction is ready, decode it. Otherwise, we'll have to + //fetch beyond the MachInst at the current pc. + if (predecoder.extMachInstReady()) { +#if THE_ISA == X86_ISA + thread->setNextPC(thread->readPC() + predecoder.getInstSize()); +#endif // X86_ISA + stayAtPC = false; + instPtr = StaticInst::decode(predecoder.getExtMachInst(), + thread->readPC()); + } else { + stayAtPC = true; + fetchOffset += sizeof(MachInst); + } //If we decoded an instruction and it's microcoded, start pulling //out micro ops - if (instPtr && instPtr->isMacroOp()) { + if (instPtr && instPtr->isMacroop()) { curMacroStaticInst = instPtr; curStaticInst = curMacroStaticInst-> - fetchMicroOp(thread->readMicroPC()); + fetchMicroop(thread->readMicroPC()); } else { curStaticInst = instPtr; } } else { //Read the next micro op from the macro op curStaticInst = curMacroStaticInst-> - fetchMicroOp(thread->readMicroPC()); + fetchMicroop(thread->readMicroPC()); } //If we decoded an instruction this "tick", record information about it. if(curStaticInst) { +#if TRACING_ON traceData = Trace::getInstRecord(curTick, tc, curStaticInst, thread->readPC()); DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", curStaticInst->getName(), curStaticInst->machInst); +#endif // TRACING_ON #if FULL_SYSTEM thread->setInst(inst); @@ -418,7 +438,7 @@ BaseSimpleCPU::postExecute() if (thread->profile) { bool usermode = TheISA::inUserMode(tc); thread->profilePC = usermode ? 1 : thread->readPC(); - StaticInstPtr si(inst); + StaticInstPtr si(inst, thread->readPC()); ProfileNode *node = thread->profile->consume(tc, si); if (node) thread->profileNode = node; @@ -447,14 +467,16 @@ BaseSimpleCPU::postExecute() void BaseSimpleCPU::advancePC(Fault fault) { + //Since we're moving to a new pc, zero out the offset + fetchOffset = 0; if (fault != NoFault) { curMacroStaticInst = StaticInst::nullStaticInstPtr; fault->invoke(tc); thread->setMicroPC(0); thread->setNextMicroPC(1); - } else if (predecoder.needMoreBytes()) { + } else { //If we're at the last micro op for this instruction - if (curStaticInst && curStaticInst->isLastMicroOp()) { + if (curStaticInst && curStaticInst->isLastMicroop()) { //We should be working with a macro op assert(curMacroStaticInst); //Close out this macro op, and clean up the diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 787259c96..d221baca8 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -137,6 +137,12 @@ class BaseSimpleCPU : public BaseCPU StaticInstPtr curStaticInst; StaticInstPtr curMacroStaticInst; + //This is the offset from the current pc that fetch should be performed at + Addr fetchOffset; + //This flag says to stay at the current pc. This is useful for + //instructions which go beyond MachInst boundaries. + bool stayAtPC; + void checkForInterrupts(); Fault setupFetchRequest(Request *req); void preExecute(); @@ -160,6 +166,9 @@ class BaseSimpleCPU : public BaseCPU return numInst - startNumInst; } + // Mask to align PCs to MachInst sized boundaries + static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); + // number of simulated memory references Stats::Scalar<> numMemRefs; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index fa7bb4f86..7698a588d 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -168,9 +168,7 @@ TimingSimpleCPU::resume() delete fetchEvent; } - fetchEvent = - new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); - fetchEvent->schedule(nextCycle()); + fetchEvent = new FetchEvent(this, nextCycle()); } changeState(SimObject::Running); @@ -224,9 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay) _status = Running; // kick things off by initiating the fetch of the next instruction - fetchEvent = - new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); - fetchEvent->schedule(nextCycle(curTick + cycles(delay))); + fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay))); } @@ -564,8 +560,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) { if (pkt->isResponse()) { // delay processing of returned data until next CPU clock edge - Tick mem_time = pkt->req->getTime(); - Tick next_tick = cpu->nextCycle(mem_time); + Tick next_tick = cpu->nextCycle(curTick); if (next_tick == curTick) cpu->completeIfetch(pkt); @@ -659,8 +654,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) { if (pkt->isResponse()) { // delay processing of returned data until next CPU clock edge - Tick mem_time = pkt->req->getTime(); - Tick next_tick = cpu->nextCycle(mem_time); + Tick next_tick = cpu->nextCycle(curTick); if (next_tick == curTick) cpu->completeDataAccess(pkt); diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index ef062d24a..39958bfb6 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -66,8 +66,6 @@ class TimingSimpleCPU : public BaseSimpleCPU Event *drainEvent; - Event *fetchEvent; - private: class CpuPort : public Port @@ -93,8 +91,8 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual void recvStatusChange(Status status); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = false; } struct TickEvent : public Event { @@ -199,7 +197,12 @@ class TimingSimpleCPU : public BaseSimpleCPU void completeIfetch(PacketPtr ); void completeDataAccess(PacketPtr ); void advanceInst(Fault fault); + private: + + typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; + FetchEvent *fetchEvent; + void completeDrain(); }; diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 824914ad0..95848ee2c 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -38,7 +38,6 @@ #include "config/full_system.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" -#include "mem/physical.hh" #include "mem/request.hh" #include "sim/byteswap.hh" #include "sim/eventq.hh" diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc index 64fcc0580..52a7ede03 100644 --- a/src/cpu/static_inst.cc +++ b/src/cpu/static_inst.cc @@ -37,6 +37,8 @@ StaticInstPtr StaticInst::nullStaticInstPtr; // Define the decode cache hash map. StaticInst::DecodeCache StaticInst::decodeCache; +StaticInst::AddrDecodeCache StaticInst::addrDecodeCache; +StaticInst::cacheElement StaticInst::recentDecodes[2]; void StaticInst::dumpDecodeCacheStats() @@ -76,9 +78,9 @@ StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const } StaticInstPtr -StaticInst::fetchMicroOp(MicroPC micropc) +StaticInst::fetchMicroop(MicroPC micropc) { - panic("StaticInst::fetchMicroOp() called on instruction " + panic("StaticInst::fetchMicroop() called on instruction " "that is not microcoded."); } diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index a58ac85d6..b0a19c151 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -63,6 +63,7 @@ class AtomicSimpleCPU; class TimingSimpleCPU; class InorderCPU; class SymbolTable; +class AddrDecodePage; namespace Trace { class InstRecord; @@ -143,11 +144,11 @@ class StaticInstBase : public RefCounted IsUnverifiable, ///< Can't be verified by a checker //Flags for microcode - IsMacroOp, ///< Is a macroop containing microops - IsMicroOp, ///< Is a microop + IsMacroop, ///< Is a macroop containing microops + IsMicroop, ///< Is a microop IsDelayedCommit, ///< This microop doesn't commit right away - IsLastMicroOp, ///< This microop ends a microop sequence - IsFirstMicroOp, ///< This microop begins a microop sequence + IsLastMicroop, ///< This microop ends a microop sequence + IsFirstMicroop, ///< This microop begins a microop sequence //This flag doesn't do anything yet IsMicroBranch, ///< This microop branches within the microcode for a macroop @@ -242,11 +243,11 @@ class StaticInstBase : public RefCounted bool isQuiesce() const { return flags[IsQuiesce]; } bool isIprAccess() const { return flags[IsIprAccess]; } bool isUnverifiable() const { return flags[IsUnverifiable]; } - bool isMacroOp() const { return flags[IsMacroOp]; } - bool isMicroOp() const { return flags[IsMicroOp]; } + bool isMacroop() const { return flags[IsMacroop]; } + bool isMicroop() const { return flags[IsMicroop]; } bool isDelayedCommit() const { return flags[IsDelayedCommit]; } - bool isLastMicroOp() const { return flags[IsLastMicroOp]; } - bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; } + bool isLastMicroop() const { return flags[IsLastMicroop]; } + bool isFirstMicroop() const { return flags[IsFirstMicroop]; } //This flag doesn't do anything yet bool isMicroBranch() const { return flags[IsMicroBranch]; } //@} @@ -349,6 +350,7 @@ class StaticInst : public StaticInstBase : StaticInstBase(__opClass), machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) { + memset(&recentDecodes, 0, 2 * sizeof(cacheElement)); } public: @@ -369,7 +371,7 @@ class StaticInst : public StaticInstBase * Return the microop that goes with a particular micropc. This should * only be defined/used in macroops which will contain microops */ - virtual StaticInstPtr fetchMicroOp(MicroPC micropc); + virtual StaticInstPtr fetchMicroop(MicroPC micropc); /** * Return the target address for a PC-relative branch. @@ -437,11 +439,52 @@ class StaticInst : public StaticInstBase /// Decode a machine instruction. /// @param mach_inst The binary instruction to decode. /// @retval A pointer to the corresponding StaticInst object. - //This is defined as inline below. - static StaticInstPtr decode(ExtMachInst mach_inst); + //This is defined as inlined below. + static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); /// Return name of machine instruction std::string getName() { return mnemonic; } + + /// Decoded instruction cache type, for address decoding. + /// A generic hash_map is used. + typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; + + /// A cache of decoded instruction objects from addresses. + static AddrDecodeCache addrDecodeCache; + + struct cacheElement { + Addr page_addr; + AddrDecodePage *decodePage; + } ; + + /// An array of recently decoded instructions. + // might not use an array if there is only two elements + static struct cacheElement recentDecodes[2]; + + /// Updates the recently decoded instructions entries + /// @param page_addr The page address recently used. + /// @param decodePage Pointer to decoding page containing the decoded + /// instruction. + static inline void + updateCache(Addr page_addr, AddrDecodePage *decodePage) + { + recentDecodes[1].page_addr = recentDecodes[0].page_addr; + recentDecodes[1].decodePage = recentDecodes[0].decodePage; + recentDecodes[0].page_addr = page_addr; + recentDecodes[0].decodePage = decodePage; + } + + /// Searches the decoded instruction cache for instruction decoding. + /// If it is not found, then we decode the instruction. + /// Otherwise, we get the instruction from the cache and move it into + /// the address-to-instruction decoding page. + /// @param mach_inst The binary instruction to decode. + /// @param addr The address that contained the binary instruction. + /// @param decodePage Pointer to decoding page containing the instruction. + /// @retval A pointer to the corresponding StaticInst object. + //This is defined as inlined below. + static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, + AddrDecodePage * decodePage); }; typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; @@ -472,8 +515,8 @@ class StaticInstPtr : public RefCountingPtr<StaticInst> /// Construct directly from machine instruction. /// Calls StaticInst::decode(). - explicit StaticInstPtr(TheISA::ExtMachInst mach_inst) - : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst)) + explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) + : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) { } @@ -484,8 +527,55 @@ class StaticInstPtr : public RefCountingPtr<StaticInst> } }; +/// A page of a list of decoded instructions from an address. +class AddrDecodePage +{ + typedef TheISA::ExtMachInst ExtMachInst; + protected: + StaticInstPtr instructions[TheISA::PageBytes]; + bool valid[TheISA::PageBytes]; + Addr lowerMask; + + public: + /// Constructor + AddrDecodePage() { + lowerMask = TheISA::PageBytes - 1; + memset(valid, 0, TheISA::PageBytes); + } + + /// Checks if the instruction is already decoded and the machine + /// instruction in the cache matches the current machine instruction + /// related to the address + /// @param mach_inst The binary instruction to check + /// @param addr The address containing the instruction + inline bool decoded(ExtMachInst mach_inst, Addr addr) + { + return (valid[addr & lowerMask] && + (instructions[addr & lowerMask]->machInst == mach_inst)); + } + + /// Returns the instruction object. decoded should be called first + /// to check if the instruction is valid. + /// @param addr The address of the instruction. + /// @retval A pointer to the corresponding StaticInst object. + inline StaticInstPtr getInst(Addr addr) + { return instructions[addr & lowerMask]; } + + /// Inserts a pointer to a StaticInst object into the list of decoded + /// instructions on the page. + /// @param addr The address of the instruction. + /// @param si A pointer to the corresponding StaticInst object. + inline void insert(Addr addr, StaticInstPtr &si) + { + instructions[addr & lowerMask] = si; + valid[addr & lowerMask] = true; + } + +}; + + inline StaticInstPtr -StaticInst::decode(StaticInst::ExtMachInst mach_inst) +StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) { #ifdef DECODE_CACHE_HASH_STATS // Simple stats on decode hash_map. Turns out the default @@ -499,12 +589,54 @@ StaticInst::decode(StaticInst::ExtMachInst mach_inst) } #endif + Addr page_addr = addr & ~(TheISA::PageBytes - 1); + + // checks recently decoded addresses + if (recentDecodes[0].decodePage && + page_addr == recentDecodes[0].page_addr) { + if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) + return recentDecodes[0].decodePage->getInst(addr); + + return searchCache(mach_inst, addr, recentDecodes[0].decodePage); + } + + if (recentDecodes[1].decodePage && + page_addr == recentDecodes[1].page_addr) { + if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) + return recentDecodes[1].decodePage->getInst(addr); + + return searchCache(mach_inst, addr, recentDecodes[1].decodePage); + } + + // searches the page containing the address to decode + AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); + if (iter != addrDecodeCache.end()) { + updateCache(page_addr, iter->second); + if (iter->second->decoded(mach_inst, addr)) + return iter->second->getInst(addr); + + return searchCache(mach_inst, addr, iter->second); + } + + // creates a new object for a page of decoded instructions + AddrDecodePage * decodePage = new AddrDecodePage; + addrDecodeCache[page_addr] = decodePage; + updateCache(page_addr, decodePage); + return searchCache(mach_inst, addr, decodePage); +} + +inline StaticInstPtr +StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, + AddrDecodePage * decodePage) +{ DecodeCache::iterator iter = decodeCache.find(mach_inst); if (iter != decodeCache.end()) { + decodePage->insert(addr, iter->second); return iter->second; } StaticInstPtr si = TheISA::decodeInst(mach_inst); + decodePage->insert(addr, si); decodeCache[mach_inst] = si; return si; } diff --git a/src/dev/BadDevice.py b/src/dev/BadDevice.py new file mode 100644 index 000000000..4fc592184 --- /dev/null +++ b/src/dev/BadDevice.py @@ -0,0 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from Device import BasicPioDevice + +class BadDevice(BasicPioDevice): + type = 'BadDevice' + devicename = Param.String("Name of device to error on") diff --git a/src/python/m5/objects/Device.py b/src/dev/Device.py index 90fbfb552..adf262f26 100644 --- a/src/python/m5/objects/Device.py +++ b/src/dev/Device.py @@ -1,3 +1,31 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.params import * from m5.proxy import * from MemObject import MemObject diff --git a/src/dev/DiskImage.py b/src/dev/DiskImage.py new file mode 100644 index 000000000..af2407458 --- /dev/null +++ b/src/dev/DiskImage.py @@ -0,0 +1,44 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +class DiskImage(SimObject): + type = 'DiskImage' + abstract = True + image_file = Param.String("disk image file") + read_only = Param.Bool(False, "read only image") + +class RawDiskImage(DiskImage): + type = 'RawDiskImage' + +class CowDiskImage(DiskImage): + type = 'CowDiskImage' + child = Param.DiskImage(RawDiskImage(read_only=True), + "child image") + table_size = Param.Int(65536, "initial table size") diff --git a/src/python/m5/objects/Ethernet.py b/src/dev/Ethernet.py index bfe30950c..e81862a96 100644 --- a/src/python/m5/objects/Ethernet.py +++ b/src/dev/Ethernet.py @@ -1,8 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.SimObject import SimObject from m5.params import * from m5.proxy import * -from m5 import build_env -from Device import DmaDevice from Pci import PciDevice, PciConfigData class EtherInt(SimObject): @@ -36,46 +62,19 @@ class EtherDump(SimObject): file = Param.String("dump file") maxlen = Param.Int(96, "max portion of packet data to dump") -if build_env['ALPHA_TLASER']: - - class EtherDev(DmaDevice): - type = 'EtherDev' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - - intr_delay = Param.Latency('0us', "Interrupt Delay") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") - tlaser = Param.Turbolaser(Parent.any, "Turbolaser") - - class EtherDevInt(EtherInt): - type = 'EtherDevInt' - device = Param.EtherDev("Ethernet device of this interface") - - class IGbE(PciDevice): type = 'IGbE' hardware_address = Param.String("Ethernet Hardware Address") - use_flow_control = Param.Bool(False, "Should we use xon/xoff flow contorl (UNIMPLMENTD)") + use_flow_control = Param.Bool(False, + "Should we use xon/xoff flow contorl (UNIMPLEMENTD)") rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") - rx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") - tx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") + rx_desc_cache_size = Param.Int(64, + "Number of enteries in the rx descriptor cache") + tx_desc_cache_size = Param.Int(64, + "Number of enteries in the rx descriptor cache") clock = Param.Clock('500MHz', "Clock speed of the device") - class IGbEPciData(PciConfigData): VendorID = 0x8086 DeviceID = 0x1075 diff --git a/src/dev/Ide.py b/src/dev/Ide.py new file mode 100644 index 000000000..6bbaad00e --- /dev/null +++ b/src/dev/Ide.py @@ -0,0 +1,68 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from Pci import PciDevice, PciConfigData + +class IdeID(Enum): vals = ['master', 'slave'] + +class IdeControllerPciData(PciConfigData): + VendorID = 0x8086 + DeviceID = 0x7111 + Command = 0x0 + Status = 0x280 + Revision = 0x0 + ClassCode = 0x01 + SubClassCode = 0x01 + ProgIF = 0x85 + BAR0 = 0x00000001 + BAR1 = 0x00000001 + BAR2 = 0x00000001 + BAR3 = 0x00000001 + BAR4 = 0x00000001 + BAR5 = 0x00000001 + InterruptLine = 0x1f + InterruptPin = 0x01 + BAR0Size = '8B' + BAR1Size = '4B' + BAR2Size = '8B' + BAR3Size = '4B' + BAR4Size = '16B' + +class IdeDisk(SimObject): + type = 'IdeDisk' + delay = Param.Latency('1us', "Fixed disk delay in microseconds") + driveID = Param.IdeID('master', "Drive ID") + image = Param.DiskImage("Disk image") + +class IdeController(PciDevice): + type = 'IdeController' + disks = VectorParam.IdeDisk("IDE disks attached to this controller") + + configdata =IdeControllerPciData() diff --git a/src/python/m5/objects/Pci.py b/src/dev/Pci.py index 9d40adbfe..b2c013f41 100644 --- a/src/python/m5/objects/Pci.py +++ b/src/dev/Pci.py @@ -1,3 +1,31 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.SimObject import SimObject from m5.params import * from m5.proxy import * diff --git a/src/dev/Platform.py b/src/dev/Platform.py new file mode 100644 index 000000000..cb414121b --- /dev/null +++ b/src/dev/Platform.py @@ -0,0 +1,35 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +class Platform(SimObject): + type = 'Platform' + abstract = True + intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/src/dev/SConscript b/src/dev/SConscript index ea529b536..2e0d75650 100644 --- a/src/dev/SConscript +++ b/src/dev/SConscript @@ -32,6 +32,17 @@ Import('*') if env['FULL_SYSTEM']: + SimObject('BadDevice.py') + SimObject('Device.py') + SimObject('DiskImage.py') + SimObject('Ethernet.py') + SimObject('Ide.py') + SimObject('Pci.py') + SimObject('Platform.py') + SimObject('SimConsole.py') + SimObject('SimpleDisk.py') + SimObject('Uart.py') + Source('baddev.cc') Source('disk_image.cc') Source('etherbus.cc') diff --git a/src/dev/SimConsole.py b/src/dev/SimConsole.py new file mode 100644 index 000000000..bb8420527 --- /dev/null +++ b/src/dev/SimConsole.py @@ -0,0 +1,39 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * + +class SimConsole(SimObject): + type = 'SimConsole' + append_name = Param.Bool(True, "append name() to filename") + intr_control = Param.IntrControl(Parent.any, "interrupt controller") + port = Param.TcpPort(3456, "listen port") + number = Param.Int(0, "console number") + output = Param.String('console', "file to dump output to") diff --git a/src/dev/SimpleDisk.py b/src/dev/SimpleDisk.py new file mode 100644 index 000000000..1c9193035 --- /dev/null +++ b/src/dev/SimpleDisk.py @@ -0,0 +1,35 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +class SimpleDisk(SimObject): + type = 'SimpleDisk' + disk = Param.DiskImage("Disk Image") + system = Param.System(Parent.any, "Sysetm Pointer") diff --git a/src/dev/Uart.py b/src/dev/Uart.py new file mode 100644 index 000000000..e32517a4c --- /dev/null +++ b/src/dev/Uart.py @@ -0,0 +1,45 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from m5 import build_env +from Device import BasicPioDevice + +class Uart(BasicPioDevice): + type = 'Uart' + abstract = True + sim_console = Param.SimConsole(Parent.any, "The console") + +class Uart8250(Uart): + type = 'Uart8250' + +if build_env['ALPHA_TLASER']: + class Uart8530(Uart): + type = 'Uart8530' + diff --git a/src/dev/alpha/AlphaConsole.py b/src/dev/alpha/AlphaConsole.py new file mode 100644 index 000000000..43c7ef954 --- /dev/null +++ b/src/dev/alpha/AlphaConsole.py @@ -0,0 +1,38 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from Device import BasicPioDevice + +class AlphaConsole(BasicPioDevice): + type = 'AlphaConsole' + cpu = Param.BaseCPU(Parent.cpu[0], "Processor") + disk = Param.SimpleDisk("Simple Disk") + sim_console = Param.SimConsole(Parent.any, "The Simulator Console") + system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript index c985fdd9f..8d7f5493b 100644 --- a/src/dev/alpha/SConscript +++ b/src/dev/alpha/SConscript @@ -32,6 +32,9 @@ Import('*') if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha': + SimObject('AlphaConsole.py') + SimObject('Tsunami.py') + Source('console.cc') Source('tsunami.cc') Source('tsunami_cchip.cc') diff --git a/src/python/m5/objects/Tsunami.py b/src/dev/alpha/Tsunami.py index 85105ff20..484976c09 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/dev/alpha/Tsunami.py @@ -1,3 +1,31 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.params import * from m5.proxy import * from Device import BasicPioDevice, IsaFake, BadAddr diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index e0272c655..baf13c49a 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -656,7 +656,7 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet) return false; pktPtr = packet; - + pktDone = false; igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf), packet->length, &pktEvent, packet->data); return true; @@ -683,8 +683,12 @@ IGbE::RxDescCache::pktComplete() uint8_t status = RXDS_DD | RXDS_EOP; uint8_t err = 0; + IpPtr ip(pktPtr); + if (ip) { + DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id()); + if (igbe->regs.rxcsum.ipofld()) { DPRINTF(EthernetDesc, "Checking IP checksum\n"); status |= RXDS_IPCS; @@ -715,7 +719,10 @@ IGbE::RxDescCache::pktComplete() err |= RXDE_TCPE; } } - } // if ip + } else { // if ip + DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); + } + desc->status = htole(status); desc->errors = htole(err); @@ -912,10 +919,20 @@ IGbE::TxDescCache::pktComplete() DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2); + if (DTRACE(EthernetDesc)) { + IpPtr ip(pktPtr); + if (ip) + DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", + ip->id()); + else + DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); + } + // Checksums are only ofloaded for new descriptor types if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) { DPRINTF(EthernetDesc, "Calculating checksums for packet\n"); IpPtr ip(pktPtr); + if (TxdOp::ixsm(desc)) { ip->sum(0); ip->sum(cksum(ip)); @@ -1192,6 +1209,7 @@ IGbE::rxStateMachine() // If the packet is done check for interrupts/descriptors/etc if (rxDescCache.packetDone()) { + rxDmaPacket = false; DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n"); int descLeft = rxDescCache.descLeft(); switch (regs.rctl.rdmts()) { @@ -1236,6 +1254,12 @@ IGbE::rxStateMachine() return; } + if (rxDmaPacket) { + DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); + rxTick = false; + return; + } + if (!rxDescCache.descUnused()) { DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n"); rxTick = false; @@ -1262,6 +1286,7 @@ IGbE::rxStateMachine() rxFifo.pop(); DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); rxTick = false; + rxDmaPacket = true; } void diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index 2dec3b08c..b6da53b09 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -80,6 +80,8 @@ class IGbE : public PciDev bool txTick; bool txFifoTick; + bool rxDmaPacket; + // Event and function to deal with RDTR timer expiring void rdtrProcess() { rxDescCache.writeback(0); diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index d430ace72..ecbb391ef 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -48,9 +48,9 @@ PioPort::recvAtomic(PacketPtr pkt) } void -PioPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) +PioPort::getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) { - snoop.clear(); + snoop = false; device->addressRanges(resp); } @@ -218,6 +218,9 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, DmaReqState *reqState = new DmaReqState(event, this, size); + + DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size, + event->scheduled()); for (ChunkGenerator gen(addr, size, peerBlockSize()); !gen.done(); gen.next()) { Request *req = new Request(gen.addr(), gen.size(), 0); @@ -231,6 +234,8 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, assert(pendingCount >= 0); pendingCount++; + DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(), + gen.size()); queueDma(pkt); } @@ -281,19 +286,28 @@ DmaPort::sendDma() if (transmitList.size() && backoffTime && !inRetry && !backoffEvent.scheduled()) { + DPRINTF(DMA, "-- Scheduling backoff timer for %d\n", + backoffTime+curTick); backoffEvent.schedule(backoffTime+curTick); } } else if (state == System::Atomic) { transmitList.pop_front(); Tick lat; + DPRINTF(DMA, "--Sending DMA for addr: %#x size: %d\n", + pkt->req->getPaddr(), pkt->req->getSize()); lat = sendAtomic(pkt); assert(pkt->senderState); DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState); assert(state); - state->numBytes += pkt->req->getSize(); + + DPRINTF(DMA, "--Received response for DMA for addr: %#x size: %d nb: %d, tot: %d sched %d\n", + pkt->req->getPaddr(), pkt->req->getSize(), state->numBytes, + state->totBytes, state->completionEvent->scheduled()); + if (state->totBytes == state->numBytes) { + assert(!state->completionEvent->scheduled()); state->completionEvent->schedule(curTick + lat); delete state; delete pkt->req; diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index bd150bfe4..25bd2de8d 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -59,7 +59,7 @@ class PioPort : public SimpleTimingPort virtual Tick recvAtomic(PacketPtr pkt); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); public: @@ -127,8 +127,8 @@ class DmaPort : public Port virtual void recvRetry() ; virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); } + bool &snoop) + { resp.clear(); snoop = false; } void queueDma(PacketPtr pkt, bool front = false); void sendDma(); diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index d9985f808..e9d9c419d 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -1270,8 +1270,7 @@ NSGigE::cpuIntrPost(Tick when) if (intrEvent) intrEvent->squash(); - intrEvent = new IntrEvent(this, true); - intrEvent->schedule(intrTick); + intrEvent = new IntrEvent(this, intrTick, true); } void @@ -2770,8 +2769,7 @@ NSGigE::unserialize(Checkpoint *cp, const std::string §ion) Tick intrEventTick; UNSERIALIZE_SCALAR(intrEventTick); if (intrEventTick) { - intrEvent = new IntrEvent(this, true); - intrEvent->schedule(intrEventTick); + intrEvent = new IntrEvent(this, intrEventTick, true); } } diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc index f906e69cf..c2a2bc02d 100644 --- a/src/dev/pcidev.cc +++ b/src/dev/pcidev.cc @@ -76,9 +76,9 @@ PciDev::PciConfigPort::recvAtomic(PacketPtr pkt) void PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { - snoop.clear(); + snoop = false;; resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1)); } diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh index 5044e2932..5ddbe84a0 100644 --- a/src/dev/pcidev.hh +++ b/src/dev/pcidev.hh @@ -89,7 +89,7 @@ class PciDev : public DmaDevice virtual Tick recvAtomic(PacketPtr pkt); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); Platform *platform; diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 420761620..e13fdb0bc 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -630,8 +630,7 @@ Base::cpuIntrPost(Tick when) if (intrEvent) intrEvent->squash(); - intrEvent = new IntrEvent(this, true); - intrEvent->schedule(intrTick); + intrEvent = new IntrEvent(this, intrTick, true); } void @@ -1339,8 +1338,7 @@ Base::unserialize(Checkpoint *cp, const std::string §ion) Tick intrEventTick; UNSERIALIZE_SCALAR(intrEventTick); if (intrEventTick) { - intrEvent = new IntrEvent(this, true); - intrEvent->schedule(intrEventTick); + intrEvent = new IntrEvent(this, intrEventTick, true); } } diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript index 8511b16fb..2ebf9fe05 100644 --- a/src/dev/sparc/SConscript +++ b/src/dev/sparc/SConscript @@ -32,6 +32,8 @@ Import('*') if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc': + SimObject('T1000.py') + Source('dtod.cc') Source('iob.cc') Source('t1000.cc') diff --git a/src/python/m5/objects/T1000.py b/src/dev/sparc/T1000.py index 0acfa0920..a033e27e2 100644 --- a/src/python/m5/objects/T1000.py +++ b/src/dev/sparc/T1000.py @@ -1,3 +1,31 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + from m5.params import * from m5.proxy import * from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr diff --git a/src/kern/tru64/tru64_events.cc b/src/kern/tru64/tru64_events.cc index 0ad89f8bd..4db5df067 100644 --- a/src/kern/tru64/tru64_events.cc +++ b/src/kern/tru64/tru64_events.cc @@ -54,7 +54,7 @@ BadAddrEvent::process(ThreadContext *tc) uint64_t a0 = tc->readIntReg(ArgumentReg0); AddrRangeList resp; - AddrRangeList snoop; + bool snoop; AddrRangeIter iter; bool found = false; diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py new file mode 100644 index 000000000..8377221cd --- /dev/null +++ b/src/mem/Bridge.py @@ -0,0 +1,44 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +from m5.params import * +from MemObject import MemObject + +class Bridge(MemObject): + type = 'Bridge' + side_a = Port('Side A port') + side_b = Port('Side B port') + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") + delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") + write_ack = Param.Bool(False, "Should this bridge ack writes") + fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") + fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/mem/Bus.py b/src/mem/Bus.py new file mode 100644 index 000000000..247a1fe31 --- /dev/null +++ b/src/mem/Bus.py @@ -0,0 +1,49 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5 import build_env +from m5.params import * +from m5.proxy import * +from MemObject import MemObject + +if build_env['FULL_SYSTEM']: + from Device import BadAddr + +class Bus(MemObject): + type = 'Bus' + port = VectorPort("vector port for connecting devices") + bus_id = Param.Int(0, "blah") + clock = Param.Clock("1GHz", "bus clock speed") + width = Param.Int(64, "bus width (bytes)") + responder_set = Param.Bool(False, "Did the user specify a default responder.") + block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") + if build_env['FULL_SYSTEM']: + responder = BadAddr(pio_addr=0x0, pio_latency="1ps") + default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") + else: + default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py new file mode 100644 index 000000000..269cf4403 --- /dev/null +++ b/src/mem/MemObject.py @@ -0,0 +1,34 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +from m5.SimObject import SimObject +from m5.SimObject import SimObject + +class MemObject(SimObject): + type = 'MemObject' + abstract = True diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py new file mode 100644 index 000000000..2ef3df7c1 --- /dev/null +++ b/src/mem/PhysicalMemory.py @@ -0,0 +1,57 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from MemObject import * + +class PhysicalMemory(MemObject): + type = 'PhysicalMemory' + port = VectorPort("the access port") + range = Param.AddrRange(AddrRange('128MB'), "Device Address") + file = Param.String('', "memory mapped file") + latency = Param.Latency('1t', "latency of an access") + zero = Param.Bool(False, "zero initialize memory") + +class DRAMMemory(PhysicalMemory): + type = 'DRAMMemory' + # Many of these should be observed from the configuration + cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") + mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") + mem_actpolicy = Param.String("open", "Open/Close policy") + memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") + bus_width = Param.Int(16, "") + act_lat = Param.Int(2, "RAS to CAS delay") + cas_lat = Param.Int(1, "CAS delay") + war_lat = Param.Int(2, "write after read delay") + pre_lat = Param.Int(2, "precharge delay") + dpl_lat = Param.Int(2, "data in to precharge delay") + trc_lat = Param.Int(6, "row cycle delay") + num_banks = Param.Int(4, "Number of Banks") + num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") + diff --git a/src/mem/SConscript b/src/mem/SConscript index 61fb766d6..bbb1e96fe 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -30,6 +30,11 @@ Import('*') +SimObject('Bridge.py') +SimObject('Bus.py') +SimObject('PhysicalMemory.py') +SimObject('MemObject.py') + Source('bridge.cc') Source('bus.cc') Source('dram.cc') diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index e89473be3..04b0308e1 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -119,7 +119,14 @@ Bridge::BridgePort::recvTiming(PacketPtr pkt) DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr()); - if (pkt->isRequest() && otherPort->reqQueueFull()) { + DPRINTF(BusBridge, "Local queue size: %d outreq: %d outresp: %d\n", + sendQueue.size(), queuedRequests, outstandingResponses); + DPRINTF(BusBridge, "Remove queue size: %d outreq: %d outresp: %d\n", + otherPort->sendQueue.size(), otherPort->queuedRequests, + otherPort->outstandingResponses); + + if (pkt->isRequest() && otherPort->reqQueueFull() && pkt->result != + Packet::Nacked) { DPRINTF(BusBridge, "Remote queue full, nacking\n"); nackRequest(pkt); return true; @@ -191,7 +198,7 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt) void Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) { - if (pkt->isResponse() || pkt->result == Packet::Nacked) { + if (pkt->isResponse() || pkt->result == Packet::Nacked) { // This is a response for a request we forwarded earlier. The // corresponding PacketBuffer should be stored in the packet's // senderState field. @@ -201,9 +208,9 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) // from original request buf->fixResponse(pkt); - // Check if this packet was expecting a response (this is either it or - // its a nacked packet and we won't be seeing that response) - if (buf->expectResponse) + // Check if this packet was expecting a response and it's a nacked + // packet, in which case we will never being seeing it + if (buf->expectResponse && pkt->result == Packet::Nacked) --outstandingResponses; @@ -213,6 +220,13 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) delete buf; } + + if (pkt->isRequest() && pkt->result != Packet::Nacked) { + ++queuedRequests; + } + + + Tick readyTime = curTick + delay; PacketBuffer *buf = new PacketBuffer(pkt, readyTime); DPRINTF(BusBridge, "old sender state: %#X, new sender state: %#X\n", @@ -225,7 +239,6 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) if (sendQueue.empty()) { sendEvent.schedule(readyTime); } - ++queuedRequests; sendQueue.push_back(buf); } @@ -234,8 +247,6 @@ Bridge::BridgePort::trySend() { assert(!sendQueue.empty()); - int pbs = peerBlockSize(); - PacketBuffer *buf = sendQueue.front(); assert(buf->ready <= curTick); @@ -244,16 +255,22 @@ Bridge::BridgePort::trySend() pkt->flags &= ~SNOOP_COMMIT; //CLear it if it was set + // Ugly! @todo When multilevel coherence works this will be removed if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite && - pkt->result != Packet::Nacked && pkt->getOffset(pbs) && - pkt->getSize() != pbs) { - buf->partialWriteFix(this); - pkt = buf->pkt; + pkt->result != Packet::Nacked) { + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq, + Packet::Broadcast); + funcPkt->dataStatic(pkt->getPtr<uint8_t>()); + sendFunctional(funcPkt); + pkt->cmd = MemCmd::WriteReq; + delete funcPkt; } DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n", buf->origSrc, pkt->getDest(), pkt->getAddr()); + bool wasReq = pkt->isRequest(); + bool wasNacked = pkt->result == Packet::Nacked; if (sendTiming(pkt)) { // send successful @@ -270,8 +287,12 @@ Bridge::BridgePort::trySend() delete buf; } - if (!buf->nacked) + if (!wasNacked) { + if (wasReq) --queuedRequests; + else + --outstandingResponses; + } // If there are more packets to send, schedule event to try again. if (!sendQueue.empty()) { @@ -281,7 +302,6 @@ Bridge::BridgePort::trySend() } } else { DPRINTF(BusBridge, " unsuccessful\n"); - buf->undoPartialWriteFix(); inRetry = true; } DPRINTF(BusBridge, "trySend: queue size: %d outreq: %d outstanding resp: %d\n", @@ -305,7 +325,18 @@ Bridge::BridgePort::recvRetry() Tick Bridge::BridgePort::recvAtomic(PacketPtr pkt) { - return otherPort->sendAtomic(pkt) + delay; + // fix partial atomic writes... similar to the timing code that does the + // same... will be removed once our code gets this right + if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite) { + + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq, + Packet::Broadcast); + funcPkt->dataStatic(pkt->getPtr<uint8_t>()); + otherPort->sendFunctional(funcPkt); + delete funcPkt; + pkt->cmd = MemCmd::WriteReq; + } + return delay + otherPort->sendAtomic(pkt); } /** Function called by the port when the bus is receiving a Functional @@ -336,7 +367,7 @@ Bridge::BridgePort::recvStatusChange(Port::Status status) void Bridge::BridgePort::getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { otherPort->getPeerAddressRanges(resp, snoop); } @@ -387,3 +418,4 @@ CREATE_SIM_OBJECT(Bridge) REGISTER_SIM_OBJECT("Bridge", Bridge) + diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index cb5a6baed..89d626611 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -80,18 +80,13 @@ class Bridge : public MemObject short origSrc; bool expectResponse; - bool partialWriteFixed; - PacketPtr oldPkt; - bool nacked; - PacketBuffer(PacketPtr _pkt, Tick t, bool nack = false) : ready(t), pkt(_pkt), origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()), - expectResponse(_pkt->needsResponse() && !nack), - partialWriteFixed(false), nacked(nack) + expectResponse(_pkt->needsResponse() && !nack) { - if (!pkt->isResponse() && !nack) + if (!pkt->isResponse() && !nack && pkt->result != Packet::Nacked) pkt->senderState = this; } @@ -100,46 +95,7 @@ class Bridge : public MemObject assert(pkt->senderState == this); pkt->setDest(origSrc); pkt->senderState = origSenderState; - if (partialWriteFixed) - delete oldPkt; - } - - void partialWriteFix(Port *port) - { - assert(!partialWriteFixed); - assert(expectResponse); - - int pbs = port->peerBlockSize(); - partialWriteFixed = true; - PacketDataPtr data; - - data = new uint8_t[pbs]; - PacketPtr funcPkt = new Packet(pkt->req, MemCmd::ReadReq, - Packet::Broadcast, pbs); - - funcPkt->dataStatic(data); - port->sendFunctional(funcPkt); - assert(funcPkt->result == Packet::Success); - delete funcPkt; - - oldPkt = pkt; - memcpy(data + oldPkt->getOffset(pbs), pkt->getPtr<uint8_t>(), - pkt->getSize()); - pkt = new Packet(oldPkt->req, MemCmd::WriteInvalidateReq, - Packet::Broadcast, pbs); - pkt->dataDynamicArray(data); - pkt->senderState = oldPkt->senderState; } - - void undoPartialWriteFix() - { - if (!partialWriteFixed) - return; - delete pkt; - pkt = oldPkt; - partialWriteFixed = false; - } - }; /** @@ -226,7 +182,7 @@ class Bridge : public MemObject /** When receiving a address range request the peer port, pass it to the bridge. */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); }; BridgePort portA, portB; diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 95d4e2873..13e545064 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -296,16 +296,15 @@ Bus::findPort(Addr addr, int id) { /* An interval tree would be a better way to do this. --ali. */ int dest_id = -1; - AddrRangeIter iter; - range_map<Addr,int>::iterator i; - i = portMap.find(RangeSize(addr,1)); + PortIter i = portMap.find(RangeSize(addr,1)); if (i != portMap.end()) dest_id = i->second; // Check if this matches the default range if (dest_id == -1) { - for (iter = defaultRange.begin(); iter != defaultRange.end(); iter++) { + for (AddrRangeIter iter = defaultRange.begin(); + iter != defaultRange.end(); iter++) { if (*iter == addr) { DPRINTF(Bus, " found addr %#llx on default\n", addr); return defaultPort; @@ -333,88 +332,63 @@ Bus::findPort(Addr addr, int id) return interfaces[dest_id]; } -std::vector<int> -Bus::findSnoopPorts(Addr addr, int id) -{ - int i = 0; - AddrRangeIter iter; - std::vector<int> ports; - - while (i < portSnoopList.size()) - { - if (portSnoopList[i].range == addr && portSnoopList[i].portId != id) { - //Careful to not overlap ranges - //or snoop will be called more than once on the port - - //@todo Fix this hack because ranges are overlapping - //need to make sure we dont't create overlapping ranges - bool hack_overlap = false; - int size = ports.size(); - for (int j=0; j < size; j++) { - if (ports[j] == portSnoopList[i].portId) - hack_overlap = true; - } - - if (!hack_overlap) - ports.push_back(portSnoopList[i].portId); -// DPRINTF(Bus, " found snoop addr %#llx on device%d\n", addr, -// portSnoopList[i].portId); - } - i++; - } - return ports; -} - Tick Bus::atomicSnoop(PacketPtr pkt, Port *responder) { - std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc()); Tick response_time = 0; - while (!ports.empty()) - { - if (interfaces[ports.back()] != responder) { - Tick response = interfaces[ports.back()]->sendAtomic(pkt); + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); + s_iter++) { + BusPort *p = *s_iter; + if (p != responder && p->getId() != pkt->getSrc()) { + Tick response = p->sendAtomic(pkt); if (response) { assert(!response_time); //Multiple responders response_time = response; } } - ports.pop_back(); } + return response_time; } void Bus::functionalSnoop(PacketPtr pkt, Port *responder) { - std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc()); - - //The packet may be changed by another bus on snoops, restore the id after each - int id = pkt->getSrc(); - while (!ports.empty() && pkt->result != Packet::Success) - { - if (interfaces[ports.back()] != responder) - interfaces[ports.back()]->sendFunctional(pkt); - ports.pop_back(); - pkt->setSrc(id); + // The packet may be changed by another bus on snoops, restore the + // id after each + int src_id = pkt->getSrc(); + + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); + s_iter++) { + BusPort *p = *s_iter; + if (p != responder && p->getId() != src_id) { + p->sendFunctional(pkt); + } + if (pkt->result == Packet::Success) { + break; + } + pkt->setSrc(src_id); } } bool Bus::timingSnoop(PacketPtr pkt, Port* responder) { - std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc()); - bool success = true; - - while (!ports.empty() && success) - { - if (interfaces[ports.back()] != responder) //Don't call if responder also, once will do - success = interfaces[ports.back()]->sendTiming(pkt); - ports.pop_back(); + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); + s_iter++) { + BusPort *p = *s_iter; + if (p != responder && p->getId() != pkt->getSrc()) { + bool success = p->sendTiming(pkt); + if (!success) + return false; + } } - return success; + return true; } @@ -467,7 +441,7 @@ void Bus::recvStatusChange(Port::Status status, int id) { AddrRangeList ranges; - AddrRangeList snoops; + bool snoops; AddrRangeIter iter; assert(status == Port::RangeChange && @@ -480,7 +454,7 @@ Bus::recvStatusChange(Port::Status status, int id) // Only try to update these ranges if the user set a default responder. if (responderSet) { defaultPort->getPeerAddressRanges(ranges, snoops); - assert(snoops.size() == 0); + assert(snoops == false); for(iter = ranges.begin(); iter != ranges.end(); iter++) { defaultRange.push_back(*iter); DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for default range\n", @@ -490,39 +464,33 @@ Bus::recvStatusChange(Port::Status status, int id) } else { assert((id < maxId && id >= 0) || id == defaultId); - Port *port = interfaces[id]; - range_map<Addr,int>::iterator portIter; - std::vector<DevMap>::iterator snoopIter; + BusPort *port = interfaces[id]; // Clean out any previously existent ids - for (portIter = portMap.begin(); portIter != portMap.end(); ) { + for (PortIter portIter = portMap.begin(); + portIter != portMap.end(); ) { if (portIter->second == id) portMap.erase(portIter++); else portIter++; } - for (snoopIter = portSnoopList.begin(); snoopIter != portSnoopList.end(); ) { - if (snoopIter->portId == id) - snoopIter = portSnoopList.erase(snoopIter); + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); ) { + if ((*s_iter)->getId() == id) + s_iter = snoopPorts.erase(s_iter); else - snoopIter++; + s_iter++; } port->getPeerAddressRanges(ranges, snoops); - for(iter = snoops.begin(); iter != snoops.end(); iter++) { - DevMap dm; - dm.portId = id; - dm.range = *iter; - - //@todo, make sure we don't overlap ranges - DPRINTF(BusAddrRanges, "Adding snoop range %#llx - %#llx for id %d\n", - dm.range.start, dm.range.end, id); - portSnoopList.push_back(dm); + if (snoops) { + DPRINTF(BusAddrRanges, "Adding id %d to snoop list\n", id); + snoopPorts.push_back(port); } - for(iter = ranges.begin(); iter != ranges.end(); iter++) { + for (iter = ranges.begin(); iter != ranges.end(); iter++) { DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for id %d\n", iter->start, iter->end, id); if (portMap.insert(*iter, id) == portMap.end()) @@ -545,28 +513,24 @@ Bus::recvStatusChange(Port::Status status, int id) } void -Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id) +Bus::addressRanges(AddrRangeList &resp, bool &snoop, int id) { - std::vector<DevMap>::iterator snoopIter; - range_map<Addr,int>::iterator portIter; - AddrRangeIter dflt_iter; - bool subset; - resp.clear(); - snoop.clear(); + snoop = false; DPRINTF(BusAddrRanges, "received address range request, returning:\n"); - for (dflt_iter = defaultRange.begin(); dflt_iter != defaultRange.end(); - dflt_iter++) { + for (AddrRangeIter dflt_iter = defaultRange.begin(); + dflt_iter != defaultRange.end(); dflt_iter++) { resp.push_back(*dflt_iter); DPRINTF(BusAddrRanges, " -- Dflt: %#llx : %#llx\n",dflt_iter->start, dflt_iter->end); } - for (portIter = portMap.begin(); portIter != portMap.end(); portIter++) { - subset = false; - for (dflt_iter = defaultRange.begin(); dflt_iter != defaultRange.end(); - dflt_iter++) { + for (PortIter portIter = portMap.begin(); + portIter != portMap.end(); portIter++) { + bool subset = false; + for (AddrRangeIter dflt_iter = defaultRange.begin(); + dflt_iter != defaultRange.end(); dflt_iter++) { if ((portIter->first.start < dflt_iter->start && portIter->first.end >= dflt_iter->start) || (portIter->first.start < dflt_iter->end && @@ -587,15 +551,11 @@ Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id) } } - for (snoopIter = portSnoopList.begin(); - snoopIter != portSnoopList.end(); snoopIter++) - { - if (snoopIter->portId != id) { - snoop.push_back(snoopIter->range); - DPRINTF(BusAddrRanges, " -- Snoop: %#llx : %#llx\n", - snoopIter->range.start, snoopIter->range.end); - //@todo We need to properly insert snoop ranges - //not overlapping the ranges (multiple) + for (SnoopIter s_iter = snoopPorts.begin(); s_iter != snoopPorts.end(); + s_iter++) { + if ((*s_iter)->getId() != id) { + snoop = true; + break; } } } @@ -606,17 +566,17 @@ Bus::findBlockSize(int id) if (cachedBlockSizeValid) return cachedBlockSize; - int max_bs = -1, tmp_bs; - range_map<Addr,int>::iterator portIter; - std::vector<DevMap>::iterator snoopIter; - for (portIter = portMap.begin(); portIter != portMap.end(); portIter++) { - tmp_bs = interfaces[portIter->second]->peerBlockSize(); + int max_bs = -1; + + for (PortIter portIter = portMap.begin(); + portIter != portMap.end(); portIter++) { + int tmp_bs = interfaces[portIter->second]->peerBlockSize(); if (tmp_bs > max_bs) max_bs = tmp_bs; } - for (snoopIter = portSnoopList.begin(); - snoopIter != portSnoopList.end(); snoopIter++) { - tmp_bs = interfaces[snoopIter->portId]->peerBlockSize(); + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); s_iter++) { + int tmp_bs = (*s_iter)->peerBlockSize(); if (tmp_bs > max_bs) max_bs = tmp_bs; } @@ -645,6 +605,13 @@ Bus::drain(Event * de) } } +void +Bus::startup() +{ + if (tickNextIdle < curTick) + tickNextIdle = (curTick / clock) * clock + clock; +} + BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus) Param<int> bus_id; diff --git a/src/mem/bus.hh b/src/mem/bus.hh index f0dc67b12..ee647e20a 100644 --- a/src/mem/bus.hh +++ b/src/mem/bus.hh @@ -52,93 +52,6 @@ class Bus : public MemObject { - /** a globally unique id for this bus. */ - int busId; - /** the clock speed for the bus */ - int clock; - /** the width of the bus in bytes */ - int width; - /** the next tick at which the bus will be idle */ - Tick tickNextIdle; - - Event * drainEvent; - - - static const int defaultId = -3; //Make it unique from Broadcast - - struct DevMap { - int portId; - Range<Addr> range; - }; - range_map<Addr, int> portMap; - AddrRangeList defaultRange; - std::vector<DevMap> portSnoopList; - - /** Function called by the port when the bus is recieving a Timing - transaction.*/ - bool recvTiming(PacketPtr pkt); - - /** Function called by the port when the bus is recieving a Atomic - transaction.*/ - Tick recvAtomic(PacketPtr pkt); - - /** Function called by the port when the bus is recieving a Functional - transaction.*/ - void recvFunctional(PacketPtr pkt); - - /** Timing function called by port when it is once again able to process - * requests. */ - void recvRetry(int id); - - /** Function called by the port when the bus is recieving a status change.*/ - void recvStatusChange(Port::Status status, int id); - - /** Find which port connected to this bus (if any) should be given a packet - * with this address. - * @param addr Address to find port for. - * @param id Id of the port this packet was received from (to prevent - * loops) - * @return pointer to port that the packet should be sent out of. - */ - Port *findPort(Addr addr, int id); - - /** Find all ports with a matching snoop range, except src port. Keep in mind - * that the ranges shouldn't overlap or you will get a double snoop to the same - * interface.and the cache will assert out. - * @param addr Address to find snoop prts for. - * @param id Id of the src port of the request to avoid calling snoop on src - * @return vector of IDs to snoop on - */ - std::vector<int> findSnoopPorts(Addr addr, int id); - - /** Snoop all relevant ports atomicly. */ - Tick atomicSnoop(PacketPtr pkt, Port* responder); - - /** Snoop all relevant ports functionally. */ - void functionalSnoop(PacketPtr pkt, Port *responder); - - /** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want - * the snoop to happen - * @return True if succeds. - */ - bool timingSnoop(PacketPtr pkt, Port *responder); - - /** Process address range request. - * @param resp addresses that we can respond to - * @param snoop addresses that we would like to snoop - * @param id ide of the busport that made the request. - */ - void addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id); - - /** Occupy the bus with transmitting the packet pkt */ - void occupyBus(PacketPtr pkt); - - /** Ask everyone on the bus what their size is - * @param id id of the busport that made the request - * @return the max of all the sizes - */ - int findBlockSize(int id); - /** Declaration of the buses port type, one will be instantiated for each of the interfaces connecting to the bus. */ class BusPort : public Port @@ -198,7 +111,7 @@ class Bus : public MemObject // the 'owned' address ranges of all the other interfaces on // this bus... virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { bus->addressRanges(resp, snoop, id); } // Ask the bus to ask everyone on the bus what their block size is and @@ -219,6 +132,84 @@ class Bus : public MemObject const char *description(); }; + /** a globally unique id for this bus. */ + int busId; + /** the clock speed for the bus */ + int clock; + /** the width of the bus in bytes */ + int width; + /** the next tick at which the bus will be idle */ + Tick tickNextIdle; + + Event * drainEvent; + + + static const int defaultId = -3; //Make it unique from Broadcast + + typedef range_map<Addr,int>::iterator PortIter; + range_map<Addr, int> portMap; + + AddrRangeList defaultRange; + + typedef std::vector<BusPort*>::iterator SnoopIter; + std::vector<BusPort*> snoopPorts; + + /** Function called by the port when the bus is recieving a Timing + transaction.*/ + bool recvTiming(PacketPtr pkt); + + /** Function called by the port when the bus is recieving a Atomic + transaction.*/ + Tick recvAtomic(PacketPtr pkt); + + /** Function called by the port when the bus is recieving a Functional + transaction.*/ + void recvFunctional(PacketPtr pkt); + + /** Timing function called by port when it is once again able to process + * requests. */ + void recvRetry(int id); + + /** Function called by the port when the bus is recieving a status change.*/ + void recvStatusChange(Port::Status status, int id); + + /** Find which port connected to this bus (if any) should be given a packet + * with this address. + * @param addr Address to find port for. + * @param id Id of the port this packet was received from (to prevent + * loops) + * @return pointer to port that the packet should be sent out of. + */ + Port *findPort(Addr addr, int id); + + /** Snoop all relevant ports atomicly. */ + Tick atomicSnoop(PacketPtr pkt, Port* responder); + + /** Snoop all relevant ports functionally. */ + void functionalSnoop(PacketPtr pkt, Port *responder); + + /** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want + * the snoop to happen + * @return True if succeds. + */ + bool timingSnoop(PacketPtr pkt, Port *responder); + + /** Process address range request. + * @param resp addresses that we can respond to + * @param snoop addresses that we would like to snoop + * @param id ide of the busport that made the request. + */ + void addressRanges(AddrRangeList &resp, bool &snoop, int id); + + /** Occupy the bus with transmitting the packet pkt */ + void occupyBus(PacketPtr pkt); + + /** Ask everyone on the bus what their size is + * @param id id of the busport that made the request + * @return the max of all the sizes + */ + int findBlockSize(int id); + BusFreeEvent busIdle; bool inRetry; @@ -276,6 +267,7 @@ class Bus : public MemObject virtual void deletePortRefs(Port *p); virtual void init(); + virtual void startup(); unsigned int drain(Event *de); diff --git a/src/python/m5/objects/BaseCache.py b/src/mem/cache/BaseCache.py index 773a11bea..32f3f0174 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -1,4 +1,33 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.params import * +from m5.proxy import Self from MemObject import MemObject class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] @@ -9,7 +38,7 @@ class BaseCache(MemObject): "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - latency = Param.Int("Latency") + latency = Param.Latency("Latency") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', @@ -49,7 +78,7 @@ class BaseCache(MemObject): "Squash prefetches with a later time on a subsequent miss") prefetch_degree = Param.Int(1, "Degree of the prefetch depth") - prefetch_latency = Param.Tick(10, + prefetch_latency = Param.Latency(10 * Self.latency, "Latency of the prefetcher") prefetch_policy = Param.Prefetch('none', "Type of prefetcher to use") @@ -59,6 +88,5 @@ class BaseCache(MemObject): "Use the CPU ID to seperate calculations of prefetches") prefetch_data_accesses_only = Param.Bool(False, "Only prefetch on data not on instruction accesses") - hit_latency = Param.Int(1,"Hit Latency of the cache") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index 7150719ad..546e037bd 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -30,6 +30,8 @@ Import('*') +SimObject('BaseCache.py') + Source('base_cache.cc') Source('cache.cc') Source('cache_builder.cc') diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index ed665dafb..8aac02460 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -59,8 +59,7 @@ BaseCache::CachePort::recvStatusChange(Port::Status status) } void -BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) +BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) { cache->getAddressRanges(resp, snoop, isCpuSide); } @@ -134,8 +133,7 @@ BaseCache::CachePort::recvRetry() isCpuSide && cache->doSlaveRequest()) { DPRINTF(CachePort, "%s has more responses/requests\n", name()); - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); - reqCpu->schedule(curTick + 1); + new BaseCache::RequestEvent(this, curTick + 1); } waitingOnRetry = false; } @@ -178,8 +176,7 @@ BaseCache::CachePort::recvRetry() { DPRINTF(CachePort, "%s has more requests\n", name()); //Still more to issue, rerequest in 1 cycle - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); - reqCpu->schedule(curTick + 1); + new BaseCache::RequestEvent(this, curTick + 1); } } else @@ -196,8 +193,7 @@ BaseCache::CachePort::recvRetry() { DPRINTF(CachePort, "%s has more requests\n", name()); //Still more to issue, rerequest in 1 cycle - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); - reqCpu->schedule(curTick + 1); + new BaseCache::RequestEvent(this, curTick + 1); } } if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name()); @@ -228,102 +224,109 @@ BaseCache::CachePort::clearBlocked() } } -BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, bool _newResponse) - : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), - newResponse(_newResponse) +BaseCache::RequestEvent::RequestEvent(CachePort *_cachePort, Tick when) + : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) { - if (!newResponse) - this->setFlags(AutoDelete); - pkt = NULL; + this->setFlags(AutoDelete); + schedule(when); } void -BaseCache::CacheEvent::process() +BaseCache::RequestEvent::process() { - if (!newResponse) - { - if (cachePort->waitingOnRetry) return; - //We have some responses to drain first - if (!cachePort->drainList.empty()) { - DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name()); - if (cachePort->sendTiming(cachePort->drainList.front())) { - DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name()); - cachePort->drainList.pop_front(); - if (!cachePort->drainList.empty() || - !cachePort->isCpuSide && cachePort->cache->doMasterRequest() || - cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) { - - DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name()); - this->schedule(curTick + 1); - } - } - else { - cachePort->waitingOnRetry = true; - DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + if (cachePort->waitingOnRetry) return; + //We have some responses to drain first + if (!cachePort->drainList.empty()) { + DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name()); + if (cachePort->sendTiming(cachePort->drainList.front())) { + DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name()); + cachePort->drainList.pop_front(); + if (!cachePort->drainList.empty() || + !cachePort->isCpuSide && cachePort->cache->doMasterRequest() || + cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) { + + DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name()); + this->schedule(curTick + 1); } } - else if (!cachePort->isCpuSide) - { //MSHR - DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name()); - if (!cachePort->cache->doMasterRequest()) { - //This can happen if I am the owner of a block and see an upgrade - //while the block was in my WB Buffers. I just remove the - //wb and de-assert the masterRequest - return; - } + else { + cachePort->waitingOnRetry = true; + DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + } + } + else if (!cachePort->isCpuSide) + { //MSHR + DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name()); + if (!cachePort->cache->doMasterRequest()) { + //This can happen if I am the owner of a block and see an upgrade + //while the block was in my WB Buffers. I just remove the + //wb and de-assert the masterRequest + return; + } - pkt = cachePort->cache->getPacket(); - MSHR* mshr = (MSHR*) pkt->senderState; - //Copy the packet, it may be modified/destroyed elsewhere - PacketPtr copyPkt = new Packet(*pkt); - copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>()); - mshr->pkt = copyPkt; + PacketPtr pkt = cachePort->cache->getPacket(); + MSHR* mshr = (MSHR*) pkt->senderState; + //Copy the packet, it may be modified/destroyed elsewhere + PacketPtr copyPkt = new Packet(*pkt); + copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>()); + mshr->pkt = copyPkt; - bool success = cachePort->sendTiming(pkt); - DPRINTF(Cache, "Address %x was %s in sending the timing request\n", - pkt->getAddr(), success ? "succesful" : "unsuccesful"); + bool success = cachePort->sendTiming(pkt); + DPRINTF(Cache, "Address %x was %s in sending the timing request\n", + pkt->getAddr(), success ? "succesful" : "unsuccesful"); - cachePort->waitingOnRetry = !success; - if (cachePort->waitingOnRetry) { - DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); - } + cachePort->waitingOnRetry = !success; + if (cachePort->waitingOnRetry) { + DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + } - cachePort->cache->sendResult(pkt, mshr, success); - if (success && cachePort->cache->doMasterRequest()) - { - DPRINTF(CachePort, "%s still more MSHR requests to send\n", - cachePort->name()); - //Still more to issue, rerequest in 1 cycle - pkt = NULL; - this->schedule(curTick+1); - } + cachePort->cache->sendResult(pkt, mshr, success); + if (success && cachePort->cache->doMasterRequest()) + { + DPRINTF(CachePort, "%s still more MSHR requests to send\n", + cachePort->name()); + //Still more to issue, rerequest in 1 cycle + this->schedule(curTick+1); } - else + } + else + { + //CSHR + assert(cachePort->cache->doSlaveRequest()); + PacketPtr pkt = cachePort->cache->getCoherencePacket(); + MSHR* cshr = (MSHR*) pkt->senderState; + bool success = cachePort->sendTiming(pkt); + cachePort->cache->sendCoherenceResult(pkt, cshr, success); + cachePort->waitingOnRetry = !success; + if (cachePort->waitingOnRetry) + DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + if (success && cachePort->cache->doSlaveRequest()) { - //CSHR - assert(cachePort->cache->doSlaveRequest()); - pkt = cachePort->cache->getCoherencePacket(); - MSHR* cshr = (MSHR*) pkt->senderState; - bool success = cachePort->sendTiming(pkt); - cachePort->cache->sendCoherenceResult(pkt, cshr, success); - cachePort->waitingOnRetry = !success; - if (cachePort->waitingOnRetry) - DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); - if (success && cachePort->cache->doSlaveRequest()) - { - DPRINTF(CachePort, "%s still more CSHR requests to send\n", - cachePort->name()); - //Still more to issue, rerequest in 1 cycle - pkt = NULL; - this->schedule(curTick+1); - } + DPRINTF(CachePort, "%s still more CSHR requests to send\n", + cachePort->name()); + //Still more to issue, rerequest in 1 cycle + this->schedule(curTick+1); } - return; } - //Else it's a response +} + +const char * +BaseCache::RequestEvent::description() +{ + return "Cache request event"; +} + +BaseCache::ResponseEvent::ResponseEvent(CachePort *_cachePort) + : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) +{ +} + +void +BaseCache::ResponseEvent::process() +{ assert(cachePort->transmitList.size()); assert(cachePort->transmitList.front().first <= curTick); - pkt = cachePort->transmitList.front().second; + PacketPtr pkt = cachePort->transmitList.front().second; cachePort->transmitList.pop_front(); if (!cachePort->transmitList.empty()) { Tick time = cachePort->transmitList.front().first; @@ -354,9 +357,9 @@ BaseCache::CacheEvent::process() } const char * -BaseCache::CacheEvent::description() +BaseCache::ResponseEvent::description() { - return "BaseCache timing event"; + return "Cache response event"; } void diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index ee871c1c4..f06a79dc0 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -87,7 +87,7 @@ class BaseCache : public MemObject virtual void recvStatusChange(Status status); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); virtual int deviceBlockSize(); @@ -117,13 +117,20 @@ class BaseCache : public MemObject std::list<std::pair<Tick,PacketPtr> > transmitList; }; - struct CacheEvent : public Event + struct RequestEvent : public Event { CachePort *cachePort; - PacketPtr pkt; - bool newResponse; - CacheEvent(CachePort *_cachePort, bool response); + RequestEvent(CachePort *_cachePort, Tick when); + void process(); + const char *description(); + }; + + struct ResponseEvent : public Event + { + CachePort *cachePort; + + ResponseEvent(CachePort *_cachePort); void process(); const char *description(); }; @@ -132,8 +139,8 @@ class BaseCache : public MemObject CachePort *cpuSidePort; CachePort *memSidePort; - CacheEvent *sendEvent; - CacheEvent *memSendEvent; + ResponseEvent *sendEvent; + ResponseEvent *memSendEvent; private: void recvStatusChange(Port::Status status, bool isCpuSide) @@ -432,9 +439,7 @@ class BaseCache : public MemObject { if (!doMasterRequest() && !memSidePort->waitingOnRetry) { - BaseCache::CacheEvent * reqCpu = - new BaseCache::CacheEvent(memSidePort, false); - reqCpu->schedule(time); + new RequestEvent(memSidePort, time); } uint8_t flag = 1<<cause; masterRequests |= flag; @@ -469,9 +474,7 @@ class BaseCache : public MemObject { if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry) { - BaseCache::CacheEvent * reqCpu = - new BaseCache::CacheEvent(cpuSidePort, false); - reqCpu->schedule(time); + new RequestEvent(cpuSidePort, time); } uint8_t flag = 1<<cause; slaveRequests |= flag; @@ -653,19 +656,18 @@ class BaseCache : public MemObject */ void rangeChange() {} - void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide) + void getAddressRanges(AddrRangeList &resp, bool &snoop, bool isCpuSide) { if (isCpuSide) { - AddrRangeList dummy; + bool dummy; memSidePort->getPeerAddressRanges(resp, dummy); } else { //This is where snoops get updated AddrRangeList dummy; - cpuSidePort->getPeerAddressRanges(dummy, snoop); - return; + snoop = true; } } diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc index 318b57d50..e887f711e 100644 --- a/src/mem/cache/cache_builder.cc +++ b/src/mem/cache/cache_builder.cc @@ -134,7 +134,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache) Param<bool> prefetch_cache_check_push; Param<bool> prefetch_use_cpu_id; Param<bool> prefetch_data_accesses_only; - Param<int> hit_latency; END_DECLARE_SIM_OBJECT_PARAMS(BaseCache) @@ -190,8 +189,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache) INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"), INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true), INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true), - INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false), - INIT_PARAM_DFLT(hit_latency, "Hit Latecny for a succesful access", 1) + INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false) END_INIT_SIM_OBJECT_PARAMS(BaseCache) @@ -211,7 +209,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache) BUILD_NULL_PREFETCHER(TAGS); \ } \ Cache<TAGS, c>::Params params(tags, mq, coh, base_params, \ - pf, prefetch_access, hit_latency, \ + pf, prefetch_access, latency, \ true, \ store_compressed, \ adaptive_compression, \ diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index c70f10151..9b094c1e3 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1146,11 +1146,11 @@ template<class TagStore, class Coherence> Port * Cache<TagStore,Coherence>::getPort(const std::string &if_name, int idx) { - if (if_name == "") + if (if_name == "" || if_name == "cpu_side") { if (cpuSidePort == NULL) { cpuSidePort = new CpuSidePort(name() + "-cpu_side_port", this); - sendEvent = new CacheEvent(cpuSidePort, true); + sendEvent = new ResponseEvent(cpuSidePort); } return cpuSidePort; } @@ -1158,20 +1158,12 @@ Cache<TagStore,Coherence>::getPort(const std::string &if_name, int idx) { return new CpuSidePort(name() + "-cpu_side_funcport", this); } - else if (if_name == "cpu_side") - { - if (cpuSidePort == NULL) { - cpuSidePort = new CpuSidePort(name() + "-cpu_side_port", this); - sendEvent = new CacheEvent(cpuSidePort, true); - } - return cpuSidePort; - } else if (if_name == "mem_side") { if (memSidePort != NULL) panic("Already have a mem side for this cache\n"); memSidePort = new MemSidePort(name() + "-mem_side_port", this); - memSendEvent = new CacheEvent(memSidePort, true); + memSendEvent = new ResponseEvent(memSidePort); return memSidePort; } else panic("Port name %s unrecognized\n", if_name); @@ -1290,9 +1282,9 @@ template<class TagStore, class Coherence> void Cache<TagStore,Coherence>::MemSidePort::recvFunctional(PacketPtr pkt) { - if (checkFunctional(pkt)) { - myCache()->probe(pkt, false, cache->cpuSidePort); - } + myCache()->probe(pkt, false, cache->cpuSidePort); + if (pkt->result != Packet::Success) + checkFunctional(pkt); } diff --git a/src/python/m5/objects/CoherenceProtocol.py b/src/mem/cache/coherence/CoherenceProtocol.py index 82adb6862..82adb6862 100644 --- a/src/python/m5/objects/CoherenceProtocol.py +++ b/src/mem/cache/coherence/CoherenceProtocol.py diff --git a/src/mem/cache/coherence/SConscript b/src/mem/cache/coherence/SConscript index 03a2d85d7..4f5966140 100644 --- a/src/mem/cache/coherence/SConscript +++ b/src/mem/cache/coherence/SConscript @@ -30,6 +30,8 @@ Import('*') +SimObject('CoherenceProtocol.py') + Source('coherence_protocol.cc') Source('uni_coherence.cc') diff --git a/src/python/m5/objects/Repl.py b/src/mem/cache/tags/Repl.py index b76aa1d6e..b76aa1d6e 100644 --- a/src/python/m5/objects/Repl.py +++ b/src/mem/cache/tags/Repl.py diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript index baf71f687..3fcaec4fa 100644 --- a/src/mem/cache/tags/SConscript +++ b/src/mem/cache/tags/SConscript @@ -38,5 +38,6 @@ Source('split.cc') Source('split_lifo.cc') Source('split_lru.cc') +SimObject('Repl.py') Source('repl/gen.cc') Source('repl/repl.cc') diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 2463a19ba..f70c0cec3 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -192,11 +192,12 @@ fixPacket(PacketPtr func, PacketPtr timing) func->flags |= SATISFIED; return false; } else { - // In this case the timing packet only partially satisfies the - // requset, so we would need more information to make this work. - // Like bytes valid in the packet or something, so the request could - // continue and get this bit of possibly newer data along with the - // older data not written to yet. + // In this case the timing packet only partially satisfies + // the request, so we would need more information to make + // this work. Like bytes valid in the packet or + // something, so the request could continue and get this + // bit of possibly newer data along with the older data + // not written to yet. panic("Timing packet only partially satisfies the functional" "request. Now what?"); } diff --git a/src/mem/packet.hh b/src/mem/packet.hh index dc23e9f6d..c1e6a1e7f 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -506,16 +506,18 @@ class Packet bool intersect(PacketPtr p); }; -/** This function given a functional packet and a timing packet either satisfies - * the timing packet, or updates the timing packet to reflect the updated state - * in the timing packet. It returns if the functional packet should continue to - * traverse the memory hierarchy or not. +/** This function given a functional packet and a timing packet either + * satisfies the timing packet, or updates the timing packet to + * reflect the updated state in the timing packet. It returns if the + * functional packet should continue to traverse the memory hierarchy + * or not. */ bool fixPacket(PacketPtr func, PacketPtr timing); -/** This function is a wrapper for the fixPacket field that toggles the hasData bit - * it is used when a response is waiting in the caches, but hasn't been marked as a - * response yet (so the fixPacket needs to get the correct value for the hasData) +/** This function is a wrapper for the fixPacket field that toggles + * the hasData bit it is used when a response is waiting in the + * caches, but hasn't been marked as a response yet (so the fixPacket + * needs to get the correct value for the hasData) */ bool fixDelayedResponsePacket(PacketPtr func, PacketPtr timing); diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index 96bc23793..b29a07078 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -90,8 +90,6 @@ PageTable::page_check(Addr addr, int64_t size) const } - - void PageTable::allocate(Addr vaddr, int64_t size) { @@ -109,12 +107,7 @@ PageTable::allocate(Addr vaddr, int64_t size) } pTable[vaddr] = system->new_page(); - pTableCache[2].paddr = pTableCache[1].paddr; - pTableCache[2].vaddr = pTableCache[1].vaddr; - pTableCache[1].paddr = pTableCache[0].paddr; - pTableCache[1].vaddr = pTableCache[0].vaddr; - pTableCache[0].paddr = pTable[vaddr]; - pTableCache[0].vaddr = vaddr; + updateCache(vaddr, pTable[vaddr]); } } @@ -126,16 +119,16 @@ PageTable::translate(Addr vaddr, Addr &paddr) Addr page_addr = pageAlign(vaddr); paddr = 0; - if (pTableCache[0].vaddr == vaddr) { - paddr = pTableCache[0].paddr; + if (pTableCache[0].vaddr == page_addr) { + paddr = pTableCache[0].paddr + pageOffset(vaddr); return true; } - if (pTableCache[1].vaddr == vaddr) { - paddr = pTableCache[1].paddr; + if (pTableCache[1].vaddr == page_addr) { + paddr = pTableCache[1].paddr + pageOffset(vaddr); return true; } - if (pTableCache[2].vaddr == vaddr) { - paddr = pTableCache[2].paddr; + if (pTableCache[2].vaddr == page_addr) { + paddr = pTableCache[2].paddr + pageOffset(vaddr); return true; } @@ -145,6 +138,7 @@ PageTable::translate(Addr vaddr, Addr &paddr) return false; } + updateCache(page_addr, iter->second); paddr = iter->second + pageOffset(vaddr); return true; } diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index 0e2b1f58c..64c824238 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -95,6 +95,22 @@ class PageTable */ Fault translate(RequestPtr &req); + /** + * Update the page table cache. + * @param vaddr virtual address (page aligned) to check + * @param paddr physical address (page aligned) to return + */ + inline void updateCache(Addr vaddr, Addr paddr) + { + pTableCache[2].paddr = pTableCache[1].paddr; + pTableCache[2].vaddr = pTableCache[1].vaddr; + pTableCache[1].paddr = pTableCache[0].paddr; + pTableCache[1].vaddr = pTableCache[0].vaddr; + pTableCache[0].paddr = paddr; + pTableCache[0].vaddr = vaddr; + } + + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); }; diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 5d7d7382a..9d840fe69 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -52,7 +52,7 @@ using namespace std; using namespace TheISA; PhysicalMemory::PhysicalMemory(Params *p) - : MemObject(p->name), pmemAddr(NULL), port(NULL), lat(p->latency), _params(p) + : MemObject(p->name), pmemAddr(NULL), lat(p->latency), _params(p) { if (params()->addrRange.size() % TheISA::PageBytes != 0) panic("Memory Size not divisible by page size\n"); @@ -76,9 +76,14 @@ PhysicalMemory::PhysicalMemory(Params *p) void PhysicalMemory::init() { - if (!port) - panic("PhysicalMemory not connected to anything!"); - port->sendStatusChange(Port::RangeChange); + if (ports.size() == 0) { + fatal("PhysicalMemory object %s is unconnected!", name()); + } + + for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) { + if (*pi) + (*pi)->sendStatusChange(Port::RangeChange); + } } PhysicalMemory::~PhysicalMemory() @@ -335,19 +340,33 @@ PhysicalMemory::doFunctionalAccess(PacketPtr pkt) Port * PhysicalMemory::getPort(const std::string &if_name, int idx) { - if (if_name == "port" && idx == -1) { - if (port != NULL) - panic("PhysicalMemory::getPort: additional port requested to memory!"); - port = new MemoryPort(name() + "-port", this); - return port; - } else if (if_name == "functional") { - /* special port for functional writes at startup. And for memtester */ - return new MemoryPort(name() + "-funcport", this); - } else { + // Accept request for "functional" port for backwards compatibility + // with places where this function is called from C++. I'd prefer + // to move all these into Python someday. + if (if_name == "functional") { + return new MemoryPort(csprintf("%s-functional", name()), this); + } + + if (if_name != "port") { panic("PhysicalMemory::getPort: unknown port %s requested", if_name); } + + if (idx >= ports.size()) { + ports.resize(idx+1); + } + + if (ports[idx] != NULL) { + panic("PhysicalMemory::getPort: port %d already assigned", idx); + } + + MemoryPort *port = + new MemoryPort(csprintf("%s-port%d", name(), idx), this); + + ports[idx] = port; + return port; } + void PhysicalMemory::recvStatusChange(Port::Status status) { @@ -366,18 +385,17 @@ PhysicalMemory::MemoryPort::recvStatusChange(Port::Status status) void PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { memory->getAddressRanges(resp, snoop); } void -PhysicalMemory::getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) +PhysicalMemory::getAddressRanges(AddrRangeList &resp, bool &snoop) { - snoop.clear(); + snoop = false; resp.clear(); - resp.push_back(RangeSize(start(), - params()->addrRange.size())); + resp.push_back(RangeSize(start(), params()->addrRange.size())); } int @@ -396,20 +414,7 @@ PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt) void PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt) { - //Since we are overriding the function, make sure to have the impl of the - //check or functional accesses here. - std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin(); - std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end(); - bool notDone = true; - - while (i != end && notDone) { - PacketPtr target = i->second; - // If the target contains data, and it overlaps the - // probed request, need to update data - if (target->intersect(pkt)) - notDone = fixPacket(pkt, target); - i++; - } + checkFunctional(pkt); // Default implementation of SimpleTimingPort::recvFunctional() // calls recvAtomic() and throws away the latency; we can save a @@ -420,7 +425,11 @@ PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt) unsigned int PhysicalMemory::drain(Event *de) { - int count = port->drain(de); + int count = 0; + for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) { + count += (*pi)->drain(de); + } + if (count) changeState(Draining); else diff --git a/src/mem/physical.hh b/src/mem/physical.hh index f7200b502..b9af5d334 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -64,7 +64,7 @@ class PhysicalMemory : public MemObject virtual void recvStatusChange(Status status); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); virtual int deviceBlockSize(); }; @@ -141,9 +141,10 @@ class PhysicalMemory : public MemObject } uint8_t *pmemAddr; - MemoryPort *port; int pagePtr; Tick lat; + std::vector<MemoryPort*> ports; + typedef std::vector<MemoryPort*>::iterator PortIterator; public: Addr new_page(); @@ -168,7 +169,7 @@ class PhysicalMemory : public MemObject public: int deviceBlockSize(); - void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop); + void getAddressRanges(AddrRangeList &resp, bool &snoop); virtual Port *getPort(const std::string &if_name, int idx = -1); void virtual init(); unsigned int drain(Event *de); diff --git a/src/mem/port.hh b/src/mem/port.hh index 877e00293..b23de6050 100644 --- a/src/mem/port.hh +++ b/src/mem/port.hh @@ -172,7 +172,7 @@ class Port @param snoop is a list of ranges snooped */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { panic("??"); } public: @@ -222,7 +222,7 @@ class Port /** Called by the associated device if it wishes to find out the address ranges connected to the peer ports devices. */ - void getPeerAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) + void getPeerAddressRanges(AddrRangeList &resp, bool &snoop) { peer->getDeviceAddressRanges(resp, snoop); } /** This function is a wrapper around sendFunctional() diff --git a/src/mem/tport.cc b/src/mem/tport.cc index 9a4bd7967..ed4c0c172 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -31,23 +31,30 @@ #include "mem/tport.hh" void -SimpleTimingPort::recvFunctional(PacketPtr pkt) +SimpleTimingPort::checkFunctional(PacketPtr pkt) { - std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin(); - std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end(); - bool notDone = true; + DeferredPacketIterator i = transmitList.begin(); + DeferredPacketIterator end = transmitList.end(); - while (i != end && notDone) { - PacketPtr target = i->second; + for (; i != end; ++i) { + PacketPtr target = i->pkt; // If the target contains data, and it overlaps the // probed request, need to update data - if (target->intersect(pkt)) - notDone = fixPacket(pkt, target); - - i++; + if (target->intersect(pkt)) { + if (!fixPacket(pkt, target)) { + // fixPacket returns true for continue, false for done + return; + } + } } +} - //Then just do an atomic access and throw away the returned latency +void +SimpleTimingPort::recvFunctional(PacketPtr pkt) +{ + checkFunctional(pkt); + + // Just do an atomic access and throw away the returned latency if (pkt->result != Packet::Success) recvAtomic(pkt); } @@ -65,93 +72,94 @@ SimpleTimingPort::recvTiming(PacketPtr pkt) // turn packet around to go back to requester if response expected if (pkt->needsResponse()) { pkt->makeTimingResponse(); - sendTiming(pkt, latency); + schedSendTiming(pkt, curTick + latency); } - else { - if (pkt->cmd != MemCmd::UpgradeReq) - { - delete pkt->req; - delete pkt; - } + else if (pkt->cmd != MemCmd::UpgradeReq) { + delete pkt->req; + delete pkt; } return true; } -void -SimpleTimingPort::recvRetry() -{ - assert(!transmitList.empty()); - if (Port::sendTiming(transmitList.front().second)) { - transmitList.pop_front(); - DPRINTF(Bus, "No Longer waiting on retry\n"); - if (!transmitList.empty()) { - Tick time = transmitList.front().first; - sendEvent.schedule(time <= curTick ? curTick+1 : time); - } - } - - if (transmitList.empty() && drainEvent) { - drainEvent->process(); - drainEvent = NULL; - } -} void -SimpleTimingPort::sendTiming(PacketPtr pkt, Tick time) +SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when) { + assert(when > curTick); + // Nothing is on the list: add it and schedule an event if (transmitList.empty()) { - assert(!sendEvent.scheduled()); - sendEvent.schedule(curTick+time); - transmitList.push_back(std::pair<Tick,PacketPtr>(time+curTick,pkt)); + assert(!sendEvent->scheduled()); + sendEvent->schedule(when); + transmitList.push_back(DeferredPacket(when, pkt)); return; } // something is on the list and this belongs at the end - if (time+curTick >= transmitList.back().first) { - transmitList.push_back(std::pair<Tick,PacketPtr>(time+curTick,pkt)); + if (when >= transmitList.back().tick) { + transmitList.push_back(DeferredPacket(when, pkt)); return; } // Something is on the list and this belongs somewhere else - std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin(); - std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end(); - bool done = false; + DeferredPacketIterator i = transmitList.begin(); + DeferredPacketIterator end = transmitList.end(); - while (i != end && !done) { - if (time+curTick < i->first) { + for (; i != end; ++i) { + if (when < i->tick) { if (i == transmitList.begin()) { //Inserting at begining, reschedule - sendEvent.reschedule(time+curTick); + sendEvent->reschedule(when); } - transmitList.insert(i,std::pair<Tick,PacketPtr>(time+curTick,pkt)); - done = true; + transmitList.insert(i, DeferredPacket(when, pkt)); + return; } - i++; } - assert(done); + assert(false); // should never get here } + void -SimpleTimingPort::SendEvent::process() +SimpleTimingPort::sendDeferredPacket() { - assert(port->transmitList.size()); - assert(port->transmitList.front().first <= curTick); - if (port->Port::sendTiming(port->transmitList.front().second)) { + assert(deferredPacketReady()); + bool success = sendTiming(transmitList.front().pkt); + + if (success) { //send successful, remove packet - port->transmitList.pop_front(); - if (!port->transmitList.empty()) { - Tick time = port->transmitList.front().first; - schedule(time <= curTick ? curTick+1 : time); + transmitList.pop_front(); + if (!transmitList.empty()) { + Tick time = transmitList.front().tick; + sendEvent->schedule(time <= curTick ? curTick+1 : time); } - if (port->transmitList.empty() && port->drainEvent) { - port->drainEvent->process(); - port->drainEvent = NULL; + + if (transmitList.empty() && drainEvent) { + drainEvent->process(); + drainEvent = NULL; } - return; } - // send unsuccessful (due to flow control). Will get retry - // callback later; save for then if not already - DPRINTF(Bus, "Waiting on retry\n"); + + waitingOnRetry = !success; + + if (waitingOnRetry) { + DPRINTF(Bus, "Send failed, waiting on retry\n"); + } +} + + +void +SimpleTimingPort::recvRetry() +{ + DPRINTF(Bus, "Received retry\n"); + assert(waitingOnRetry); + sendDeferredPacket(); +} + + +void +SimpleTimingPort::processSendEvent() +{ + assert(!waitingOnRetry); + sendDeferredPacket(); } diff --git a/src/mem/tport.hh b/src/mem/tport.hh index 3d28ea3e5..ea0f05ed1 100644 --- a/src/mem/tport.hh +++ b/src/mem/tport.hh @@ -58,9 +58,26 @@ class SimpleTimingPort : public Port { protected: + /** A deferred packet, buffered to transmit later. */ + class DeferredPacket { + public: + Tick tick; ///< The tick when the packet is ready to transmit + PacketPtr pkt; ///< Pointer to the packet to transmit + DeferredPacket(Tick t, PacketPtr p) + : tick(t), pkt(p) + {} + }; + + typedef std::list<DeferredPacket> DeferredPacketList; + typedef std::list<DeferredPacket>::iterator DeferredPacketIterator; + /** A list of outgoing timing response packets that haven't been * serviced yet. */ - std::list<std::pair<Tick,PacketPtr> > transmitList; + DeferredPacketList transmitList; + + /** This function attempts to send deferred packets. Scheduled to + * be called in the future via SendEvent. */ + void processSendEvent(); /** * This class is used to implemented sendTiming() with a delay. When @@ -68,32 +85,38 @@ class SimpleTimingPort : public Port * When the event time expires it attempts to send the packet. * If it cannot, the packet sent when recvRetry() is called. **/ - class SendEvent : public Event - { - SimpleTimingPort *port; - - public: - SendEvent(SimpleTimingPort *p) - : Event(&mainEventQueue), port(p) - { } - - virtual void process(); + typedef EventWrapper<SimpleTimingPort, &SimpleTimingPort::processSendEvent> + SendEvent; - virtual const char *description() - { return "Future scheduled sendTiming event"; } - }; - - SendEvent sendEvent; + Event *sendEvent; /** If we need to drain, keep the drain event around until we're done * here.*/ Event *drainEvent; + /** Remember whether we're awaiting a retry from the bus. */ + bool waitingOnRetry; + + /** Check the list of buffered packets against the supplied + * functional request. */ + void checkFunctional(PacketPtr funcPkt); + + /** Check whether we have a packet ready to go on the transmit list. */ + bool deferredPacketReady() + { return !transmitList.empty() && transmitList.front().tick <= curTick; } + /** Schedule a sendTiming() event to be called in the future. * @param pkt packet to send - * @param time increment from now (in ticks) to send packet + * @param absolute time (in ticks) to send packet + */ + void schedSendTiming(PacketPtr pkt, Tick when); + + /** Attempt to send the packet at the head of the deferred packet + * list. Caller must guarantee that the deferred packet list is + * non-empty and that the head packet is scheduled for curTick (or + * earlier). */ - void sendTiming(PacketPtr pkt, Tick time); + void sendDeferredPacket(); /** This function is notification that the device should attempt to send a * packet again. */ @@ -115,9 +138,14 @@ class SimpleTimingPort : public Port public: SimpleTimingPort(std::string pname, MemObject *_owner = NULL) - : Port(pname, _owner), sendEvent(this), drainEvent(NULL) + : Port(pname, _owner), + sendEvent(new SendEvent(this)), + drainEvent(NULL), + waitingOnRetry(false) {} + ~SimpleTimingPort() { delete sendEvent; } + /** Hook for draining timing accesses from the system. The * associated SimObject's drain() functions should be implemented * something like this when this class is used: diff --git a/src/python/SConscript b/src/python/SConscript index 3c5ab4da1..66b852d25 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -60,56 +60,3 @@ SwigSource('m5.internal', 'swig/sim_object.i') SwigSource('m5.internal', 'swig/stats.i') SwigSource('m5.internal', 'swig/trace.i') PySource('m5.internal', 'm5/internal/__init__.py') - -SimObject('m5/objects/AlphaConsole.py') -SimObject('m5/objects/AlphaTLB.py') -SimObject('m5/objects/BadDevice.py') -SimObject('m5/objects/BaseCPU.py') -SimObject('m5/objects/BaseCache.py') -SimObject('m5/objects/BaseHier.py') -SimObject('m5/objects/BaseMem.py') -SimObject('m5/objects/BaseMemory.py') -SimObject('m5/objects/BranchPred.py') -SimObject('m5/objects/Bridge.py') -SimObject('m5/objects/Bus.py') -SimObject('m5/objects/Checker.py') -SimObject('m5/objects/CoherenceProtocol.py') -SimObject('m5/objects/DRAMMemory.py') -SimObject('m5/objects/Device.py') -SimObject('m5/objects/DiskImage.py') -SimObject('m5/objects/Ethernet.py') -SimObject('m5/objects/FUPool.py') -SimObject('m5/objects/FastCPU.py') -#SimObject('m5/objects/FreebsdSystem.py') -SimObject('m5/objects/FullCPU.py') -SimObject('m5/objects/FuncUnit.py') -SimObject('m5/objects/FuncUnitConfig.py') -SimObject('m5/objects/FunctionalMemory.py') -SimObject('m5/objects/HierParams.py') -SimObject('m5/objects/Ide.py') -SimObject('m5/objects/IntrControl.py') -SimObject('m5/objects/LinuxSystem.py') -SimObject('m5/objects/MainMemory.py') -SimObject('m5/objects/MemObject.py') -SimObject('m5/objects/MemTest.py') -SimObject('m5/objects/MemoryController.py') -SimObject('m5/objects/O3CPU.py') -SimObject('m5/objects/OzoneCPU.py') -SimObject('m5/objects/Pci.py') -SimObject('m5/objects/PhysicalMemory.py') -SimObject('m5/objects/PipeTrace.py') -SimObject('m5/objects/Platform.py') -SimObject('m5/objects/Process.py') -SimObject('m5/objects/Repl.py') -SimObject('m5/objects/Root.py') -SimObject('m5/objects/Sampler.py') -SimObject('m5/objects/SimConsole.py') -SimObject('m5/objects/SimpleCPU.py') -SimObject('m5/objects/SimpleDisk.py') -#SimObject('m5/objects/SimpleOzoneCPU.py') -SimObject('m5/objects/SparcTLB.py') -SimObject('m5/objects/System.py') -SimObject('m5/objects/T1000.py') -#SimObject('m5/objects/Tru64System.py') -SimObject('m5/objects/Tsunami.py') -SimObject('m5/objects/Uart.py') diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 42266a80e..f87e13732 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -722,6 +722,13 @@ class SimObject(object): for child in self._children.itervalues(): child.resume() + def getMemoryMode(self): + if not isinstance(self, m5.objects.System): + return None + + system_ptr = internal.sim_object.convertToSystemPtr(self._ccObject) + return system_ptr.getMemoryMode() + def changeTiming(self, mode): if isinstance(self, m5.objects.System): # i don't know if there's a better way to do this - calling diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 06dc92bc6..a9206a474 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -190,17 +190,20 @@ def changeToAtomic(system): if not isinstance(system, (objects.Root, objects.System)): raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ (type(system), objects.Root, objects.System) - doDrain(system) - print "Changing memory mode to atomic" - system.changeTiming(internal.sim_object.SimObject.Atomic) + if system.getMemoryMode() != internal.sim_object.SimObject.Atomic: + doDrain(system) + print "Changing memory mode to atomic" + system.changeTiming(internal.sim_object.SimObject.Atomic) def changeToTiming(system): if not isinstance(system, (objects.Root, objects.System)): raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ (type(system), objects.Root, objects.System) - doDrain(system) - print "Changing memory mode to timing" - system.changeTiming(internal.sim_object.SimObject.Timing) + + if system.getMemoryMode() != internal.sim_object.SimObject.Timing: + doDrain(system) + print "Changing memory mode to timing" + system.changeTiming(internal.sim_object.SimObject.Timing) def switchCpus(cpuList): print "switching cpus" diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py deleted file mode 100644 index f968aaa40..000000000 --- a/src/python/m5/objects/AlphaConsole.py +++ /dev/null @@ -1,10 +0,0 @@ -from m5.params import * -from m5.proxy import * -from Device import BasicPioDevice - -class AlphaConsole(BasicPioDevice): - type = 'AlphaConsole' - cpu = Param.BaseCPU(Parent.cpu[0], "Processor") - disk = Param.SimpleDisk("Simple Disk") - sim_console = Param.SimConsole(Parent.any, "The Simulator Console") - system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/python/m5/objects/AlphaTLB.py b/src/python/m5/objects/AlphaTLB.py deleted file mode 100644 index af7c04a84..000000000 --- a/src/python/m5/objects/AlphaTLB.py +++ /dev/null @@ -1,14 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class AlphaTLB(SimObject): - type = 'AlphaTLB' - abstract = True - size = Param.Int("TLB size") - -class AlphaDTB(AlphaTLB): - type = 'AlphaDTB' - size = 64 - -class AlphaITB(AlphaTLB): - type = 'AlphaITB' - size = 48 diff --git a/src/python/m5/objects/BadDevice.py b/src/python/m5/objects/BadDevice.py deleted file mode 100644 index 919623887..000000000 --- a/src/python/m5/objects/BadDevice.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.params import * -from Device import BasicPioDevice - -class BadDevice(BasicPioDevice): - type = 'BadDevice' - devicename = Param.String("Name of device to error on") diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py deleted file mode 100644 index 33b24ad3c..000000000 --- a/src/python/m5/objects/Bridge.py +++ /dev/null @@ -1,16 +0,0 @@ -from m5.params import * -from MemObject import MemObject - -class Bridge(MemObject): - type = 'Bridge' - side_a = Port('Side A port') - side_b = Port('Side B port') - req_size_a = Param.Int(16, "The number of requests to buffer") - req_size_b = Param.Int(16, "The number of requests to buffer") - resp_size_a = Param.Int(16, "The number of requests to buffer") - resp_size_b = Param.Int(16, "The number of requests to buffer") - delay = Param.Latency('0ns', "The latency of this bridge") - nack_delay = Param.Latency('0ns', "The latency of this bridge") - write_ack = Param.Bool(False, "Should this bridge ack writes") - fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") - fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py deleted file mode 100644 index 48dbbe307..000000000 --- a/src/python/m5/objects/Bus.py +++ /dev/null @@ -1,19 +0,0 @@ -from m5 import build_env -from m5.params import * -from m5.proxy import * -from MemObject import MemObject -from Device import BadAddr - -class Bus(MemObject): - type = 'Bus' - port = VectorPort("vector port for connecting devices") - bus_id = Param.Int(0, "blah") - clock = Param.Clock("1GHz", "bus clock speed") - width = Param.Int(64, "bus width (bytes)") - responder_set = Param.Bool(False, "Did the user specify a default responder.") - block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") - if build_env['FULL_SYSTEM']: - responder = BadAddr(pio_addr=0x0, pio_latency="1ps") - default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") - else: - default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py deleted file mode 100644 index d0ada7ee1..000000000 --- a/src/python/m5/objects/DiskImage.py +++ /dev/null @@ -1,16 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class DiskImage(SimObject): - type = 'DiskImage' - abstract = True - image_file = Param.String("disk image file") - read_only = Param.Bool(False, "read only image") - -class RawDiskImage(DiskImage): - type = 'RawDiskImage' - -class CowDiskImage(DiskImage): - type = 'CowDiskImage' - child = Param.DiskImage(RawDiskImage(read_only=True), - "child image") - table_size = Param.Int(65536, "initial table size") diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py deleted file mode 100644 index 916183bd7..000000000 --- a/src/python/m5/objects/FUPool.py +++ /dev/null @@ -1,12 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from FuncUnit import * -from FuncUnitConfig import * - -class FUPool(SimObject): - type = 'FUPool' - FUList = VectorParam.FUDesc("list of FU's for this pool") - -class DefaultFUPool(FUPool): - FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), - WritePort(), RdWrPort(), IprPort() ] diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py deleted file mode 100644 index f0ad55f7a..000000000 --- a/src/python/m5/objects/FuncUnit.py +++ /dev/null @@ -1,18 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * - -class OpType(Enum): - vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', - 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', - 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] - -class OpDesc(SimObject): - type = 'OpDesc' - issueLat = Param.Int(1, "cycles until another can be issued") - opClass = Param.OpType("type of operation") - opLat = Param.Int(1, "cycles until result is available") - -class FUDesc(SimObject): - type = 'FUDesc' - count = Param.Int("number of these FU's available") - opList = VectorParam.OpDesc("operation classes for this FU type") diff --git a/src/python/m5/objects/FuncUnitConfig.py b/src/python/m5/objects/FuncUnitConfig.py deleted file mode 100644 index 43d7a4bb7..000000000 --- a/src/python/m5/objects/FuncUnitConfig.py +++ /dev/null @@ -1,41 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from FuncUnit import * - -class IntALU(FUDesc): - opList = [ OpDesc(opClass='IntAlu') ] - count = 6 - -class IntMultDiv(FUDesc): - opList = [ OpDesc(opClass='IntMult', opLat=3), - OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ] - count=2 - -class FP_ALU(FUDesc): - opList = [ OpDesc(opClass='FloatAdd', opLat=2), - OpDesc(opClass='FloatCmp', opLat=2), - OpDesc(opClass='FloatCvt', opLat=2) ] - count = 4 - -class FP_MultDiv(FUDesc): - opList = [ OpDesc(opClass='FloatMult', opLat=4), - OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), - OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] - count = 2 - -class ReadPort(FUDesc): - opList = [ OpDesc(opClass='MemRead') ] - count = 0 - -class WritePort(FUDesc): - opList = [ OpDesc(opClass='MemWrite') ] - count = 0 - -class RdWrPort(FUDesc): - opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] - count = 4 - -class IprPort(FUDesc): - opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ] - count = 1 - diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py deleted file mode 100644 index ef7e28785..000000000 --- a/src/python/m5/objects/Ide.py +++ /dev/null @@ -1,40 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from Pci import PciDevice, PciConfigData - -class IdeID(Enum): vals = ['master', 'slave'] - -class IdeControllerPciData(PciConfigData): - VendorID = 0x8086 - DeviceID = 0x7111 - Command = 0x0 - Status = 0x280 - Revision = 0x0 - ClassCode = 0x01 - SubClassCode = 0x01 - ProgIF = 0x85 - BAR0 = 0x00000001 - BAR1 = 0x00000001 - BAR2 = 0x00000001 - BAR3 = 0x00000001 - BAR4 = 0x00000001 - BAR5 = 0x00000001 - InterruptLine = 0x1f - InterruptPin = 0x01 - BAR0Size = '8B' - BAR1Size = '4B' - BAR2Size = '8B' - BAR3Size = '4B' - BAR4Size = '16B' - -class IdeDisk(SimObject): - type = 'IdeDisk' - delay = Param.Latency('1us', "Fixed disk delay in microseconds") - driveID = Param.IdeID('master', "Drive ID") - image = Param.DiskImage("Disk image") - -class IdeController(PciDevice): - type = 'IdeController' - disks = VectorParam.IdeDisk("IDE disks attached to this controller") - - configdata =IdeControllerPciData() diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py deleted file mode 100644 index 398ba47f9..000000000 --- a/src/python/m5/objects/IntrControl.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class IntrControl(SimObject): - type = 'IntrControl' - sys = Param.System(Parent.any, "the system we are part of") diff --git a/src/python/m5/objects/MemObject.py b/src/python/m5/objects/MemObject.py deleted file mode 100644 index 8982d553d..000000000 --- a/src/python/m5/objects/MemObject.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.SimObject import SimObject -from m5.SimObject import SimObject - -class MemObject(SimObject): - type = 'MemObject' - abstract = True diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py deleted file mode 100644 index 1219ddd4d..000000000 --- a/src/python/m5/objects/MemTest.py +++ /dev/null @@ -1,24 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5 import build_env - -class MemTest(SimObject): - type = 'MemTest' - max_loads = Param.Counter("number of loads to execute") - atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n") - memory_size = Param.Int(65536, "memory size") - percent_dest_unaligned = Param.Percent(50, - "percent of copy dest address that are unaligned") - percent_reads = Param.Percent(65, "target read percentage") - percent_source_unaligned = Param.Percent(50, - "percent of copy source address that are unaligned") - percent_functional = Param.Percent(50, "percent of access that are functional") - percent_uncacheable = Param.Percent(10, - "target uncacheable percentage") - progress_interval = Param.Counter(1000000, - "progress report interval (in accesses)") - trace_addr = Param.Addr(0, "address to trace") - - test = Port("Port to the memory system to test") - functional = Port("Port to the functional memory used for verification") diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py deleted file mode 100644 index c389e4a7f..000000000 --- a/src/python/m5/objects/PhysicalMemory.py +++ /dev/null @@ -1,30 +0,0 @@ -from m5.params import * -from m5.proxy import * -from MemObject import * - -class PhysicalMemory(MemObject): - type = 'PhysicalMemory' - port = Port("the access port") - functional = Port("Functional Access Port") - range = Param.AddrRange(AddrRange('128MB'), "Device Address") - file = Param.String('', "memory mapped file") - latency = Param.Latency('1t', "latency of an access") - zero = Param.Bool(False, "zero initialize memory") - -class DRAMMemory(PhysicalMemory): - type = 'DRAMMemory' - # Many of these should be observed from the configuration - cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") - mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") - mem_actpolicy = Param.String("open", "Open/Close policy") - memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") - bus_width = Param.Int(16, "") - act_lat = Param.Int(2, "RAS to CAS delay") - cas_lat = Param.Int(1, "CAS delay") - war_lat = Param.Int(2, "write after read delay") - pre_lat = Param.Int(2, "precharge delay") - dpl_lat = Param.Int(2, "data in to precharge delay") - trc_lat = Param.Int(6, "row cycle delay") - num_banks = Param.Int(4, "Number of Banks") - num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") - diff --git a/src/python/m5/objects/Platform.py b/src/python/m5/objects/Platform.py deleted file mode 100644 index ab2083eea..000000000 --- a/src/python/m5/objects/Platform.py +++ /dev/null @@ -1,7 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class Platform(SimObject): - type = 'Platform' - abstract = True - intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/src/python/m5/objects/Process.py b/src/python/m5/objects/Process.py deleted file mode 100644 index 79268e6f4..000000000 --- a/src/python/m5/objects/Process.py +++ /dev/null @@ -1,36 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class Process(SimObject): - type = 'Process' - abstract = True - output = Param.String('cout', 'filename for stdout/stderr') - system = Param.System(Parent.any, "system process will run on") - -class LiveProcess(Process): - type = 'LiveProcess' - executable = Param.String('', "executable (overrides cmd[0] if set)") - cmd = VectorParam.String("command line (executable plus arguments)") - env = VectorParam.String('', "environment settings") - cwd = Param.String('', "current working directory") - input = Param.String('cin', "filename for stdin") - uid = Param.Int(100, 'user id') - euid = Param.Int(100, 'effective user id') - gid = Param.Int(100, 'group id') - egid = Param.Int(100, 'effective group id') - pid = Param.Int(100, 'process id') - ppid = Param.Int(99, 'parent process id') - -class AlphaLiveProcess(LiveProcess): - type = 'AlphaLiveProcess' - -class SparcLiveProcess(LiveProcess): - type = 'SparcLiveProcess' - -class MipsLiveProcess(LiveProcess): - type = 'MipsLiveProcess' - -class EioProcess(Process): - type = 'EioProcess' - chkpt = Param.String('', "EIO checkpoint file name (optional)") - file = Param.String("EIO trace file name") diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py deleted file mode 100644 index 2b0e736e7..000000000 --- a/src/python/m5/objects/Root.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * - -class Root(SimObject): - type = 'Root' - dummy = Param.Int(0, "We don't support objects without params") diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py deleted file mode 100644 index dfad18eb6..000000000 --- a/src/python/m5/objects/SimConsole.py +++ /dev/null @@ -1,11 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * - -class SimConsole(SimObject): - type = 'SimConsole' - append_name = Param.Bool(True, "append name() to filename") - intr_control = Param.IntrControl(Parent.any, "interrupt controller") - port = Param.TcpPort(3456, "listen port") - number = Param.Int(0, "console number") - output = Param.String('console', "file to dump output to") diff --git a/src/python/m5/objects/SimpleDisk.py b/src/python/m5/objects/SimpleDisk.py deleted file mode 100644 index 099a77dbb..000000000 --- a/src/python/m5/objects/SimpleDisk.py +++ /dev/null @@ -1,7 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class SimpleDisk(SimObject): - type = 'SimpleDisk' - disk = Param.DiskImage("Disk Image") - system = Param.System(Parent.any, "Sysetm Pointer") diff --git a/src/python/m5/objects/SparcTLB.py b/src/python/m5/objects/SparcTLB.py deleted file mode 100644 index 06d2a8231..000000000 --- a/src/python/m5/objects/SparcTLB.py +++ /dev/null @@ -1,14 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class SparcTLB(SimObject): - type = 'SparcTLB' - abstract = True - size = Param.Int("TLB size") - -class SparcDTB(SparcTLB): - type = 'SparcDTB' - size = 64 - -class SparcITB(SparcTLB): - type = 'SparcITB' - size = 64 diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py deleted file mode 100644 index 810a320be..000000000 --- a/src/python/m5/objects/System.py +++ /dev/null @@ -1,68 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5 import build_env -from PhysicalMemory import * - -class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] - -class System(SimObject): - type = 'System' - physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") - mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") - if build_env['FULL_SYSTEM']: - boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, - "boot processor frequency") - init_param = Param.UInt64(0, "numerical value to pass into simulator") - boot_osflags = Param.String("a", "boot flags to pass to the kernel") - kernel = Param.String("", "file that contains the kernel code") - readfile = Param.String("", "file to read startup script from") - symbolfile = Param.String("", "file to get the symbols from") - -class AlphaSystem(System): - type = 'AlphaSystem' - console = Param.String("file that contains the console code") - pal = Param.String("file that contains palcode") - system_type = Param.UInt64("Type of system we are emulating") - system_rev = Param.UInt64("Revision of system we are emulating") - -class SparcSystem(System): - type = 'SparcSystem' - _rom_base = 0xfff0000000 - _nvram_base = 0x1f11000000 - _hypervisor_desc_base = 0x1f12080000 - _partition_desc_base = 0x1f12000000 - # ROM for OBP/Reset/Hypervisor - rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')), - "Memory to hold the ROM data") - # nvram - nvram = Param.PhysicalMemory( - PhysicalMemory(range = AddrRange(_nvram_base, size = '8kB')), - "Memory to hold the nvram data") - # hypervisor description - hypervisor_desc = Param.PhysicalMemory( - PhysicalMemory(range = AddrRange(_hypervisor_desc_base, size = '8kB')), - "Memory to hold the hypervisor description") - # partition description - partition_desc = Param.PhysicalMemory( - PhysicalMemory(range = AddrRange(_partition_desc_base, size = '8kB')), - "Memory to hold the partition description") - - reset_addr = Param.Addr(_rom_base, "Address to load ROM at") - hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base, - "Address to load hypervisor at") - openboot_addr = Param.Addr(Addr('512kB') + _rom_base, - "Address to load openboot at") - nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram") - hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base, - "Address for the hypervisor description") - partition_desc_addr = Param.Addr(_partition_desc_base, - "Address for the partition description") - - reset_bin = Param.String("file that contains the reset code") - hypervisor_bin = Param.String("file that contains the hypervisor code") - openboot_bin = Param.String("file that contains the openboot code") - nvram_bin = Param.String("file that contains the contents of nvram") - hypervisor_desc_bin = Param.String("file that contains the hypervisor description") - partition_desc_bin = Param.String("file that contains the partition description") - diff --git a/src/python/m5/objects/Uart.py b/src/python/m5/objects/Uart.py deleted file mode 100644 index 62062c6b1..000000000 --- a/src/python/m5/objects/Uart.py +++ /dev/null @@ -1,17 +0,0 @@ -from m5.params import * -from m5.proxy import * -from m5 import build_env -from Device import BasicPioDevice - -class Uart(BasicPioDevice): - type = 'Uart' - abstract = True - sim_console = Param.SimConsole(Parent.any, "The console") - -class Uart8250(Uart): - type = 'Uart8250' - -if build_env['ALPHA_TLASER']: - class Uart8530(Uart): - type = 'Uart8530' - diff --git a/src/python/m5/params.py b/src/python/m5/params.py index da7ddd65e..88b162874 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -348,7 +348,7 @@ class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100 class Float(ParamValue, float): - pass + cxx_type = 'double' class MemorySize(CheckedInt): cxx_type = 'uint64_t' diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc index 11141fa84..2a5f2b9fb 100644 --- a/src/python/swig/pyobject.cc +++ b/src/python/swig/pyobject.cc @@ -62,6 +62,7 @@ lookupPort(SimObject *so, const std::string &name, int i) /** * Connect the described MemObject ports. Called from Python via SWIG. + * The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports. */ int connectPorts(SimObject *o1, const std::string &name1, int i1, diff --git a/src/python/swig/sim_object.i b/src/python/swig/sim_object.i index b2af72c61..a1737c438 100644 --- a/src/python/swig/sim_object.i +++ b/src/python/swig/sim_object.i @@ -66,6 +66,7 @@ class System { private: System(); public: + SimObject::MemoryMode getMemoryMode(); void setMemoryMode(SimObject::MemoryMode mode); }; diff --git a/src/sim/Process.py b/src/sim/Process.py new file mode 100644 index 000000000..16be65fd4 --- /dev/null +++ b/src/sim/Process.py @@ -0,0 +1,51 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * + +class Process(SimObject): + type = 'Process' + abstract = True + output = Param.String('cout', 'filename for stdout/stderr') + system = Param.System(Parent.any, "system process will run on") + +class LiveProcess(Process): + type = 'LiveProcess' + executable = Param.String('', "executable (overrides cmd[0] if set)") + cmd = VectorParam.String("command line (executable plus arguments)") + env = VectorParam.String('', "environment settings") + cwd = Param.String('', "current working directory") + input = Param.String('cin', "filename for stdin") + uid = Param.Int(100, 'user id') + euid = Param.Int(100, 'effective user id') + gid = Param.Int(100, 'group id') + egid = Param.Int(100, 'effective group id') + pid = Param.Int(100, 'process id') + ppid = Param.Int(99, 'parent process id') diff --git a/src/sim/Root.py b/src/sim/Root.py new file mode 100644 index 000000000..fff998e0d --- /dev/null +++ b/src/sim/Root.py @@ -0,0 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * + +class Root(SimObject): + type = 'Root' + dummy = Param.Int(0, "We don't support objects without params") diff --git a/src/sim/SConscript b/src/sim/SConscript index 46dc2c8dd..50f966bcf 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -30,6 +30,9 @@ Import('*') +SimObject('Root.py') +SimObject('System.py') + Source('async.cc') Source('builder.cc') Source('core.cc') @@ -50,5 +53,7 @@ Source('system.cc') if env['FULL_SYSTEM']: Source('pseudo_inst.cc') else: + SimObject('Process.py') + Source('process.cc') Source('syscall_emul.cc') diff --git a/src/sim/System.py b/src/sim/System.py new file mode 100644 index 000000000..b37e385c1 --- /dev/null +++ b/src/sim/System.py @@ -0,0 +1,48 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +from m5 import build_env +from PhysicalMemory import * + +class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] + +class System(SimObject): + type = 'System' + physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") + mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") + if build_env['FULL_SYSTEM']: + boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, + "boot processor frequency") + init_param = Param.UInt64(0, "numerical value to pass into simulator") + boot_osflags = Param.String("a", "boot flags to pass to the kernel") + kernel = Param.String("", "file that contains the kernel code") + readfile = Param.String("", "file to read startup script from") + symbolfile = Param.String("", "file to get the symbols from") diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index 974313968..6fbba46d5 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -293,13 +293,25 @@ class EventWrapper : public Event T *object; public: - EventWrapper(T *obj, bool del = false, EventQueue *q = &mainEventQueue, + EventWrapper(T *obj, bool del = false, + EventQueue *q = &mainEventQueue, Priority p = Default_Pri) : Event(q, p), object(obj) { if (del) setFlags(AutoDelete); } + + EventWrapper(T *obj, Tick t, bool del = false, + EventQueue *q = &mainEventQueue, + Priority p = Default_Pri) + : Event(q, p), object(obj) + { + if (del) + setFlags(AutoDelete); + schedule(t); + } + void process() { (object->*F)(); } }; |