summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/isa/decoder/thumb.isa3
-rw-r--r--src/arch/arm/isa/formats/macromem.isa13
2 files changed, 14 insertions, 2 deletions
diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa
index 56dbcfe28..7fb8dd854 100644
--- a/src/arch/arm/isa/decoder/thumb.isa
+++ b/src/arch/arm/isa/decoder/thumb.isa
@@ -137,8 +137,7 @@
}
}
0x6: decode TOPCODE_12_11 {
- 0x0: WarnUnimpl::stm(); // also stmia, stmea
- 0x1: WarnUnimpl::ldm(); // also ldmia, ldmea
+ 0x0, 0x1: Thumb16MacroMem::thumb16MacroMem();
default: decode TOPCODE_11_8 {
0xe: WarnUnimpl::undefined(); // permanently undefined
0xf: WarnUnimpl::svc(); // formerly swi
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa
index 95b7ccd6a..98505be84 100644
--- a/src/arch/arm/isa/formats/macromem.isa
+++ b/src/arch/arm/isa/formats/macromem.isa
@@ -43,3 +43,16 @@ def format ArmMacroMem() {{
PSRUSER, WRITEBACK, LOADOP, machInst.regList);
'''
}};
+
+def format Thumb16MacroMem() {{
+ decode_block = '''
+ {
+ const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
+ const bool load = (bits(machInst, 11) == 1);
+ const uint32_t regList = bits(machInst, 7, 0);
+ const bool writeback = (!load || bits(regList, rn) == 0);
+ return new LdmStm(machInst, rn, true, true, false,
+ writeback, load, regList);
+ }
+ '''
+}};