8 files changed, 0 insertions, 32 deletions
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 54b8003be..61688b5c8 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -45,9 +45,6 @@ using namespace LittleEndianGuest;
 
 StaticInstPtr decodeInst(ExtMachInst);
 
-// Alpha Does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;
 const Addr PageMask = ~(PageBytes - 1);
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index fa2779558..5763e7747 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -57,9 +57,6 @@ namespace ArmISA
 
     StaticInstPtr decodeInst(ExtMachInst);
 
-    // ARM DOES NOT have a delay slot
-    #define ISA_HAS_DELAY_SLOT 0
-
     const Addr PageShift = 12;
     const Addr PageBytes = ULL(1) << PageShift;
     const Addr Page_Mask = ~(PageBytes - 1);
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 7a1607183..6e08c7e85 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -47,9 +47,6 @@ using namespace LittleEndianGuest;
 
 StaticInstPtr decodeInst(ExtMachInst);
 
-// MIPS DOES have a delay slot
-#define ISA_HAS_DELAY_SLOT 1
-
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;
 const Addr Page_Mask = ~(PageBytes - 1);
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 41a8d7d1b..9afe6803a 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -48,9 +48,6 @@ using namespace BigEndianGuest;
 
 StaticInstPtr decodeInst(ExtMachInst);
 
-// POWER DOES NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;
 const Addr Page_Mask = ~(PageBytes - 1);
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 21e684a25..abafad2e2 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -57,9 +57,6 @@ namespace RiscvISA
 
 using namespace LittleEndianGuest;
 
-// Riscv does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;
 
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 4f98f7580..58d8437ad 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,9 +44,6 @@ namespace SparcISA
 // This makes sure the big endian versions of certain functions are used.
 using namespace BigEndianGuest;
 
-// SPARC has a delay slot
-#define ISA_HAS_DELAY_SLOT 1
-
 // real address virtual mapping
 // sort of like alpha super page, but less frequently used
 const Addr SegKPMEnd  = ULL(0xfffffffc00000000);
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 2b19b1ba7..158e2f9e4 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -53,9 +53,6 @@ namespace X86ISA
     //are used.
     using namespace LittleEndianGuest;
 
-    // X86 does not have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
     const Addr PageShift = 12;
     const Addr PageBytes = ULL(1) << PageShift;
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d8793426b..2e8ec67ae 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1277,17 +1277,6 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                 break;
             }
 
-            if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
-                // Walk past any annulled delay slot instructions.
-                Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
-                while (fetchAddr != pcAddr && blkOffset < numInsts) {
-                    blkOffset++;
-                    fetchAddr += instSize;
-                }
-                if (blkOffset >= numInsts)
-                    break;
-            }
-
             MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
             decoder[tid]->moreBytes(thisPC, fetchAddr, inst);