diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/alpha/AlphaTLB.py | 5 | ||||
| -rw-r--r-- | src/arch/mips/MipsTLB.py | 4 | ||||
| -rw-r--r-- | src/arch/sparc/SparcTLB.py | 5 | ||||
| -rw-r--r-- | src/arch/x86/X86TLB.py | 4 | ||||
| -rw-r--r-- | src/sim/BaseTLB.py | 33 | ||||
| -rw-r--r-- | src/sim/SConscript | 1 |
6 files changed, 47 insertions, 5 deletions
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py index 7cfb549f3..099327470 100644 --- a/src/arch/alpha/AlphaTLB.py +++ b/src/arch/alpha/AlphaTLB.py @@ -28,7 +28,10 @@ from m5.SimObject import SimObject from m5.params import * -class AlphaTLB(SimObject): + +from BaseTLB import BaseTLB + +class AlphaTLB(BaseTLB): type = 'AlphaTLB' abstract = True size = Param.Int("TLB size") diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py index 0054acae5..41d46c572 100644 --- a/src/arch/mips/MipsTLB.py +++ b/src/arch/mips/MipsTLB.py @@ -32,7 +32,9 @@ from m5.SimObject import SimObject from m5.params import * -class MipsTLB(SimObject): +from BaseTLB import BaseTLB + +class MipsTLB(BaseTLB): type = 'MipsTLB' abstract = True size = Param.Int("TLB size") diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py index 20672a24e..6758d612a 100644 --- a/src/arch/sparc/SparcTLB.py +++ b/src/arch/sparc/SparcTLB.py @@ -28,7 +28,10 @@ from m5.SimObject import SimObject from m5.params import * -class SparcTLB(SimObject): + +from BaseTLB import BaseTLB + +class SparcTLB(BaseTLB): type = 'SparcTLB' abstract = True size = Param.Int("TLB size") diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index c20566efb..d5ae95372 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -54,10 +54,10 @@ # Authors: Gabe Black from MemObject import MemObject -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * from m5 import build_env +from BaseTLB import BaseTLB if build_env['FULL_SYSTEM']: class X86PagetableWalker(MemObject): @@ -66,7 +66,7 @@ if build_env['FULL_SYSTEM']: port = Port("Port for the hardware table walker") system = Param.System(Parent.any, "system object") -class X86TLB(SimObject): +class X86TLB(BaseTLB): type = 'X86TLB' abstract = True size = Param.Int("TLB size") diff --git a/src/sim/BaseTLB.py b/src/sim/BaseTLB.py new file mode 100644 index 000000000..9aca4a97c --- /dev/null +++ b/src/sim/BaseTLB.py @@ -0,0 +1,33 @@ +# Copyright (c) 2008 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.SimObject import SimObject + +class BaseTLB(SimObject): + type = 'BaseTLB' + abstract = True diff --git a/src/sim/SConscript b/src/sim/SConscript index 3e6adb85a..7acf4e9b6 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -30,6 +30,7 @@ Import('*') +SimObject('BaseTLB.py') SimObject('Root.py') SimObject('System.py') SimObject('InstTracer.py') |